JPH0529964A - Data error correction decoding method and device thereof - Google Patents

Abstract

PURPOSE: To provide the decoding method and its device of improved CIRC. CONSTITUTION: The first errors of C1 and C2 sequences are corrected and 28 symbol data of the error correction result of the C2 sequence are interleaved again. The error of the second C1 sequence is corrected with four symbol data of P parity, which is obtained by delaying 28 interleaved symbol data. 28 symbol data being the error correction result of the second C1 sequence are de- interleaved again and the error of the second C2 sequence is corrected with four symbol data of Q parity. Thus, the error of two symbols can be corrected with the first C1 sequence, four symbols with the first C2 sequence, four symbols with the second C1 sequence and four symbols with the second C2 sequence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction method and apparatus for a digital signal processing apparatus, and more particularly to an improved CIRC (Circular Interleave Reed-solomon Code) decoding method and apparatus.

[0002]

2. Description of the Related Art Digital signal processing apparatus, such as CDP
In (Compact Disc Tape player) or the like, CIRC is used as an error correction method for correcting an error due to a scratch or the like that exceeds a permissible range that occurs during the manufacturing process or use of a recording medium such as an optical disk or a magnetic tape. The CD type CIRC is a combination of a Reed-solomon code, which is an error correction code having a high correction ability for random errors, and a cyclic interleave method for converting a bust error into a random error by interleaving. That is, in the CD system, 6 samples of L / R channels, that is, 12 samples of audio signals displayed by so-called 16 bits are formed in one unit, and each 16-bit data is divided into upper 8 bits and lower 8 bits, and each Bit data is treated as one symbol (or word). Therefore, 12 samples are formed by 24 symbols. Data of sample times that are even from the beginning of such 24-symbol data are delayed by two words, and then the 24-symbol data are crossed so that adjacent data are arranged at regular intervals. The first error correction code C ₂ is constructed from the 24-symbol data which is crossed and arranged in this way. This C ₂ has n = 28,
It is a Reed-Solomon code with k = 24 and a redundancy of 4, and the minimum distance is 5. The parity of C ₂ is designated as Q. The first check word string, that is, the Q parity which is 4 symbol data is arranged in the center of 24 symbol data. Then, 4 symbols of P parity and a total of 28 symbol data of 24 symbol data are interleaved by delaying different amounts of difference for each symbol. The differential delay is 1 in sequence from the second symbol data excluding the first symbol data in a basic unit with a constant delay amount D of 4 words.
D, 2D, 3D, 4D ... 26D and 27D delay the difference equally. 28 thus delayed by the difference
A second error correction code C ₁ is constructed from the symbol data. This C ₁ is a Reed-Solomon code with n = 32, k = 28 and a redundancy of 4. The minimum distance is 5. C
The parity of ₁ is P. The second check word string, that is, the P parity of 4 symbol data is arranged next to the last symbol data of 28 symbol data. Then, the even-numbered symbol data is delayed by one word to generate a total of 32 symbol data, thereby completing the encoding. The 32-symbol data encoded by the CIRC in this way corrects and restores the error detected by the P / Q parity while processing the symbol data in the reverse order of encoding by the CIRC recorder. Therefore, the conventional C
In the IRC decoder, only the errors within the error correction capability of the C ₁ and C ₂ sequences are corrected. That is, the correction capability of the C ₁ sequence with the minimum distance of 5 is up to 2 symbols, and the correction capability of the C ₂ sequence with the minimum distance of 5 is up to 4 symbols using the error detection and correction results of the C ₁ sequence. it can.

[0003]

However, if a large amount of error data exists on the optical disk, there will be error data that cannot be corrected by the C ₁ and C ₂ error correction capabilities. Therefore, due to uncorrected error data, data different from the original data can be obtained.
Noise is generated in the audio signal reproduced from the obtained data.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data error correction method and an apparatus therefor having a significantly improved error correction capability in order to solve the above-mentioned problems of the prior art.

[0005]

In order to achieve the above-mentioned object, an error correction decoding method of the present invention comprises a data word string corresponding to a number of parallel channels and a first check word string generated from the data words. And a second checkword sequence generated from the dataword sequence and the first checkword sequence, and a data error device for decoding and error-correcting a data sequence in which the respective words are interspersed in the middle by a Reed-Solomon code. Receiving the data sequence in parallel on a number of channels equivalent to the data sequence each time, and first decoding by the first syndrome generated by the received second checkword sequence. Generated error-corrected data word string and first check word string every time Reordering the first decoded and error-corrected data word sequence and the first checkword sequence with different delay times, and the first checkword sequence generated by the reordered first checkword sequence. Generating a second decoded and error-corrected data word sequence each time with 2 syndromes;
A step of restoring the second decoded and error-corrected data word sequence and the first and second checkword sequences to the alignment state before the rearrangement; A process of generating a data word sequence and a first check word sequence which are first decoded and error-corrected again by the third syndrome, and the generated data word sequence and the first check word sequence are delayed by the difference. At least one or more of a process of rearranging again in time and a process of again generating a second decoded and error-corrected data word sequence again by the fourth syndrome generated by the rearranged first check word sequence. Repeated steps and error correction by second decoding again at least once Characterized by comprising the step of outputting each time a data word sequence into multiple parallel on the channel.

The error correction decoding device according to the present invention comprises a data word string corresponding to a number of parallel channels, a first check word string generated from the data word string, the data word string and the first check word string. In a data error correction device for decoding and error-correcting a data string which is composed of a second check word string generated by the above-mentioned word and in which each word is cross-intermediately inserted by Reed-Solomon code, the data string is distributed over a plurality of equal channels. Input means for inputting the data string each time in parallel, and decoding the data string input through the input means to again decode the first string by the first syndrome generated by the second check word string. Error-corrected data word sequence and first checker A first decoder for generating a read sequence every time, a first delay means for rearranging a data word sequence and a first checkword sequence output from the first decoder with different delay times, and the first delay means. The data word sequence and the first check word sequence rearranged by the above are decoded, and the second decoded and error-corrected data word sequence is generated every time by the second syndrome generated by the first check word sequence. Before rearranging the second decoder, the data word string and the first checkword string output from the second decoder, and the second checkword string output from the first decoder by the first delay means. Second delay means for restoring to the array state, and the data word restored and arrayed by the second delay means. A column and the first and second checkword sequences are decoded to generate a dataword sequence and a first checkword sequence which are first decoded and error-corrected by the third syndrome generated by the second checkword sequence. 3rd to do
A decoder, a third delay means for rearranging the data word sequence and the second checkword sequence outputted from the third decoder with the different delay time, and the data rearranged by the third delay means. A fourth decoder for decoding a word string and a first check word string to generate a data word string which is second-decoded and error-corrected again by the fourth syndrome generated by the first check word string; It is characterized in that it is provided with an output means for outputting the data word string outputted from the fourth decoder to a plurality of parallel channels every time.

[0007]

By operating the data error correction decoding device of the present invention described in claims 2 to 5 according to the method described in claim 1, the error correction capability is improved in proportion to the number of repetitions. To be done.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings.

First, in order to understand the present invention, a conventional CIR is used.
The C decoding method will be described with reference to FIGS. 1 and 2.

FIG. 1 is a system diagram showing a conventional CIRC decoding device.

In FIG. 1, 32 symbol data, which is represented by W, P and Q, that is, a data string is a signal picked up from an optical disk and demodulated. The 24-symbol data labeled W, that is, the data word string is audio data, and P and Q are the parity data for error detection and correction, that is, the first and second check word strings. The 32 symbol data is supplied to the CIRC decoder. The CIRC decoder includes an input means 11, ie, a descramble means 11a and an inverter means 11b, a first decoder, ie, C ₁ decoding means 12, a first delay means, ie, deinterliving means 13, and a second decoder, ie, C ₂ It is composed of a decoder 14 and an output means, that is, a reverse crossing time delay means 15. The descramble means 11a delays the even-numbered symbol data from the beginning one word at a time in order to descramble the scrambled 32 symbol data which is composed of 16 1-word delay lines. That is, since the size of the pit formed on the optical disc in the CD system is within 8 bits, the signal processing unit is 8 bits = 1 symbol data, and therefore the error due to the scratch of the optical disc is almost 1 symbol unit. If there is a scratch between symbols, there will be an error of 2 symbols. Therefore, in order to disperse such continuous errors, a delay is performed in symbol units, which is scramble processing, and at the time of reproduction, descramble processing is performed to cancel the scramble processing. The inverter means 11b inverts 4 symbol data of Q parity and 0 and 1 of 4 symbol data of P parity. This is a part of measures against fixed patterns and bust errors during encoding.
This is for restoring the data obtained by inverting 0 and 1 of the 8-symbol data of Q.

The C ₁ decoding means 12 uses the P parity 4 symbol data out of the 32 symbol data and the remaining 2
A bust error of 8-symbol data is detected and a random error is also corrected. At this time, the error correction generates four syndromes by the parity check matrix, that is, the Reed-Solomon code, and the syndrome has only the correction capability for one symbol. When two or more symbol errors occur, it is determined that the data block cannot be error-corrected, and 28-symbol data is transmitted to the next end without being corrected. Here, the indicator (minimum 1-bit reduction) is added to all the words in the data string so as to indicate the presence or absence of an error.

The deinterleaving means 13 delays the 28-symbol data transmitted from the C ₁ decoding means 12 by equal delay and cancels the interleaving. That is, most of the errors that occur during reproduction of an optical disk are regarded as scratches, dust, and dirt, but once a defect occurs, many symbols that are in close proximity are uniformly damaged. If many symbols are damaged in the same data block, error detection and correction becomes impossible. Therefore, at the time of recording, the symbols in the same data block are dispersed and recorded in other data blocks, and at the time of reproduction, the dispersed symbols are restored to the original data block positions. This restoration process is deinterleaving.

The deinterleaving means 13 includes 27D, 26D and 2D for delaying 28 symbol data by a constant difference.
A delay line having another delay time of 5D ... 2D, 1D (D is a basic unit of a constant delay amount of 4 words) and is composed of the first to 27th transmission channels.

The C ₂ composite means 14 is deinterleaved, ie all 28 data words are identically 27.
Of the 28 symbol data delayed by the D delay time and restored to the original data block position, 4 of Q parity
Reed-Solomon code and input 2 using symbol data
4 syndromes are generated from 8 words and a maximum of 4 symbol errors are corrected. Here, the markers for the words whose error has been corrected are erased, but the markers for the error words that cannot be corrected are not erased.

The reverse crossing time delay means 15 crosses each other in order to restore the original position in the 24 symbol data block supplied from the C ₂ decoding means 14, and the adjacent symbol data on the time axis of the encoding. The symbol data not subjected to the 2-word delay processing is subjected to the 2-word delay processing in order to restore the data dispersed by the 2-word delay processing to the original position. This delay processing is to prevent uncorrectable error data from being continuously output during reproduction.

A memory such as a RAM is used to perform the above conventional CIRC decoder. FIG. 2 shows the memory use locations of the C ₁ and C ₂ sequences for CIRC decoding. The memory has a symbol address of 0 to 31 and a block address of n to n-108. The C ₁ decoding means 12 takes the symbol data existing in the memory location shown in the following <Table 1> to take the descrambled 32 symbol data from the scrambled 32 symbol data. Then, the C ₂ decoding means 14
Takes the symbol data present in the memory locations shown in Table 2 below to take the deinterleaved 28 symbol data from the interleaved 28 symbol data. Also, the CIR obtained by cross-delaying the 24-symbol data in the memory locations shown in Table 3 below.
It is provided as the final decoding output of C.

[0018]

[Table 1]

[0019]

[Table 2]

[0020]

[Table 3]

[0021] However, the conventional CIRC decoding process as described above, a number of errors exceeding the error correction capability of the C ₁ and C ₂ series since the respective error correction by a single C ₁ sequence and the C ₂ sequence When data occurs, the error is not corrected and is played back as audio. Therefore, there is a problem that the quality of the reproduced audio signal is deteriorated due to the generation of noise due to an uncorrected error.

The CIRC decoding method of the present invention, which has been improved to solve the problems of the prior art, remarkably improves the error correction capability by performing the error correction of the C ₁ and C ₂ sequences twice or more. It is to improve. That is, after the first error correction of the C ₁ and C ₂ series is performed, the 28-symbol data of the error correction result of the C ₂ series is re-interleaved, and then the interleaved 28-symbol data is delayed. The error correction of the second C ₁ series is performed with the 4-symbol data. After deinterleaving the 28-symbol data of the error correction result of the second C ₁ series again, the error correction of the second C ₂ series is performed with the 4-symbol data of Q parity. Therefore, two symbols in the first C ₁ sequence, the second C ₁ sequence with four symbols of four symbols in the first C ₂ sequence, an error of the second C ₂ sequence with 4 symbols can be corrected.

As shown in FIG. 3, the CIRC decoding system of the present invention has an input means 11, ie, a descrambling means 11a and an inverter means 11b, a first decoder, ie, a first C ₁ decoding means 12, and a first delay. means, namely a first deinterleaving means 13, a second decoder, namely a first 1C ₂ decoding unit 14, the second delay means, i.e. the interleaving unit 16, a third decoder, that is, the second 2C ₁ decoding unit 17, A third delay means, namely a second deinterleaving means 18, a fourth decoder,
That is, it is composed of the _second C ₂ decoding means 19 and the output means, that is, the cross delay processing means 15. The same parts as those in FIG. 1 are designated by the same reference numerals. The input unit 11 inverts a plurality of delay lines for delaying word data received through odd-numbered channels of the plurality of channels to a delay time of one word, and the first and second check word strings. It is equipped with a large number of inverters. That is, the improved CIRC decoder of the present invention provides error correction for the first C ₁
And C ₂ decoding means 12, 14, and then the first C ₂
The second delay means 16 for restoring the 24-symbol data of the decoding means 14 and the first and second check word sequences to the arrangement state of the data sequence input to the first delay means 13.
To enter. In the second delay means 16, in order to re-interleave the 28-symbol data, 1D from the second transmission channel excluding the first transmission channel,
27D for delaying the four checkword strings supplied from the first C ₂ decoding means 14, which are composed of delay lines having delay amounts of 2D, 3D ... 26D and 27D.
The delay amount of the delay line constitutes the 29th to 32nd channels. 32 data string again interleaved by the second delay unit 16, through the same error correction process and a method of de-coded in the 1C ₁ decoding unit 12 described above to correct the error is error corrected by the 2C ₁ decoding unit 17 , The error presence / absence indicator is applied to all the words. The output data string of the second C ₁ decoding means 17 is deinterleaved again by the third delay means 18. The deinterleaved output data string of the third delay means 18 is supplied to the _second C ₂ decoding means 19. Second C ₂ decoding means 1
In 9, the input data string is error-corrected and output in the same process as the first C ₂ decoding means 14 described above. The output data string of the _second C ₂ decoding means 19 is output to the final error-corrected data word string through the output means and the anti-crossing delay means 15. The output unit 15 crosses a plurality of output channels to rearrange the data word sequence output from the fourth decoder into an array of 6 channels and 4 periods in an array of 8 channels and 3 periods, and 8 of each period. A plurality of delay lines are provided to delay each of the 5th to 8th channels by a delay time of 2 words. The input means, the first, second and third delay means and the output means are each assigned a predetermined area in one RAM.

The CIRC decoding system according to the present invention in FIG. 3 doubles the capacity of the buffer memory as shown in FIG. 4, and designates the symbol and block addresses as shown in Table 4 below. Thus, the error correction of C ₁ and C ₂ can be repeated twice.

[0025]

[Table 4]

[0026]

Therefore, in the CIRC decoding system according to the present invention, the required memory is 3456 × 8 bits = 27648 bits because 32 symbol data × 27D = 3456 symbol data can be reproduced. By the way, the buffer memory has a capacity of 55 for decoding the C ₁ and C ₂ sequences twice.
296 (= 27648 × 2) bits, that is, 64K RAM
Is possible by using. In the present embodiment, description has been given by taking the case of repeating twice as an example, but it can be expanded by providing an additional memory for repeating three times, repeating four times, and so on. Be improved error correction capability in proportion to the number of repetitions in the case of repeated error correction twice or more C ₁ and C ₂ sequence as compared with the case where the error correction of one C ₁ and C ₂ sequence I understand.

[Brief description of drawings]

FIG. 1 is a system diagram of a conventional CIRC decoder.

FIG. 2 shows C ₁ and C in the CIRC decoder of FIG.
₃ is a view showing memory use positions of _two series.

FIG. 3 is a system diagram of a CIRC decoder according to the present invention.

FIG. 4 is a diagram showing the first C in the CIRC decoder of FIG.
_{3 is} a diagram showing memory use positions of ₁ , 1C ₂ , 2C ₁ and 2C ₂ series.

Claims (5)

[Claims] 1. A data word string corresponding to a number of parallel channels, a first checkword string generated from the data word string, and a second checkword string generated from the data word string and the first checkword string. In the error correction method of the data error device, wherein the data string in which each word is cross-intermediately inserted is decoded with a Reed-Solomon code to perform error correction, in each of a plurality of channels equivalent to the data string in parallel. Inputting a data sequence, generating a first decoded and error-corrected data word sequence and a first checkword sequence each time by the first syndrome generated by the received second checkword sequence, and The first decoded and error-corrected data word string and the first string Rearranging the check word sequence with different delay times, and each time generating a second decoded and error-corrected data word sequence by the second syndrome generated by the rearranged first check word sequence. A step of restoring the second decoded and error-corrected data word sequence and the first and second checkword sequences to the arrangement state before the rearrangement; Generating a data word sequence and a first checkword sequence which are first decoded and error-corrected again by the generated third syndrome, and delaying the generated dataword sequence and the first checkword sequence by the difference. The process of re-arranging in time and the re-arrangement of the first check word sequence Repeating the process of generating the second decoded and error-corrected data word string again at least once by the fourth syndrome, and the second decoded and error-corrected data word string at least once more A method of correcting data error, comprising the step of outputting each of them on a large number of parallel channels. 2. A data word string corresponding to a large number of parallel channels, a first check word string generated from the data word string, and a second check word string generated from the data word string and the first check word string. In a data error correction device that performs error correction by decoding a data string in which each word is inserted in the middle of a cross with a Reed-Solomon code, the data string is paralleled every time on a number of channels equivalent to the data string. Input means for inputting; a data word string which is first decoded and error-corrected by the first syndrome generated by the second check word string by decoding the data string input through the input means; A first decoder for generating a first checkword sequence each time; First delay means for rearranging the data word sequence and the first check word sequence outputted from one decoder with different delay times; the data word sequence rearranged by the first delay means and the first check A second decoder that decodes a word string to generate a data word string that is secondly decoded and error-corrected by the second syndrome generated by the first check word string, and is output from the second decoder. A second data word sequence and a first check word sequence, and a second sequence for restoring the second check word sequence output from the first decoder to the alignment state before being rearranged by the first delay means.
Delay means, and a third word generated by the second checkword string by decoding the data word string and the first and second checkword strings restored and arranged by the second delay means.
A third decoder that generates a data word sequence and a first check word sequence that are first decoded and error-corrected again by the syndrome, and the data word sequence and the second check word sequence output from the third decoder are different from each other. Third delay means for rearranging with a delay time of, and the data word sequence and the first checkword sequence rearranged by the third delay means are decoded and generated by the first checkword sequence. A fourth decoder that generates a data word string that is second-decoded and error-corrected again by the fourth syndrome, and an output unit that outputs the data word string output from the fourth decoder to a large number of parallel channels each time. A data error correction decoding device comprising. 3. The input means includes a plurality of delay lines for delaying word data received through odd-numbered channels of the plurality of channels with a delay time of one word, and the first and second checkwords. The data error correction decoding apparatus according to claim 2, further comprising a plurality of inverters for inverting the columns. 4. The output means intersects a plurality of output channels in order to rearrange the data word sequence output from the fourth decoder in an array of 6 channels and 4 periods in an array of 8 channels and 3 periods, and 4. The error correction decoding apparatus according to claim 3, further comprising a plurality of delay lines for delaying the 5th to 8th channels among the 8 channels of the cycle with a delay time of 2 words. 5. The error correction decoding apparatus according to claim 2, wherein the input means, the first, second and third delay means and the output means are respectively allocated to a predetermined area in one RAM.