JPH07211014A - Error correction code-coding method, error correction code-decoding method, error correction code-coding apparatus, error correction code-decoding apparatus, digital signal-coding method, digital signal-decoding method, digital signal-coding apparatus, digital signal-decoding apparatus and recording medium - Google Patents

Abstract

PURPOSE:To enhance a coding efficiency and improve an error correction efficiency while sharing part of a recording system circuit and a reproducing system circuit of a conventional coding method, by extending code lengths of C1 and C2 codes. CONSTITUTION:A coding circuit for coding an error correction code of the apparatus adds C2 and C1 parities of 12 bytes to the actual data of 104 bytes, thereby outputting a C1 code of a data length of 128 bytes. The C1 code is divided every 32 bytes into four frames. The number of bytes of one frame becomes equal to that in a present CD format. A sub code of one byte and a frame synchronous signal are added to each of the four frames, which is a C1 code of an error correction code. 20 C1 codes are collected to form one sector (of 80 frames). In this manner, while a frame length is maintained the same as the CD standard, code lengths of C1 and C2 codes are extended in comparison with the code length of the CD standard, so that a coding efficiency and an error correction efficiency are improved.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology (FIGS. 5 to 9) Problems to be Solved by the Invention Means for Solving Problems (FIGS. 1 to 4) Action Example (FIGS. 1 to 4) (1) Data Format (FIG. 1) (2) Recording medium (3) Recording device (FIG. 2) (3-1) Configuration of error correction code encoding circuit (FIG. 3) (3-2) Encoding process (4) Reproducing device (FIG. 2) (4-1) Configuration of error correction code decoding circuit (FIG. 4) (4-2) Decoding process (5) Other embodiment Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction code coding method, an error correction code decoding method, an error correction code coding apparatus, an error correction code decoding apparatus, a digital signal coding method, a digital signal decoding method, Regarding a digital signal encoding device, a digital signal decoding device and a recording medium,
In particular, the present invention is suitable for application to a device for recording or reproducing data whose data structure partially matches a data format of a compact disk (hereinafter referred to as CD).

[0003]

2. Description of the Related Art When reproducing a digital signal, the recorded codes ("0" and "1") may not be correctly read due to a problem that occurred during recording or a problem that occurred during reproduction. Therefore, it is common to record an error correction code in which parity is added to the digital signal so that the error can be corrected during reproduction. By adding parity bit in this way, even if a code error occurs, the digital signal at the time of recording can be restored within the range of the correction capability.

Code errors include a random error having a relatively short length and a burst error having a relatively long length. Of these, a Reed-Solomon is used as an error correction code having an improved correction capability for random errors. The code is known. Further, in order to enhance the error correction capability for burst errors, a method called interleaving in which block data to be encoded is rearranged irrespective of the temporal arrangement of data to be recorded is used. In this method, burst errors are converted into random errors and then encoded.

For example, in a compact disk (hereinafter referred to as a CD) or the like, a CIRC (Cross In
An error correction code called terleave Reed-Solomon Code) is used. This CIRC is a combination of two-stage Reed-Solomon codes via interleaving.

The two-stage Reed-Solomon code is C1
It is called a code and a C2 code, and [code length,
Dimension, minimum distance] is [32, 28, 5] and [28, 24, 5]
Is defined in. Here, the dimension represents the number of information symbols, and the minimum distance is a parameter representing the correction capability. In the case of this example, since the minimum distances are both 5, it is possible to perform error correction with a maximum of 2 symbols or erasure correction with a maximum of 4 symbols.

The function of this CIRC can be divided and considered as shown in FIG. Here, FIG. 6 is a detailed representation of the CIRC encoding system 1, and FIG. 7 is a detailed representation of the decoding system 11. First, a conventionally used CIRC coding system 1 will be described with reference to FIG.

In the CIRC encoding system 1, 6 samples (L0 to L5, R0 to R5) of each LR channel of digital audio data are input in parallel as one unit. That is, the encoding system 1 has 16 bits × 2 × 6.
Input the data of 192 bits (24 bytes).

The even-numbered sample delay circuit 2 outputs the data of the even-numbered samples of the data of each of 6 samples by 2 respectively.
Delay by symbols. This is to make it possible to supplement the data by interpolation even when all the corresponding sequences become erroneous in the C2 code decoding circuit.

Next, the scramble circuit 3 inputs from the even sample delay circuit 2 and scrambles the data to rearrange the order of the data. By this scrambling, the maximum burst error interpolation length can be obtained. The C2 code encoding circuit 4 encodes the scrambled data into a C2 code. As a result, the 4-symbol-length parity Q is added to the 24-symbol data. This makes the data length 28 bytes.

The interleave circuit 6 sets the interleave length D to 4 and applies interleave with a maximum delay of 108 frames. The C1 code encoding circuit 25 encodes the C1 code. As a result, the parity P having a 4-symbol length is added to the 28-symbol data. This makes the total data length 32 bytes.

Then, the odd-numbered symbol delay circuit 7 delays only the odd-numbered symbols by one symbol. This is so that when a random error occurs over two symbols, the effect thereof affects only one symbol in one C1 code and C2 code sequence.

The parity reversing circuit 8 inverts the polarity of the parity. This is because all the data may become 0 due to a burst error or the like, and at this time, if the parity is not reversed, this cannot be determined as an error. A CIRC coded output can be obtained by a series of these processes.

Next, a decoding system 11 using CIRC is shown in FIG.
Will be explained. Decoding is performed by the reverse procedure of encoding. First, the decoding circuit inputs data for one frame (32 symbols) in parallel. The even-numbered symbol delay circuit 12 delays the even-numbered symbols by one symbol.

The parity reversing circuit 13 inverts the parity. The C1 code decoding circuit 14 decodes the C1 code.
As a result, the parity P having a length of 4 symbols is removed from the data of 32 symbols. This gives a data length of 28 bytes. The deinterleave circuit 15 restores the interleave. The C2 code decoding circuit 16 decodes the C2 code. As a result, the parity Q having a 4-symbol length is removed from the 28-symbol data. This gives a data length of 24 bytes.

The descramble circuit 17 descrambles. Here, the odd sample delay circuit 18 delays the odd-numbered samples by two symbols. As a result, 24 bytes of data for one frame can be output. As described above, CIRC is an error correction code effective for both random errors and burst errors.

FIG. 8 is a diagram in which the functional block of the CIRC having the recording system and the reproducing system shown in FIGS. 6 and 7 is rewritten centering on the signal format layer portion of the CD. C
D is recorded by the data format shown in FIG.
This format is called a sub-coding format. FIG. 9B shows the sector structure.

Therefore, in the case of a CD, digital data is encoded by the CIRC encoding circuit 21 having the same circuit configuration as the encoding system 1 shown in FIG. A subcode is added to the converted data. This subcode is used to find the beginning of a song. Incidentally, among these subcodes, sync signals S0 and S1 for identifying the head of the sector are recorded in the subcodes of the first and second frames, which are the head positions of the sectors.

In this sub-coding frame format, 98 frames are regarded as one block, which is called a sector. 24 bytes of digital data are assigned to one frame. Therefore, 23 in one sector
Data of 52 bytes (= 98 frames × 24 bytes) are included.

When the addition of the sub-code is completed, the processing circuit 23 adds a frame synchronization signal to the data of each frame and further executes various processing such as EFM (Eight To Fourteen) modulation. A CD is manufactured by recording the data to which the series of processes have been applied to the recording medium 24.

On the other hand, the CD reproducing apparatus reads the data recorded on the recording medium 24 through an optical system such as an optical pickup and supplies it to the processing circuit 25. The processing circuit 25 detects the frame synchronization signal from the read data and outputs the EF.
Various processes such as demodulation based on M modulation are executed.

The data output from the processing circuit 25 is input to the subcode separation circuit 26 and the subcodes are separated. After that, the digital data is decoded by the CIRC decoding circuit 27 having the same circuit configuration as the decoding system 11 shown in FIG.

[0023]

As described above, the CIRC is used.
The error correction code, which is called, is an error correction code effective for both random error and burst error. However, if signals are recorded at a high density, random errors and burst errors are inevitably inevitable, and it becomes easy to make uncorrectable and erroneous corrections.

Therefore, it is conceivable to add a lot of parity as the inspection data in order to reproduce the signal while keeping the error rate of the signal low while recording the signal at a high density. In this case, the original information can be efficiently used. There is a problem that it cannot be encoded.

Similarly, in order to reproduce the signal while keeping the error rate low while recording the signal at a high density, a powerful error correction capability that is completely different from the conventional encoding and decoding methods using CIRC is provided. It is conceivable to use the existing method. Further, a method of using a sector structure, a modulation method or the like which is completely different from the CD format can be considered. However, it is necessary for the reproducing system to be able to read the signals recorded by the conventional CD format.

This is because when data is recorded on the recording medium 24 by a new sector structure or modulation method which is completely different from the conventional CD format, in addition to the processing circuit and sub-code separation circuit provided in the preceding stage of the error correction code decoding circuit, This is because it is necessary to newly provide a circuit group suitable for a new recording method such as a device that reads data from a recording medium, and the circuit scale of the reproducing system becomes very large. For the same reason, the recording system is inevitably large in circuit scale.

The present invention has been made in consideration of the above points, and has high coding efficiency and error correction capability while partially sharing a circuit of a recording system and a reproducing system of a conventional coding system. In addition to the excellent error correction code coding method and its error correction code decoding method, the error correction code coding apparatus and the error correction code decoding apparatus, and the digital signal coding method and decoding method using these It is a proposal.

[0028]

In order to solve the above problems, in the present invention, the digital data is converted into first and second error correction codes (C1) having a code length and a check data length defined in the compact disk standard. Code and C2 code), an error correction code encoding method in which the error correction capability is improved by encoding the product code of the frame length to the same size as the data length defined in the compact disk standard. The second error correction code (C2
The code length of the first error correction code (C1 code) is set to the code length defined by the compact disk standard after the code length of the code) is extended and encoded with respect to the code length defined by the compact disk standard. On the other hand, it is expanded to a constant multiple and encoded.

Further, in the present invention, the error for decoding the transmission data transmitted as the product code of the first and second error correction codes (C1 code and C2 code), which have their own code length and check data length, respectively. In the correction code decoding method, at the time of decoding, the transmission data is fetched for each constant multiple of the frame length defined by the compact disk standard, and the code length is compared with the code length defined by the compact disk standard. The first error correction code (C1 code), which is expanded by a constant multiple, is decoded based on the first check data (C1 parity) having the data length expanded according to the constant multiple, and The second error correction code (C2 code) whose code length is expanded according to the code length of the error correction code (C1 code) is used as a second detection code having a data length expanded according to a constant multiple. Decoding based on data (C2 parity).

Further, in the present invention, the digital data is coded as a product code of the first and second error correction codes (C1 code and C2 code) having the code length and the check data length defined by the compact disk standard. In the error correction code encoding method that improves the error correction ability by converting the digital data into multiple frames while maintaining the same frame length as the data length defined in the compact disk standard during encoding. By adding the second check data (C2 parity) extended to the data length defined as the compact disk standard, the second error correction extended to the code length defined as the compact disk standard. A process for obtaining a code (C2 code), a process for interleaving the second error correction code (C2 code), By adding the first check data (C1 parity) whose data length is extended to the data length defined in the compact disk standard to the second error correction code (C2 code) after the leave processing , A process for obtaining a first error constant code (C1 code) whose code length is extended by a constant multiple with respect to the code length defined in the compact disc standard.

Further, in the present invention, the error for decoding the transmission data transmitted as the product code of the first and second error correction codes (C1 code and C2 code), which have their own code length and check data length, respectively. In the correction code decoding method, at the time of decoding, the process of capturing the transmission data for each constant multiple of the frame length defined by the compact disk standard and the extension of the captured data according to the constant multiple are performed. The first inspection data (C1
Parity) to decode a first error correction code (C1 code) whose code length is a constant multiple of the code length defined in the compact disk standard, and A process of deinterleaving the transmission data decoded based on the first check data (C1 parity), and a second process of expanding the transmission data after the deinterleaving process by a constant multiple.
Of the second error correction code (C2) whose code length is extended according to the code length of the first error correction code (C1 code) by decoding based on the check data (C2 parity) of
2 code) is decoded.

Further, in the present invention, even sample delay means 35 for delaying and outputting even sample data of digital data inputted in parallel by a predetermined amount, and
A scramble means 36 for rearranging the order of the data input from the even-numbered sample delay means 35, and digital data for a plurality of frames input from the scramble means 36 for the data length defined in the compact disk standard. By adding the second check data (C2 parity) whose length is extended, the second error correction code (C2 parity) is added.
A second coding means 37 for generating a code), an interleaving means 38 for rearranging and outputting the time sequence of the second error correction code (C2 code) input from the second coding means 37, and an interleave. The first inspection data (C) in which the data length is extended from the data length defined in the compact disc standard to the digital data input from the means 38
1 parity) to generate a first error correction code (C1 code) having a code length that is a constant multiple of the code length defined in the compact disc standard.
9 and the odd symbol delay means 40 for delaying and outputting the data of the odd number symbols of the first error correction code (C1 code) output from the first encoding means 39 by a predetermined amount.
And parity inversion means 41 for inverting the polarities of the second and first check data (C2 parity and C1 parity) included in the error correction code output from the odd symbol delay means 40.

Further, according to the present invention, the even-numbered symbol delay means 45 for delaying and outputting the even-numbered symbol data out of the transmission data for a plurality of frames by a predetermined amount, and the data input from the even-numbered symbol delay means 45 are included. First
And a parity inversion means 46 for inverting and outputting the polarities of the second inspection data (C1 parity and C2 parity).
And the transmission data input from the parity reversing means 46 is decoded by the first check data (C1 parity) whose data length is extended with respect to the data length defined in the compact disk standard. First decoding means 47 for decoding one error correction code (C1 code);
Deinterleaving means 48 for rearranging and outputting the time sequence of the transmission data input from the first decoding means 47,
The transmission data input from the deinterleaver 48 is
The second error correction code (C2 code) is decoded by decoding with the second check data (C2 parity) whose data length is extended with respect to the data length defined in the compact disk standard. 2 decoding means 49, descrambling means 50 for rearranging and outputting the transmission data input from the second encoding means 49, and odd-numbered sample data of the transmission data input from the descrambling means 50. An odd-numbered sample delay means 51 that delays by a predetermined amount and outputs the delayed sample is provided.

Further, in the present invention, a second error correction code (the second data is a digital data whose frame length is the same as that of the compact disk standard but whose code length is extended to the code length defined in the compact disk standard ( C
2 code) and a first error correction code (C1 code) whose code length is a constant multiple of the code length defined in the compact disk standard, and then a plurality of product codes The first auxiliary data is added to the data group consisting of and encoded into a sector structure data structure close to the compact disk standard.

Further, in the present invention, the digital data is defined in the compact disk standard and the second error correction code (C2 code) in which the code length is extended from the code length defined in the compact disk standard. After being encoded into a product code with a first error correction code (C1 code) in which the code length is extended by a constant multiple of the code length, the first auxiliary data is added to a data group including the plurality of product codes. Is added to encode a sector data structure close to the Compact Disc standard, and digital data is encoded with a second and first error correction code lengths defined in the Compact Disc standard. After encoding to the product code of the codes (C2 code and C1 code), the second auxiliary data is added to the data group consisting of a plurality of the product codes, and the sector of the compact disk standard And a second encoding process of encoding the granulation, to be capable of appropriately encoded by connexion digital data to the first or second encoding process.

Further, in the present invention, the digital data is extended to the code length defined in the compact disc standard, which has the same frame length as the compact disc standard and the code length is extended to several frames. Coded as a product code of the second error correction code (C2 code) and the first error correction code (C1 code) whose code length is extended by a constant multiple with respect to the code length defined in the compact disk standard. After the conversion, the first auxiliary means 32B for adding the first auxiliary data to the data group consisting of the plurality of product codes to encode into the data structure of the sector structure close to the compact disk standard, and the digital data, 2nd and 1st respectively having a code length defined in the compact disk standard
Of the error correction code (C2 code and C1 code), the second auxiliary data is added to the data group consisting of a plurality of the product codes, and the data is encoded into the sector structure of the compact disk standard. The second encoding means 32A is provided so that the digital data can be appropriately encoded by the first or second encoding means 32B or 32A.

Further, according to the present invention, after separating the first auxiliary data from the transmission data which has the same frame length as the compact disk standard and is encoded in a structure in which the code length is extended to several frames, , The transmission length is a constant multiple of the frame length defined by the compact disk standard, and the code length is expanded by a predetermined multiple of the code length defined by the compact disk standard. The error correction code (C1 code) has a first check data (C1) having a data length extended according to a constant multiple.
Parity) and the second error correction code (C2 code) whose code length is expanded according to the code length of the first error correction code (C1 code) is expanded according to a constant multiple. The first decoding process 44B for decoding based on the second inspection data (C2 parity) having a different data length
And, after separating the second auxiliary data from the transmission data encoded in the sector structure of the compact disk standard,
The transmission data is fetched for each frame length defined by the compact disk standard, and the first error correction code (C1 code) having the code length defined by the compact disk standard is first created.
And a second decoding process for decoding the second error correction code (C2 code) defined by the compact disk standard based on the second check data. Alternatively, the digital data can be appropriately decoded by the second decoding process.

Further, in the present invention, the code length is extended with respect to the code length defined in the compact disc standard while keeping the frame length the same as the data length defined in the compact disc standard. Of the error correction code (C2 code) and the first error correction code (C1 code) whose code length is a constant multiple of the code length defined in the compact disk standard. The recorded recording area is provided on the recording medium.

[0039]

The first and second error correction codes (C1 code and C
By extending the code length of each of the two codes) to the code length determined by the compact disk standard, the error correction capability can be further improved. Therefore, even if the signal is recorded at a higher density, it can be stably read.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Data Format The data format described in this embodiment has a sector structure close to that of the CD format, and all the basic parts of the error correction code encoding system and the error correction code decoding system are included. While maintaining the code length of the error correction code (C1 code) to the current C
It is a constant multiple of the code length of the D format. That is, the code length of the error correction code is extended to several frame lengths while keeping the same frame length as the current CD standard. In this section, the code length of C1 code is 4
The case of using a frame will be described as an example.

FIG. 1 shows the frame structure and sector structure of this embodiment. In the case of the present embodiment, the error correction code encoding circuit uses 12 bytes of C2 for each 104 bytes of actual data.
Parity and C1 parity are added, and a C1 code having a data length of 128 bytes is output. If we call this a data that is divided into 4 by 32 bytes,
The number of bytes per frame is the same as the number of bytes of the current CD format. The error correction code of this embodiment is obtained by adding a 1-byte subcode and a frame synchronization signal to each of these four frames.

One sector is a collection of 20 C1 codes, that is, a collection of 80 frames (= 4 × 20) converted into frames. Also, in the subcode part of the first frame and the second frame in one sector,
Sync signals S0 and S1 for identifying the head of the sector are added. Therefore, in this embodiment, the amount of data in one sector is 20.
It becomes 80 bytes (= 104 × 20). The subcode in one sector is 78 bytes ((80-2) x 1 byte).
become.

In this embodiment, the same sync signals S0 and S1 as the sync signals S0 and S1 in the CD format are used. The frame sync signal used is the same as the frame sync signal in the CD format. As described above, the length of one frame is the same, and the position of the subcode and the synchronizing signals S0 and S1 as well as the frame synchronizing signal and the modulation are exactly the same as in the case of the CD format. Therefore, the encoding circuit and the decoding circuit for the data recorded by the present format can be shared with the circuit of the CD format. This makes it possible to realize an encoding circuit and a decoding circuit without increasing the circuit scale so much.

(2) Recording medium This data format can be switched in recording medium units or partial units on one recording medium. In the recording medium used in this embodiment, in addition to the data of the CD format, the data of the data format described in the previous section is recorded in a mixed manner. Incidentally, the data format can be switched in track units. Lead-in and TO here
It is assumed that C (table of contents) is recorded by a CD format and other data is recorded by the error correction code encoding system and the subcode addition system of this embodiment.

(3) Recording Device FIG. 2 shows the overall structure of the recording device 30 and the reproducing device 31 of this embodiment. First, the recording device 30 contains the current CD format encoding circuits 32A and 33A and the format encoding circuits 32B and 33B of the present embodiment. Then, it is possible to select which of the formats is used to record the digital data by the format switching signal S1.

However, in this recording apparatus 30, the data length of one frame is the same regardless of which format is used for encoding, and the processing after adding the subcode is common.
That is, since the addition and modulation of the frame synchronization signal are common, these series of processes are shared by one processing circuit 34. This processing circuit 34 is the processing circuit 23 shown in FIG.
It has the same structure as.

Incidentally, the encoding circuit of the present CD format is CI
It is composed of an RC encoding circuit 32A and a sub code adding circuit 33A. The CIRC encoding circuit 32A has the same circuit configuration as that of FIG. 6, and the subcode adding circuit 33A also has the configuration of FIG.
It has the same circuit configuration as the sub-code adding circuit 22 shown in FIG.

(3-1) Configuration of Error Correction Code Coding Circuit On the other hand, the coding circuit of the present embodiment is composed of a dedicated error correction code coding circuit 32B and a sub code adding circuit 33B. Of these, the subcode adding circuit 33B
Is a circuit for adding a sub-code to the output data of the error correction code encoding circuit 32B encoded by the format of the present embodiment. The sub-code adding circuit 33B is designed to insert identification information into the sub-code whether it is the CD format or the format of this embodiment.

On the other hand, the error correction code encoding circuit 32B is constructed as shown in FIG. The error correction code encoding circuit 32B uses the 26 samples (L0 to L25, R0 to R25) of each LR channel as one unit.
Input byte digital data in parallel. This data amount corresponds to 4 frames.

The even sample delay circuit 35 delays the data of the even-numbered samples of the data of each of the 26 samples by 2 symbols (that is, 8 frames). This is to make it possible to supplement the data by interpolation even when all the corresponding sequences become erroneous in the C2 code decoding circuit. Then, the data is supplied to the scramble circuit 36.

The scramble circuit 36 is for four frames (104 bytes) input from the even sample delay circuit 35.
Sort the data in. At this time, the scramble circuit 36
Will output data rearranged as shown in FIG. The data output from the scramble circuit 36 is supplied to the C2 code encoding circuit 37. The C2 code encoding circuit 37 encodes 104-symbol data into a C2 code. This gives 1 to 104 symbols of data
A 2-symbol-length parity Q is added. This gives C
The code length of the two codes is 116 bytes.

The interleaving circuit 38 delays the 116-byte data input from the C2 encoding / encoding circuit 64 by 0D ', 1D', 2D ', 3D' ... 115D 'units, and interleaves them. . Incidentally, the value of D ′ is a value obtained by dividing the interleave length D by the number of frames n input at one time (= interleave length D / the number of frames n input at one time). In the case of this embodiment, the value of this value D'is 1
Since (= 4/4), interleaving is performed so that the maximum delay amount reaches 460 frames (= 115 × 4). As a result, the error correction capability for random errors is
It is improved compared to C.

The interleaved data is supplied to the C1 code encoding circuit 39. C1 code encoding circuit 39
Encodes 116-symbol data into a C1 code in which the code length is four times the code length of the conventional format. Here, the parity P having a length of 12 symbols is added, and the data length becomes 128 bytes. This data is supplied to the odd symbol delay circuit 40.

The odd-numbered symbol delay circuit 40 delays the odd-numbered symbols by one symbol (4 frames). This is because, when a random error occurs over two symbols, the influence thereof affects only one symbol in one C1 code and C2 code sequence. Then, the data is supplied to the parity reversing circuit 41.

The parity inverting circuit 41 inverts the polarity of the parity. This is because all the data may become 0 due to a burst error, etc.
This is because it is impossible to determine this as an error unless the parity is reversed at this time. By this series of processing, the error correction code encoding circuit 32B outputs four frames (128
Byte) error correction code encoded output is obtained.

(3-2) Encoding Process Next, the encoding operation by the recording device 30 will be described. First, it is assumed that the CD format is selected by the format switching signal S1. In this case, the switch of the switch circuit SW1 is switched to the CIRC encoding circuit 32A side. At this time, the digital data is input to the CIRC encoding circuit 32A in units of 24 bytes. Then, a subcode is added to the output data of the CIRC encoding circuit 32A by the subcode adding circuit 33A. This data is output to the processing circuit 34 via the switch circuit SW2, subjected to various kinds of processing such as addition of a frame synchronization signal and modulation, and sequentially recorded on the recording medium 24.

On the other hand, when the format of this embodiment is selected by the format switch signal S1, the switch of the switch circuit SW1 is switched to the error correction code coding circuit 32B side. At this time, the digital data is input to the error correction code encoding circuit 32B of this system in units of 104 bytes.

The output data coded by the error correction code coding circuit 32B is added with a subcode by the subcode adding circuit 33B of this system. Thereafter, the data is supplied to the processing circuit 34 common to both formats via the switch circuit SW2. In this way, the recording device 30 can handle any format. Moreover, the circuit scale can be minimized because the circuit for adding the frame synchronization signal can be used in common.

In the encoding system of this embodiment, the input data is 104 bytes, the parity of the C1 code is 12 bytes, and C is the parity.
The parity of 2 codes is 12 bytes, and the interleaving is every 4 frames (interleave length D = 4). Therefore, C1
The [code length, dimension, distance] of the code and the C2 code are [128, 116, 13] and [116, 104, 13], respectively. C
The code length of one code is four times the code length of the C1 code of CIRC, that is, the number of bytes in one frame.

Therefore, the actual data for one frame is 26 bytes (104/4), which is 2 bytes more than the actual data for one frame (24 bytes) in CIRC. That is, it can be seen that if data is recorded with the format of the present embodiment, the amount of recorded data for one frame is the same, but 2 bytes more information can be sent in the actual amount of data.

Incidentally, the number of code lengths and the parities of the C1 code and the C2 code, and the number of interleaving are not limited to the present embodiment. However, C
The code length of one code is an integral multiple (the value is n) of the number of bytes (32 bytes) per frame in CIRC, and the interleave length D needs to be an integral multiple of n. However, as long as that condition is satisfied, each value can be set arbitrarily according to the error correction capability and the circuit scale.

(4) Reproducing Device Next, the circuit configuration of the reproducing device 31 will be described. Playback device 31
Also, like the recording apparatus, a decoding circuit 44A for the current CD format and a decoding circuit 44B for the format of the present embodiment are built in. Then, which format is used to record the digital data, the format switching signal S
It is made possible to select by 2. However, in the case of the reproducing apparatus 31, the sub-code separation circuit is shared by both formats in addition to the frame synchronization detection circuit and the demodulation circuit. CIR corresponding to the current CD format
The C decoding circuit 44A has the same circuit configuration as that of FIG.

Next, the common circuit portion will be described. The data recorded on the recording medium 24 is input to a processing circuit 42 having the same configuration as the current CD format, and various processing such as frame synchronization detection and demodulation is executed. This processing circuit 4
2 has the same configuration as the processing circuit 25 shown in FIG. 8, and its output is output to the subcode separation circuit 43 adapted to this embodiment.

The sub-code separation circuit 43 decodes the sub-code to determine whether the reproduced data has the sector structure of the current CD format or the sector structure of the present embodiment, and by the CIRC encoding circuit 32A. It is determined whether it has been coded or coded by the error correction code coding circuit 32B of this embodiment.

Then, based on the result of the judgment, the sub-code separation circuit 43 outputs the format switching signal S2.
The switch circuit SW is activated by this format switching signal.
The switches of 3 and SW4 are switched. This switching operation controls whether the reproduction data is supplied to the CIRC decoding circuit 44A for decoding or the reproduction data is supplied to the error correction code decoding circuit 44B of this system to decode the error correction code of this embodiment.

First, when the CIRC decoding circuit 44A determines that decoding should be performed, the subcode separation circuit 43 outputs C
Data is supplied to the IRC decoding circuit 44A for each frame (32 bytes). On the other hand, when it is determined that decoding should be performed by the error correction code decoding system of this embodiment, the sub-code separation circuit 43 sends data for four frames to the error correction code decoding circuit 44B of this embodiment. (1
28 bytes) each.

(4-1) Configuration of Error Correction Code Decoding Circuit FIG. 4 shows in detail the error correction code decoding circuit of this system. The error correction code decoding system of this embodiment will be described with reference to FIG. Basically, the processing of the decoding circuit 44B is the inverse conversion of the encoding circuit 32B.

The error correction code decoding device 44B first causes the even-numbered symbol delay circuit 45 to generate four frames (128 bytes).
Enter the data of all at once. Even symbol delay circuit 72
Delays the even-numbered symbols by one symbol (4 frames). The data obtained by delaying the even-numbered symbols is supplied to the parity inverting circuit 46. The polarity inversion circuit 46 inverts the polarity of the parity.

The data output from the parity inverting circuit 46 is supplied to the C1 code decoding circuit 47. The C1 code decoding circuit 47 decodes the C1 code given to the data of 4 frames (128 symbols). This is the current CD
The parity P having a length of 12 symbols is removed from the data of 128 symbols having a code length four times that of the format, and the data length becomes 116 bytes.

Continuing, the deinterleave circuit 48 outputs C1
116 bytes of data are received from the encoding / encoding circuit 47, and 115D ′, 114D ′, and
113D '... Deinterleave processing is performed by delaying by 1D' and 0D 'units.

Incidentally, the value of D'is a number obtained by dividing the interleave length by the number of frames input at one time (= interleave length D / the number of frames input at one time), as described at the time of encoding. Given. In the case of the present embodiment, the value of D'is 1 (= 4/4). As a result, the maximum delay amount is 460
The interleave applied over the frame (= 115 × 4) is restored.

The deinterleaved data is supplied to the C2 code decoding circuit 49. C2 code decoding circuit 4
9 decodes a C2 code consisting of 116-symbol data. As a result, the parity Q having a length of 12 symbols is removed from the data of 116 symbols, and the data length becomes 104 bytes. The C2 code decoding circuit 49 supplies 104-byte data to the descramble circuit 50.

At this time, the arrangement of the data input to the descramble circuit 50 is L0, L2 ... In order as shown in FIG.
Is. The descramble circuit 50 rearranges the data of four frames (104 bytes) thus input. The rearranged data is the odd sample delay circuit 51.
Is supplied to. The odd sample delay circuit 51 delays the odd-numbered samples by 2 symbols (8 frames). In this way, the decoded output of 4 frames (104 bytes) is obtained.

(4-2) Decoding Process Next, the decoding operation of the reproducing device 31 will be described. The reproducing device 31 takes in the reproduced data from the recording medium 24 to the processing circuit 42, detects the frame synchronization signal, and demodulates the modulated data. Then, the subcode is extracted by the subcode separation circuit 43, and whether the data currently being reproduced is the data recorded by the current CD format or the data recorded by the format proposed in the embodiment. Identify.

For example, the lead-in portion of the recording medium 24 and T
It is assumed that the OC portion is recorded in the CD format and the other data areas are recorded in the format proposed in this embodiment. At this time, the subcode separation circuit 43 outputs the data corresponding to the lead-in part and the TOC part to the CIRC decoding circuit 44A one frame (32 bytes) at a time. On the other hand, the data corresponding to the other data area is output to the error correction code decoding circuit 44B of this system by 4 frames (128 bytes) at a time.

At this time, the error correction code decoding circuit 44B of this system executes the deinterleaving process of the C1 code, and further the decoding process of the C2 code. Here, the data encoded by the error correction code of this method is extended to a constant multiple (for example, four times) of the code length of the C1 code, and the data length of the C1 parity is several times (for example, three times). Has been extended). By the way, in the case of C1 parity, the error correction capability exponentially increases as the data length increases, so the code error contained in the reproduced data processed in this embodiment is lower than that recorded in CIRC.

Similarly, the code length of the C2 code is expanded to a predetermined multiple as compared with the case of CIRC, and the data length of the C2 parity is expanded in error correction capability.
The code error included in the reproduced data is further reduced as compared with the case of reproducing the data recorded by CIRC.

Furthermore, since the interleave length of the data recorded by the method of this embodiment is longer than the interleave length of 460 frames and CIRC (108 frames), the error correction capability for burst errors is also high. From these, it can be seen that when reproducing the data recorded by the format of the present embodiment, the correction ability for both the random error and the burst error is high. Therefore, a stable signal output can be obtained even if the signal is recorded at a higher density.

Further, in the format of the present embodiment, even when the code length of the C1 code is expanded to a predetermined multiple of CIRC (for example, 4 times), the data length of C1 parity is suppressed to less than that (for example, 3 times). The ratio of parity to the total amount of data can be reduced, and the actual amount of data that can be actually recorded can be increased as compared with the case of recording data by CIRC.

Further, since the reproducing apparatus 31 can discriminate the recording format by the sub-code in this way, even if the recording medium is recorded by the CD format, the recording format recorded by the format of this embodiment is used. It can be reliably reproduced even on a medium. That is, the data can be surely reproduced even on one recording medium in which the data recorded by the CD format and the data recorded by the format of the present embodiment are mixed on one medium.

(5) Other Embodiments In the above embodiment, the digital data is recorded on the CD.
The recording device 30 capable of recording with a format and also with the format described in this embodiment has been described.
The present invention is not limited to this, and the recording apparatus may be the recording apparatus dedicated to the format shown in this embodiment. This dedicated recording device may be configured by the error correction code encoding circuit 32B, the subcode adding circuit 33B, and the processing circuit 34.

Similarly, in the above-mentioned embodiment, the reproducing apparatus 31 capable of reproducing both the digital data recorded by the CD format and the digital data recorded by the format shown in this embodiment has been described. However, the reproducing apparatus is not limited to this, and may be the reproducing apparatus dedicated to the format shown in this embodiment. This dedicated reproducing device may be configured by the processing circuit 42, the sub-code separation circuit 43, and the error correction code decoding device 44B.

In the above embodiment, the case where one sector is formed by collecting 20 C1 codes output from the error correction code encoding circuit 32B has been described, but the present invention is not limited to this. The number of C1 codes forming one sector can be set arbitrarily.

Further, in the above-mentioned embodiments, a read-only optical disk such as a CD is premised, but the present invention is not limited to this, and a writable recording medium such as a magneto-optical disk is also applicable. Applicable.

In the above embodiment, the data of the CD format and the data of the format of the present embodiment are mixed on one recording medium, and the lead-in and T
Although the case where the OC data is recorded by the CD format and the other data is recorded by the format of the present embodiment has been described, the present invention is not limited to this, and each of them may be recorded by the other format.

The mixture of formats is not limited to two types. Any number of error correction code encoding methods and sector structures other than this embodiment can be mixed. In that case, an error correction code coding circuit, a subcode addition circuit, a subcode separation circuit, and an error correction code decoding circuit corresponding thereto are required. The sub-code separation circuits need not be provided in parallel as long as they are compatible.

In any case, the addition and modulation of the frame sync signal in both formats is the same as in the CD format. It is sufficient that the sub-code stores the format identification code and can be discriminated at the time of reproduction.

[0089]

As described above, according to the present invention, the code lengths of the first and second error correction codes are extended with respect to the code lengths defined by the compact disk standard, so that the error correction capability is improved. Can be further improved. Therefore, even if the signal is recorded at a higher density, it can be stably read.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a sector structure of data coded by an error correction code coding method according to the present invention.

FIG. 2 is a block diagram showing an embodiment of an encoding device and a decoding device adopting an error correction code encoding method and an error correction code decoding method according to the present invention.

FIG. 3 is a block diagram showing an embodiment of an error correction coding apparatus according to the present invention.

FIG. 4 is a block diagram showing an embodiment of an error correction code decoding apparatus according to the present invention.

FIG. 5 is a schematic diagram for explaining a conventionally used CIRC encoding system and decoding system.

FIG. 6 is a schematic diagram showing an embodiment of a conventional CIRC encoding device.

FIG. 7 is a schematic diagram showing an embodiment of a conventionally used CIRC decoding device.

FIG. 8 is a schematic diagram showing an encoding device and a decoding device of a CD format.

FIG. 9 is a schematic diagram showing a sector structure of a CD format.

[Explanation of symbols]

1 ... Encoding system, 2 ... Even sample delay circuit, 3 ...
Scramble circuit, 4 ... C2 code encoding circuit, 5 ...
Interleave circuit, 6 ... C1 code encoding circuit, 7 ...
Odd symbol delay circuit, 8, 13 ... Parity inversion circuit, 11 ... Decoding system, 12 ... Even symbol delay circuit, 14 ... C1 code decoding circuit, 15 ... Deinterleave circuit, 16 ... C2 code Decoding circuit, 17 ... Descramble circuit, 18 ... Odd sample delay circuit, 21
...... CIRC encoding circuit, 22 ...... subcode adding circuit, 23, 25, 34, 42 ...... processing circuit, 24 ...... recording medium, 26, 43 ...... subcode separating circuit, 27, 4
4A ... CIRC decoding circuit, 30 ... recording device, 31
...... Playback device, 32A ...... CIRC encoding circuit, 32B
... error correction code encoding circuit, 33A, 33B ... subcode addition circuit, 44B ... error correction code decoding circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location G11B 20/18 F 9074-5D 20/12 9295-5D (54) [Title of invention] Error correction code Coding method, error correction code decoding method, error correction code coding apparatus, error correction code decoding apparatus, digital signal coding method, digital signal decoding method, digital signal coding apparatus, digital signal decoding apparatus and recoding media

Claims (23)

[Claims] 1. A first digital data having a code length and a check data length defined in a compact disk standard.
And an error correction code encoding method in which the error correction capability is enhanced by encoding into a product code of the second error correction code, wherein the frame length at the time of encoding is the same as the data length defined in the compact disk standard. The code length of the second error correction code is expanded and encoded with respect to the code length defined in the compact disk standard while keeping the above value, and then the code length of the first error correction code is changed to the compact disk standard. An error correction code encoding method characterized in that the code length is extended by a constant multiple with respect to the code length defined in 1. 2. When the code length of the second error correction code is extended, the ratio of actual data in the second error correction code is increased as compared with the second check data. The error correction code encoding method according to Item 1. 3. When the code length of the first error correction code is extended, the ratio of actual data in the first error correction code is increased as compared with the first check data. The error correction code encoding method according to claim 1 or 2. 4. An error correction code decoding method for decoding transmission data transmitted as a product code of first and second error correction codes, each having a unique code length and check data length, respectively. , The above-mentioned transmission data is fetched at every constant multiple of the frame length defined by the compact disk standard, and the code length is expanded by the constant multiple of the code length defined by the compact disk standard. 1 error correction code is decoded based on the first check data having a data length expanded according to the constant multiple, and the code length is expanded according to the code length of the first error correction code. An error correction code decoding method characterized in that the present second error correction code is decoded based on second check data having a data length extended according to the constant multiple. 5. The error correction code decoding method according to claim 4, wherein said transmission data is taken in every four times the frame length defined by the compact disk standard. 6. An error having an improved error correction capability by encoding digital data into a product code of first and second error correction codes having a code length and a check data length defined by the Compact Disc standard. In the correction code encoding method, when encoding, the frame length is kept the same as the data length defined in the compact disk standard, and the digital data for multiple frames is converted into the data length defined in the compact disk standard. A process for obtaining the second error correction code extended to the code length defined as the compact disk standard by adding the second check data extended to the second error correction code Interleave processing and the second error correction code after interleaving processing are defined in the compact disk standard. The first error constant code in which the code length is extended by a constant multiple with respect to the code length defined in the compact disk standard by adding the first check data in which the data length is extended to the data length. And an error correction code encoding method. 7. The error correction code encoding method according to claim 6, wherein the interleave length is given by an integral multiple of the constant multiple. 8. A process of delaying an even number of samples of the digital data and a process of scrambling the data before the process of obtaining the second error correction code, and the first error correction. 7. The method according to claim 1, further comprising a step of encoding odd-numbered symbol data of the encoded digital data and a step of inverting the polarities of the second and first check data after the step of obtaining the code. 6. The error correction code encoding method according to claim 6 or 7. 9. An error correction code decoding method for decoding transmission data transmitted as a product code of first and second error correction codes, each having a unique code length and check data length, respectively. , A process of fetching the above-mentioned transmission data for each length that is a constant multiple of the frame length defined by the compact disk standard, and a first inspection having a data length in which the captured data is extended according to the constant multiple By decoding based on the data, the code length is expanded by the above-mentioned constant multiple with respect to the code length defined in the compact disk standard.
Processing for decoding the error correction code, processing for deinterleaving the transmission data decoded based on the first check data, and processing for expanding the transmission data after the deinterleaving processing according to the constant multiple. By decoding based on the second check data having the determined data length, the second error correction code whose code length is extended according to the code length of the first error correction code is decoded. An error correction code decoding method, comprising: 10. The error correction code encoding method according to claim 9, wherein the deinterleave length is given by an integral multiple of the constant multiple. 11. A process of delaying even-numbered symbol data of the transmission data after the process of fetching the transmission data, and before the process of decoding the first error correction code, and the second process. And a process of inverting the polarity of the first check data, and a process of descrambling the decoded digital data after the process of decoding the second error correction code and an odd number of the digital data. 11. The error correction code decoding method according to claim 9, further comprising a process of delaying sample data. 12. An even-numbered sample delay means for delaying and outputting even-numbered sample data out of digital data input in parallel by a predetermined amount, and rearranging the order of the data input from the even-number sample delay means and outputting them. Scrambling means for adding a second error to the digital data for a plurality of frames input from the scrambling means, and a second check data whose data length is extended from the data length defined in the compact disk standard. Second coding means for generating a correction code, interleaving means for rearranging and outputting the time sequence of the second error correction code inputted from the second coding means, and input from the interleaving means. The first inspection in which the data length is extended from the digital data to the data length defined in the compact disk standard. A first error-correcting code having a code length that is a constant multiple of the code length defined in the compact disk standard by adding data;
Coding means, an odd symbol delaying means for delaying and outputting a predetermined amount of odd symbol data of the first error correction code output from the first coding means, and the odd symbol delaying means. An error correction code encoding device, comprising: a parity inversion means for inverting the polarities of the second and first check data included in the error correction code output from the device. 13. An even-numbered symbol delay means for delaying and outputting even-numbered-symbol data of a plurality of frames of transmission data by a predetermined amount, and first and second data included in the data input from the even-numbered symbol delay means. Parity inversion means for inverting and outputting the polarity of the inspection data and the transmission data input from the parity inversion means for the first inspection in which the data length is extended with respect to the data length defined in the compact disk standard. A first decoding unit that decodes the first error correction code by decoding the data and a data array that rearranges and outputs the time array of the transmission data input from the first decoding unit. The interleave means and the transmission data input from the deinterleave means,
Second decoding means for decoding the second error correction code by decoding with the second check data whose data length is extended with respect to the data length defined in the compact disc standard; Descramble means for rearranging and outputting the transmission data input from the second encoding means, and odd sample for delaying and outputting a predetermined amount of data of odd samples of the transmission data input from the descramble means. An error correction code decoding device comprising: delay means. 14. A second error correction code in which digital data is extended to a code length defined in the compact disc standard while having the same frame length as the compact disc standard, and a compact disc standard. After encoding to a product code with the first error correction code whose code length is extended by a constant multiple with respect to the code length defined in, the first auxiliary data is added to the data group consisting of a plurality of the above product codes. A digital signal encoding method characterized by adding and encoding to a data structure of a sector structure close to the compact disk standard. 15. A second error correction code in which digital data is extended to a code length defined in the compact disk standard while having the same frame length as the compact disk standard, and a compact disk standard. After encoding to a product code with the first error correction code whose code length is extended by a constant multiple with respect to the code length defined in, the first auxiliary data is added to the data group consisting of a plurality of the product codes. A first encoding process of adding and encoding into a sector structure data structure close to the compact disk standard, and second and first error correction of the above digital data, each having a code length defined in the compact disk standard. After encoding to the product code of the code, the second auxiliary data is added to the data group consisting of a plurality of the product codes to code to the sector structure of the compact disk standard. Second comprises an encoding process, the digital signal encoding method characterized by be appropriately encoded by connexion the digital data in the first or second coding processing to. 16. The digital signal encoding method according to claim 14 or 15, wherein the first auxiliary data is identification information indicating a data structure of encoded data. 17. The auxiliary data is separated from the transmission data having the same frame length as the compact disc standard and the code length is extended to several frames, and then the auxiliary data is defined by the compact disc standard. The above-mentioned transmission data is taken in every constant multiple of the frame length, and the first error correction code in which the code length is extended by the predetermined multiple above the code length defined in the compact disk standard A second error correction code which is decoded based on the first check data having a data length extended according to the constant multiple and whose code length is extended according to the code length of the first error correction code Is decoded based on the second check data having a data length extended according to the constant multiple. 18. The compact disk standard after separating the first auxiliary data from the transmission data having the same frame length as the compact disk standard and encoded in a structure in which the code length is extended to several frames. The first error correction in which the above transmission data is fetched for every constant multiple of the frame length defined in 1., and the code length is expanded by the predetermined multiple above the code length defined in the compact disk standard. A code is decoded based on the first check data having a data length extended according to the constant multiple, and a second code length is extended according to the code length of the first error correction code. A first decoding process for decoding the error correction code based on the second check data having a data length extended according to the constant multiple, and a sector structure of the compact disk standard. After separating the second auxiliary data from the encoded transmission data, the above transmission data is fetched for each frame length defined by the compact disk standard to correct the first error of the code length defined by the compact disk standard. A second decoding process for decoding the code based on the first check data, and decoding the second error correction code defined by the compact disc standard based on the second check data. A digital signal decoding method, wherein the digital data can be appropriately decoded by the first or second decoding processing. 19. The digital signal decoding method according to claim 17, wherein the first auxiliary data is identification information indicating a data structure of transmission data. 20. A code length of digital data, wherein the code length is extended with respect to the code length defined in the compact disc standard while keeping the frame length the same as the data length defined in the compact disc standard. Of the error correction code and the first error correction code whose code length is a constant multiple of the code length defined in the compact disk standard, and then is coded into a plurality of product codes. The first encoding means for adding the first auxiliary data to the data group to encode into a sector structure data structure close to the compact disk standard, and the digital data respectively have a code length defined in the compact disk standard. After being encoded into a product code of the second and first error correction codes that it has, the second auxiliary data is added to the data group consisting of a plurality of the product codes, and the compact data is added. A digital signal coding apparatus, comprising: a second coding means for coding into a sector structure of a standard, and the digital data can be coded appropriately by the first or second coding means. . 21. After separating the first auxiliary data from the transmission data having the same frame length as the compact disc standard and having a code length extended to several frames, the compact disc standard is obtained. The first error correction in which the above transmission data is fetched for every constant multiple of the frame length defined in 1., and the code length is expanded by the predetermined multiple above the code length defined in the compact disk standard. A code is decoded based on the first check data having a data length extended according to the constant multiple, and a second code length is extended according to the code length of the first error correction code. First decoding means for decoding the error correction code based on the second check data having a data length extended according to the constant multiple, and a sector structure of the compact disk standard. After separating the second auxiliary data from the encoded transmission data, the above transmission data is fetched for each frame length defined by the compact disk standard to correct the first error of the code length defined by the compact disk standard. A second decoding means for decoding the code based on the first check data, and decoding the second error correction code defined by the compact disk standard on the basis of the second check data; A digital signal decoding device, wherein the transmission data can be appropriately decoded by the first or second decoding means based on one auxiliary data. 22. A second error correction code in which the code length is extended with respect to the code length defined in the compact disk standard while keeping the frame length equal to the data length defined in the compact disk standard. And a recording area in which digital data, which is a product code of a first error correction code whose code length is a constant multiple of the code length defined in the compact disc standard, is recorded. Recording medium. 23. A recording area in which digital data, which is a product code of the second and first error correction codes given by the code length defined in the compact disk standard, is recorded. 22. The recording medium according to 22.