JPS62208472A - Decoding device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an abnormal sound at a reproducing sound by setting a pointer independently from the result of the error correction of a PCM signal in accordance with the decoding condition of a decoder to decode the error detecting code of an additive code or an error correcting code. CONSTITUTION:An interpolating circuit 38 executes the interpolating action by using a pointer attendant with respective words of a PCM signal from an error correcting circuit 37 usually, and independant of this, the interpolating action is forcibly executed by an interpolating control signal generated from an interpolating control circuit 49. When the amplitudes of the reproducing signals of a magnetic head 2A and a magnetic head 2B come to be smaller, the number of times of deciding that there is no error as the result of the error detection of an error detecting circuit 44, is decreased to (n) or below, the reproducing signal of the magnetic head 2A and 2B comes to be both (n) or below and the output of a number detecting circuit 47 comes to be '1'. Thus, the interpolating control signal to set a pointer forcibly occurs from an interpolating control circuit 49 to both of the reproducing signal of the magnetic heads 2A and 2B. Thus, the occurrence of the abnormal reproducing sound can be prevented without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding device applied to a digital tape recorder that reproduces digital information signals such as digital audio signals and digital video signals.

[Summary of the invention]

This invention provides a PCM signal encoded with an error correction code and a PC encoded with an error detection code or an error correction code.
In a decoding device that is supplied with input data consisting of continuous blocks consisting of an additional code of the M signal, error correction of the PCM signal is performed depending on the decoding state of the decoder that decodes the error detection code or error correction code of the additional code. By setting the pointer independently of the result, abnormal sounds are prevented from occurring in the reproduced sound.

[Conventional technology]

As an error correction code when digital audio signals (referred to as PCM signals) are recorded/reproduced by a pair of rotary heads, the amount of PCM signals to be recorded/reproduced by one rotating head is arranged in a matrix, and this A system is used in which an error correction code C1 is encoded for each PCM signal arranged in the vertical direction of the matrix arrangement, and an error correction code C2 is encoded for each PCM signal arranged in the horizontal direction of the matrix arrangement. The PCM signal encoded with this error correction code is recorded/recorded for each check symbol of the error correction codes C1 and C2 arranged in the vertical direction.
will be played. To correct errors in the reproduced signal, the error correction code C1 is decoded (C1 decoding), and then the error correction code C2 is decoded (C2 decoding).

Furthermore, in order to facilitate interpolation of error symbols when an uncorrectable error occurs, it is possible to record the even-numbered data and the odd-numbered data of the PCM signal separately on two adjacent tracks. It is being done. Let's call the pair of rotating heads magnetic head A and magnetic head B. In the case of a stereo PCM signal, the even numbered data Le of the L (left) channel and the odd numbered data Ro of the R (right) channel are magnetically transmitted. Head A records on the magnetic tape, and magnetic head B records odd numbered data Lo on the L channel and even numbered data Re on the R channel. A pair of tracks formed by each magnetic head in this way is called an interleave pair. The data recorded on the tracks of the interleave pair have the same frame address in the additional code, so that the reproduction side can know the interleave pair from the frame address. The reproduced data is subjected to error correction processing as described above, and is converted into a PCM signal in which the respective reproduced data of the interleave pair are combined.

Furthermore, in order to increase the utilization rate of the magnetic tape, a recording method is used that does not require a guard band between tracks. That is, the extending direction of the gap of magnetic head A is made different from the extending direction of the gap of magnetic head B, and crosstalk from adjacent tracks is suppressed by azimuth loss.

[Problem that the invention seeks to solve]

In the rotary head type digital tape recorder described above, error detection using simple parity is performed separately from the PCM signal regarding additional codes such as block addresses for writing each block of playback data into a buffer memory and frame addresses indicating interleave pairs. sign is applied. However, with this error detection code, the reliability of the error detection result is low, and because the reproduced block address is incorrect, the reproduced data may be written to the wrong block address, or the frame address is incorrect, resulting in interleaving. Pairs were formed by unrelated data, and there was a risk that a harsh abnormal sound would occur in the reproduced sound. Even if C1 decoding and C2 decoding were performed using the error correction code of the PCM signal, the occurrence of abnormal sounds could not be completely prevented.

Therefore, an object of the present invention is to provide a decoding device that can reliably prevent abnormal sounds from occurring.

[Means for solving problems]

This invention provides a PCM signal encoded with an error correction code and a PC encoded with an error detection code or an error correction code.
In a decoding device that is supplied with input data consisting of consecutive blocks of additional codes of the M signal, an error correction circuit that performs correction processing of the error correction code of the PCM signal and decoding of the error detection code or error correction code of the additional code are provided. A decoder that performs processing, an interpolation circuit to which the output data of the error correction circuit is supplied, and a pointer for the data interpolated by the interpolation circuit independently of the correction result of the error correction circuit according to the decoding state of the decoder. This is a decoding device characterized by comprising: determination means for setting.

[Effect]

In the additional code decoder, the quality of reproduced data can be determined from the amount of data detected as errors. When a lot of error data is detected in the reproduced additional code, the quality of the reproduced data is poor, and there is a high possibility that the PCM signal will be erroneously decoded. Therefore,
If a large amount of error data is detected in the additional data, a pointer is set regardless of error correction of the PCM signal.The interpolation circuit performs interpolation operations such as holding the previous value according to the set pointer. conduct.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to a rotary head type digital tape recorder (abbreviated as RDAT) will be described with reference to the drawings.

The description of this one embodiment will follow in the following order.

a, overall configuration of the digital tape recorder, data configuration of the digital tape recorder C, error correction code of the digital tape recorder d, playback signal processing circuit e, frame address determination circuit f, control of interpolation operation and error correction operation a, Overall Structure of Digital Tape Recorder FIG. 1 shows the overall structure of a rotary head type digital tape recorder, so-called RDAT. l has a diameter of 3011II11 and 2000rp+
*It is a drum that is rotated. A pair of magnetic healds 2A and 2B are attached to the drum 1 with an angular spacing of 180°.

The magnetic tape 3 (indicated by a dashed line) is wound diagonally around the circumferential surface of the drum 1 by 90' at a corner. The magnetic tape 3 is spread between reel hubs 4A and 4B of the tape cassette, and is run at a speed of 8.15 (mm/5eC) by a capstan 5 and a pinch roller 6.

As the magnetic heads 2A and 2B alternately come into sliding contact with the magnetic tape 3, an inclined track 7 is formed as shown in FIG.
A and 7B are formed on the magnetic tape 3. magnetic tape 3
The tape width A is 3.81 mn+. The magnetic gap of one rotary head 2A is tilted by +α with respect to the direction perpendicular to the track, and the magnetic gap of the other rotary head 2B is tilted by 1α with respect to the direction perpendicular to the track.

The angles of the magnetic gaps of the magnetic heads 2A and 2B, which are (α=20°), are called +azimuth and -azimuth, respectively.

The magnetic heads 2A and 2B are alternately selected by a head switching switch 8, and a recording signal from a terminal r of a recording/reproduction switch 9 is supplied to the magnetic heads 2A and 2B via a rotary transformer (not shown). , the reproduction signals of the magnetic helads 2A and 2B are taken out to the terminal p of the recording/reproduction switch 9 via a rotary transformer (not shown).

The analog audio signal from the input terminal 10 is supplied to the A/D converter 12 via the low-pass filter 11.
Sampling frequency: 4BKHz.

(16-bit linear quantization) into a digital audio signal. A digital audio signal from the A/D converter 12 is supplied to a recording signal processing circuit 13.

The recording signal processing circuit 13 performs error correction encoding of the digital audio signal and conversion into a recording data format as described below. In this case, an ID signal (PCM-
ID) is added. Further, a program number of a signal to be recorded, a subcode such as a time code, and an ID signal (subcode ID) for the subcode are formed by a subcode encoder (not shown), and are sent from a terminal 14 to a recording signal processing circuit. 13.

From the recording signal processing circuit 13, serial recording data for each trough of two minutes is generated in synchronization with the rotation of the magnetic heads 2A and 2B. Recorded data is supplied to the head changeover switch 8 through the recording amplifier 15 and the terminal r of the recording/reproduction switch 9.

Recorded data is alternately supplied to the magnetic heads 2A and 2B by the head changeover switch 8.

The signals reproduced by the two magnetic heads and 2B are sent to the terminal p of the head changeover switch 8 and the recording/reproduction switch 9.
The signal is supplied to the reproduction amplifier 16 through. Playback amplifier 1
The output signal of No. 6 is supplied to the PLL 17, and the PLL 17 extracts a clock synchronized with the reproduced signal. The reproduced signal undergoes error correction and error correction in the reproduced signal processing circuit 18.
After undergoing processing such as interpolation, the reproduced digital audio signal is supplied to the D/A converter 19. A reproduced audio signal from the D/A converter 19 is taken out to an output terminal 21 via a low-pass filter 20. At the same time, the reproduced signal processing circuit 18 separates the subcode and subcode ID, and outputs them to the output terminal 22. A subcode decoder is connected to the output terminal 22, and control data and the like are formed from the subcode.

Control signals for controlling the head changeover switch 8 and the recording/reproduction changeover switch 9 are generated by the timing control circuit 23. In addition, the timing control circuit 2
3 is a recording signal processing circuit 13 and a reproduction signal processing circuit 18
generates clock signals and timing signals required by each.

b. Data structure of digital tape recorder The entire data recorded on one trunk is called one segment. FIG. 3A shows 1 recorded by one rotating head.
Indicates the structure of segment data. When the unit amount of recording data is one block, one segment includes 196 blocks (7500 μsec) of data.

A margin (11 blocks) is provided at each end of one segment corresponding to the end of the track. Subcode 1 and subcode 2 are recorded adjacent to each of these margins. These two subcodes are the same data and are recorded twice.

The subcode is a program number and a time code. PLL on both sides of the 8-block recording area of the subcode
A run-in section (2 blocks) and a boss ampoule section (1 block) are arranged.

Also, inter-block blocks where no data is recorded
A gap is provided, and pilot signals for ATF are recorded over five blocks between three inter-block gaps. Within the 130 block length area at the center of one segment, two blocks of P
The PCM signal subjected to recording processing is recorded in an area having a length of 128 blocks excluding the run-in section of LL. This PCM signal is data corresponding to the audio signal of the rotation time of the rotary head.

This PCM signal consists of a two-channel stereo PCM signal consisting of an L (left) channel and an R (right) channel and parity data of an error detection/correction code. Third
One segment shown in FIG. A is recorded/reproduced by two magnetic heads. Data Le is recorded in the left half of the PCM signal recording area, and data R is recorded in the right half.

is recorded. Data Le consists of even-numbered data of the L channel and parity data regarding this data, and data Ro consists of odd-numbered data of the R channel and parity data regarding this data. The odd number and even number are the order counted from the beginning of the interleaved block.

The track formed by the other magnetic head has the same configuration as the one track described above, and one segment of data is recorded thereon. In the data section of one segment of data on this other track, data Re is placed in the left half.
is recorded, and data Lo is recorded in the right half. The data Re consists of even-numbered data of the R channel and parity data regarding this data. Data Lo consists of odd-numbered data of the L channel and parity data regarding this data. In this way, recording the even-numbered data and odd-numbered data of each channel separately on two adjacent tracks, and recording the L channel and R channel data on the same track is a method such as dropout etc. This is to prevent errors in consecutive data on the same channel.

FIG. 3B shows the data structure of one block of the PCM signal. An 8-bit (1 symbol) block synchronization signal is added to the beginning of the l block, and then an 8-bit PCM-ID
is added. A block address is added next to the PCM-ID. Simple parity error correction encoding processing is performed on the two symbols (W1 and W2) of the PCM-ID and block address, and 8-bit parity is added next to the block address. The block address has the most significant bit (MSB) as shown in the third diagram.
), and the most significant bit is set to "θ" to indicate that it is a PCM block.

The 7-bit block address is (OO) ~ (7F) (1
(in hexadecimal). Lower 3 of block address
Bits are (000) (010) (100) (110)
) is determined to be recorded in each block. The lower 3 bits of the block address are (001)
Each block address (011) (101) (111) can record an optional code of PCM-ID. The PCM-ID includes 2-bit Di to ID8 and a 4-bit frame address. Identification information is defined for IDl-ID7, respectively. A pack is composed of 32 ID8s.

For example, IDI is a format ID, audio or other use is identified by IDI, ID2 identifies pre-emphasis on/off and pre-emphasis characteristics, and ID3 identifies the sampling frequency. .

The IDl-ID7 and frame address described above are the same data in the segments of the interleave pair.

FIG. 3C shows the data structure of one block of subcode. It has the same data structure as the PCM block described above. As shown in FIG. 3E, the most significant bit of the symbol W2 of the subcode block is 1'', indicating that it is a subcode block.The lower 4 bits of this symbol W2 are the block address, and the symbol W1 The 8 bits of the symbol W2 and the 3 bits excluding the MSB and block address of the symbol W2 are used as the subcode ID.

Simple parity error correction encoding processing is performed on the two symbols (W1 and W2) of the subcode block, and 8-bit parity is added.

Subcode IDs are those recorded at the even numbered block address (LSB (least significant bit) of the block address is "0") and those recorded at the odd numbered number (LSB of the block address is '1'). The subcode ID includes a control ID that specifies the playback method, a time code, etc.Subcode data is an error correction code using a Reed-Solomon code like the PCM data. are undergoing treatment.

C. Error correction code of digital tape recorder Error detection/correction code processing is performed for each 128 block of data recorded in one segment. Figure 4A is
The code structure of data recorded by one magnetic head 2A is shown, and FIG. 4B shows the code structure of data recorded by the other magnetic head 2B. A PCM signal with a quantization bit count of 16 bits is divided into upper 8 bits and lower 8 bits, and an error detection/correction code is encoded using 8 bits as one symbol.

Data of (128×32-4096 symbols) is recorded in one segment. As shown in Figure 4A, (L
O, L2. ... L 1438) even-numbered data Le of the L channel and (R1, R
The error detection code C1 and the error correction code C2 are encoded in the vertical and horizontal directions of the two-dimensional array of data consisting of the odd-numbered data Ro of the R channel of 3,---R1439). The 28 symbols in the vertical direction are encoded with a C1 code using a (32,,28,5) Reed-Solomon code. Parity data P of four symbols of this C1 code is arranged at the last position of the two-dimensional array. Further, 52 symbols in the horizontal direction are encoded with a C2 code using a (32, 26, 7) Reed-Solomon code. This C2 code is 5
This is done for every 26 symbols of 2 symbols, and parity data Q consisting of 6 symbols is generated for one code sequence. Parity data Q consisting of a total of 12 symbols of C2 code is arranged at the center of the two-dimensional array. The other 52 PCM data symbols located in the horizontal direction are similarly encoded with the 02 code, and their parity data Q is placed in the center.

The code structure shown in FIG. 4B converts the even-numbered PCM signals of the L channel in the code structure of FIG. 4A to the even-numbered PCM signals of the R channel (RO1R2,...R14).
38), and the odd-numbered P of the R channel
The CM signal is converted to the odd-numbered PCM signal of the L channel (Ll
, L3. ...L1439).

As shown in FIG. 3B, for the 32 symbols arranged vertically in these code configurations, the synchronization signal,
One PCM block is configured by adding an ID, block address, and parity.

d. Reproduction Signal Processing Circuit The present invention is applied to processing reproduction data during variable speed reproduction in the reproduction signal processing circuit 18 of the above-mentioned rotary head type digital tape recorder. FIG. 5 shows the configuration of the reproduced signal processing circuit 18, in which a reproduced signal is supplied to an input terminal indicated by 31.

The reproduced signal is supplied to the demodulation circuit 32, and one symbol 10
The bits are demodulated into 8 bits per symbol. When recording on the magnetic tape 3, the 8 bits of one symbol are subjected to digital modulation processing in which they are converted into a preferred pattern of 10 bits in order to reduce low-frequency components as much as possible.

The reproduced data from the demodulation circuit 32 is transferred to the data register 33.
and is supplied to the data bus 35 symbol by symbol via the buffer 34.

A buffer RAM 36 and an error correction circuit 37 are coupled to the data bus 35 . Reproduction data is taken into the buffer RAM 36 from the data bus 35, and in the error correction circuit 37, the data stored in the buffer RAM 36 is subjected to error correction processing (C1 decoding and C2 decoding) using Reed-Solomon code. The error-corrected PCM signal is supplied to an interpolation circuit 38, where uncorrectable errors are interpolated, and a reproduced PCM signal is taken out at an output terminal 39. This reproduced PCM signal is supplied to the D/A converter 19 (see FIG. 1).

In addition, the subcode is processed by a subcode decoder (not shown)
The signal undergoes processing such as error correction, and is output to the subcode output terminal.

Further, a block address detection circuit 40 is provided in association with the demodulation circuit 32. Block address detection circuit 4
0 reads the playback block address. The reproduction block address is supplied to the address generation circuit 41. The reproduced address generated by the address generation circuit 41 is used as the address signal of the buffer RAMa6. The reproduction block address is (32 symbols x 12
This is an address for writing the reproduced data of 8 blocks) (see FIG. 4) block by block in order from the 1st block to the 128th block.

ECC (error correction circuit) by address generation circuit 41
An address for is also generated. This ECC address is supplied to the buffer RAM 36. The ECC address is an address for reading data from the buffer RAM 36 for each of C1 decoding and C2 decoding, and an address for writing error-corrected data and a pointer to the buffer RAM 36.

At the time of Ct decoding, the C1 series data (PCM signal and parity data P) written in advance by the reproduction address is read out from the buffer RAM 36 block by block, error corrected in the error correction circuit 37,
The corrected PCM signal and 01 pointer are stored in buffer RAM3.
6 is written to the same block address. The C1 pointer is written to the memory area where parity P was written. This error correction process is performed for all 01 series. The ECC address generates the read address and write address in the C1 decoding described above. During C2 decoding, the C1 decoded PCM signal, Cl pointer, and parity data Q are read out for each C2 series, and subjected to C2 decoding processing in the error correction circuit 37. This C2 decoding consists of one or two symbol correction using the error correction code C2 and erasure correction using the Cl pointer. The PCM signal and C2 pointer error-corrected by C2 decoding are written into the buffer RAM 36. Also in this C2 decoding,
The required read and write addresses are generated by the address generation circuit 41.

The PCM signals for which C1 decoding and C2 decoding have been completed are read out from the buffer RAM 36 in the original order.

In this case, the PC that is reproduced from each of track TA and track T of the interleaved pair and subjected to error correction.
A two-channel stereo signal is formed by the M signal. PCM with error correction from buffer RAM 36
In order to read the signal, the address formed by the address generation circuit 41 is supplied to the buffer RAM 36, and the PCM signal read from the buffer RAM 36 is sent to the interpolation circuit 3.
8.

PCM-ID in the reproduced data obtained from the demodulation circuit 32
The frame address is detected by the frame address detection circuit 42.
This frame address FRAD is detected by the frame address determination circuit 4 together with the reproduction block address.
3.

Further, the PCM-ID or subcode ID (Wl), block address (W2), and parity obtained from the demodulation circuit 32 are supplied to the error detection circuit 44, and error detection using simple parity is performed in the error detection circuit 44. be exposed. This error detection circuit 44 generates an error pulse indicating the presence or absence of an error. This error pulse becomes "1" when there is an error, and becomes "0" when there is no error. The error pulse is sent to the frame address determination circuit 43.
and is supplied to the counter 45. The counter 45 counts error pulses that become 0'' without an error with respect to one segment of reproduced data.

The count value of the counter 45 is detected by the number detection circuit 47. Comparison circuit 4
8 and register 46. The count value of the counter 45 for one segment of reproduction data reproduced by the magnetic head 2A is taken into the register 46, and then the count value of the counter 45 and the register 46 for one segment of reproduction data reproduced by the magnetic head 2B. The comparator circuit 48 compares the count value of . Comparison circuit 48
At , these count values are compared and a 1-bit comparison output signal corresponding to the magnitude of the count value is generated. This comparison output signal is supplied to an interpolation control circuit 49.

The number detection circuit 47 detects whether the count value of one segment of reproduced data reproduced by each of the magnetic heads 2A and 2B is less than or equal to a predetermined number n. For example, n is selected to be 7. The number detection circuit 47 generates a detection signal that becomes "1" when the number of magnetic heads detected as error-free is less than or equal to n for both magnetic heads 2A and 2B. This detection signal is supplied to an interpolation control circuit 49.

Further, the interpolation control circuit 49 is supplied with a discrimination signal NGAB from the frame address determination circuit 43 and a track identification signal from a terminal 50 .

As will be described later, the frame address determination circuit 43 uses the most significant bit and the least significant bit of the block address determined to be error-free by the error detection circuit 44 and the frame address FRAE) determined to be error-free. , generates a determination signal NGTR regarding a frame address within one track and a determination signal NGAB regarding a frame address of an adjacent track. Discrimination signal NG
TR becomes 1'' when different frame addresses are detected within one track.The frame addresses are the same for PCM signals forming an interleave pair, and when different frame addresses are detected within one track, What is detected is an abnormal playback operation that occurs when playing across other tracks.This discrimination signal NGTR is supplied to the error correction circuit 37.When the discrimination signal NGTR is "1", error correction is performed. In circuit 37,
Execution of erasure correction using the C1 pointer is prohibited.

Further, the determination signal NGAB becomes "1" when the frame addresses contained in the reproduction signal of the magnetic head 2A and the reproduction signal of the magnetic head 2B do not match. This determination signal NGAB detects that no interleave pair is formed. This discrimination signal NGAB is supplied to the interpolation control circuit 49. Discrimination signal NG
When AB is "1", the reproduction data of one magnetic head with fewer errors detected by the error detection circuit 44 is used to interpolate the reproduction data of the other magnetic head.

Interpolation control circuit 49 generates an interpolation control signal for interpolation circuit 38. The interpolation circuit 38 performs average value interpolation, previous value hold, etc. for the word of the PCM signal that cannot be error corrected and is specified by the pointer among the PCM signals that have undergone error correction processing. Interpolation control circuit 4
For PCM signals for which the interpolation control signal from 9 is 1'', for example, the interpolation operation is forcibly performed.

e9, Frame Address Judgment Circuit FIG. 6 shows the configuration of an example of the frame address judgment circuit 43. The frame address determination circuit 43 generates at an output terminal 62 a determination signal NGAB indicating whether the frame addresses match between track A reproduced by the magnetic head 2A and track B reproduced by the magnetic head 2B. In addition, a determination signal NGTR indicating whether or not the frame addresses match within one track is generated at the output terminal 61.

The PCM-ID (Wl) of the PCM block (FIG. 3B) is multiplexed at a cycle of 8 blocks. Therefore, 1
The same P is used (128/8-16) times in the segment.
CM-ID is recorded.

Also, the block address (w2) is (o6) to (7F
), but the ID signal and optional code can be distinguished from each other by the least significant bit BO of this block address. The PCM-ID of the block address (BO="0") is a standardized ID signal, and this block address includes IDI to ID8 and a frame address (4 bits). Furthermore, the frame address is a code signal that changes sequentially from (0000) to (1111), and in an interleaved pair,
It is the same code. Whether it is an interleaved pair or not,
This can be determined by the lower two bits FRAD of the frame address. The most significant bit of the block address (
PCM block (S/P
i d signal: “0”) and subcode block (S/P
id signal: “1”).

The S/Pid signal is supplied to the input terminal 63 in FIG. 6, and the least significant bit B of the block address is supplied to the input terminal 64.
O is supplied and both are EX-N.

The signal is supplied to an R (exclusive N0R) gate 68. Therefore, the output signal of EX-NOR gate 68 is
The output signal of the EX-NOR gate 68 is supplied to the AND gate 69. The error pulse is supplied when there is no error.
0'', so when it is determined that there is no error, AN
An output signal is obtained from D gate 69. The output signal of this AND gate 69 is supplied to the enable terminal of flip-flop 71.

The flip-flop 71 contains the lower two of the frame address.
A focus (simply referred to as frame address) FRAD is provided. Therefore, the PCM-
ID frame address FRAD is flip-flop 7
1.

The output of flip-flop 71 is supplied to flip-flop 72. The frame address FRAD from the input terminal 65 and the flip-flop 71 are input to the EX-NOR gate 73.
The frame address from Although not shown, the flip-flops 71 and 72 are supplied with clock pulses having a block period. EX-NOR gate 7
The output of 3 is provided to AND gate 74. The AND gate 74 is supplied with the output signal of the AND gate 69 . The output signal of the AND gate 74 is sent to the flip-flop 72.
is supplied to the enable terminal of Therefore, the same frame address determined to have no error is stored in flip-flops 71 and 72.

The 2-bit frame address stored in each of flip-flops 71 and 72 is supplied to EX-OR gate 75. The output signal of EX-OR gate 75 is AND
The signal is supplied to gate 76.

The output signal of the RS flip-flop 77 is supplied to the AND gate 76 . RS flip-flop 77 is set by the output signal of AND gate 74 via inverter 78 and reset by a clear pulse CLR from terminal 67 via inverter 79.

The clear pulse CLR is applied to the magnetic head 2A shown in FIG. 7A.
90° where the output A of the magnetic head 2B and the output B of the magnetic head 2B are obtained.
This is the pulse at the first timing (FIG. 7B) of the rotation angle period. Therefore, the output of the RS flip-flop 77 is the frame address FRAD determined to have no error.
When they match twice, it becomes 1''.The output of this RS flip-flop 77 is supplied to the AND gate 76.EX
-The output signal of the OR gate 75 becomes 1lx11 when the two frame addresses FRAD do not match, so A
The output signal of the ND gate 76 becomes "1" when the two frame addresses do not match.

The output signal of AND gate 76 is stored in flip-flop 80.

The output signal of the flip-flop 80 is used as a set input of the RS flip-flop 82 via an inverter 81, and the clear pulse CLR is used as a reset input of the RS flip-flop 82 via an inverter 83. The output signal of this RS flip-flop 82 is taken out to the output terminal 61 as a discrimination signal NGTR. This discrimination signal NGTR is output when the frame addresses do not match within one track.
1″.

In addition, in order to generate the discrimination signal NGAB, a flip-flop 84, an EX-OR gate 85, a flip-flop 8
6 is provided. The flip-flop 84 and the flip-flop 86 are supplied with a clock pulse CKI shown in FIG. 7C and a clock pulse CK2 shown in FIG. 7, respectively.

The output signal of the flip-flop 72 is taken into the flip-flop 84 by the clock pulse CKI.

As shown in FIG. 7C, the clock pulse CKI sends the frame address FRAD (stored in the flip-flop 72) detected as described above from the reproduction signals of the magnetic heads 2A and 2B to the flip-flop. This is a clock for importing into 84. EX-OR
The frame address detected from the reproduction signal of one magnetic head 2A and the other magnetic head 2B are determined by the gate 85.
A match with the frame address detected from the reproduced signal is detected. The output signal of the EX-OR gate 85, which becomes "0"" when the two match and becomes "1" when the two do not match, is sent to the flip-flop 86 as a clock pulse CK.
2 (Fig. 7D). The output signal of this flip-flop 86 is taken out to the output terminal 62 as a discrimination signal NGAB.

f. Control of Interpolation and Error Correction Operations In one embodiment of the invention described above, interpolation circuit 38 typically performs the interpolation operation using a pointer associated with each word of the PCM signal from error correction circuit 37. In addition to this normal interpolation operation, an interpolation control signal generated from the interpolation control circuit 49 forcibly performs the interpolation operation regardless of the pointer from the error correction circuit 37. The reproduction state when this forced interpolation operation is performed will be explained with reference to FIG.

FIG. 8 shows examples of reproduction signals of the magnetic heads 2A and 2B. FIG. 8A shows a case where the amplitudes of both the reproduction signal of the magnetic head 2A and the reproduction signal of the magnetic head 2B become small. For example, the azimuth during reproduction is different from that during recording, and the amplitude of the reproduced signal becomes small due to azimuth loss, or the amplitude of the reproduced signal becomes small because an unrecorded area is reproduced. In such a reproduction state, as a result of error detection by the error detection circuit 44, the number of times it is determined that there is no error is reduced to n or less. However, both the reproduction signals of the magnetic hemispheres 2A and 2B become less than n, and the output of the number detection circuit 47 becomes "1". As a result, the interpolation control circuit 49 generates an interpolation control signal that forcibly sets a pointer for both the reproduction signals of the magnetic heads 2A and 2B. Since many pointers are set, the interpolation circuit 38 performs a previous value holding operation or a muting operation.

FIG. 8B shows a case where the reproduced signal from one magnetic head 2A has a normal amplitude and the amplitude of the reproduced signal from the other magnetic head 2B is small. For example, when performing continuous recording with a device in which one magnetic head is clogged,
A reproduced signal shown in FIG. 8B is generated. In such a reproduction state, the reproduction signal of the magnetic head 2B contains many errors, so that the quality of the corrected PCM signal is poor. In the case of continuous recording, frame addresses do not match between two adjacent tracks. Therefore, the determination signal NGAB generated by the frame address determination circuit 43 becomes 1''. Furthermore, the comparison circuit 48 detects the reproduced data with fewer errors among the reproduced data from two adjacent tracks. .

In the interpolation control circuit 49, the determination signal NGAB is “
1'', the comparison output signal of the comparator circuit 48 is validated, and an interpolation control signal for interpolating the reproduced data with more errors using the reproduced data with fewer errors is formed.Interpolation circuit 38 The series of PCM signals supplied to (L
O, RO, Ll, R1, L2. R2, L3. R3, L4
...), (LO, R1, L2.R3, L4・
) are the PCM signals reproduced by the magnetic head 2A, and (RO, LL, R2, L3...) are the PCM signals reproduced by the magnetic head 2B. Input terminal 50
The track identification signal supplied to the interpolation control circuit 49 is a pulse signal that becomes "0" during the period of the PCM signal reproduced by the magnetic head 2A and becomes "1" during the period of the PCM signal reproduced by the magnetic head 2B. It is.

From this track identification signal and the comparison output signal of the comparison circuit 48, the interpolation control circuit 49 generates an interpolation control signal which becomes "1" corresponding to the period of the PCM signal reproduced by one of the magnetic heads. The interpolation control signal is “l”
A pointer is set for the PCM signal of the period ``.Therefore, the interpolation circuit 38 uses the reproduced PCM signal of one magnetic head with fewer errors to interpolate the reproduced PCM signal of the other magnetic head. .

FIG. 8C shows reproduction signals of the magnetic heads 2A and 2B when the magnetic heads 2A and 2B scan another track from the middle because the track is curved. In such a reproduction state, different frame addresses within one track are reproduced, and the discrimination signal NGTR becomes 13. This discrimination signal is NG.
TR is supplied to the error correction circuit 37, and pointer laser correction in C2 decoding is prohibited. In C2 decoding, one symbol or two error symbols are corrected by error correction using error correction code C2, and erasure correction is performed using the C1 pointer generated by C1 decoding. However, as mentioned above, 2
In a reproduction state in which the magnetic head scans across the tracks of a book, the reliability of the C1 pointer generated in C1 decoding is low, and erasure correction using the C1 pointer is prohibited by the discrimination signal NGTR.

By controlling the interpolation operation and the error correction operation as described above, it is possible to reliably prevent an unpleasant abnormal sound from occurring in the reproduced sound.

The present invention can also be applied to the case where the PCM-ID of recorded data has a data structure in which errors can be detected using a CRC code in addition to simple parity.

〔Effect of the invention〕

According to this invention, since the decoding state of the additional code is used separately from the decoding result of the error correction code for the PCM signal, there is no possibility that the error correction code will perform erroneous decoding when the amplitude of the reproduced signal is small. Even in such a case, it is possible to reliably prevent abnormal reproduction sound from occurring.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a digital tape recorder with two rotary heads to which the present invention can be applied, FIG. 2 is a route map showing the tape format of the digital tape recorder, and FIG. 3 is a diagram showing the digital tape recorder. 4 is a route map used to explain the error correction code of a digital tape recorder. FIG. 5 is a block diagram of the main parts of an embodiment of the present invention. 7 and 7 are connection diagrams showing the structure of the frame address determination circuit and a time chart used to explain its operation, and FIG. 8 is a waveform diagram of a reproduced signal used to explain the present invention. Explanation of main symbols in the drawings: 1 drum, 2A, 2B: magnetic head, 3: magnetic tape, 13: recording signal processing circuit, 18: reproduction signal processing circuit, 32: demodulation circuit, 35: data path,
36: Bathophore RAM, 37: Error correction circuit, 38: Interpolation circuit, 40 Ni block address detection circuit, 42: Frame address detection circuit, 43
: Frame address judgment circuit, 44: Error detection circuit, 47: Number detection circuit, 48: Comparison circuit, 49
:Interpolation control circuit. Agent Patent Attorney Tadashi Sugiura Figure 5 Kutsuyu Status Figure 8

Claims (1)

[Claims] A decoding device to which input data is supplied with consecutive blocks consisting of a PCM signal encoded with an error correction code and an additional code of the PCM signal encoded with an error detection code or an error correction code. an error correction circuit that performs correction processing of the error correction code of the PCM signal; a decoder that performs decoding processing of the error detection code or the error correction code of the additional code; and an output data of the error correction circuit. an interpolation circuit to be supplied; and determination means for setting a pointer to data interpolated by the interpolation circuit according to a decoding state of the decoder and independently of a correction result of the error correction circuit. A decoding device characterized by: