JPS59152509A - Muting device - Google Patents

Abstract

PURPOSE:To deliver the reproduction information even in a fast forward mode and at the same time to mute said reproduction information when noises are generated, by driving a resetting means and a muting means in response to a fact that the relation between read and write addresses does not satisfy the prescribed conditions to a memory. CONSTITUTION:A comparing means 14 which compares the relation between the write and read addresses, i.e., the outputs of counter 10 and 13 delivers pulses when both addresses get close too much to each other or away too much from each other. This pulse sets the counter 10 under an initial state, and the counter 10 starts counting the synchronizing signals. Then a flip-flop 16 is set and accordingly a counter 15 delivers the signal of a low level to close a gate circuit 7. A D/A converter 8 delivers continuously the output obtained at that time point, that is, the converter 8 is muted. At the same time, the counter 13 is reset by the set output of the flip-flop 16. The counter 15 counts 15 synchronizing signals, and the output of the counter 15 is inverted to a high level to reset the flip-flop. The gate 7 is also driven to apply the read data of an RAM5 to the converter 8. The muting state of the converter 8 is released.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a noise muting device aVC in a digital audio player.

<C4 Background of the Invention Aspects of the digital audio disc system are as described below. After sampling music information and converting it into a digital signal, a synchronization signal, error detection and correction code, etc. are added. Furthermore, these signals are subjected to Inter 2 League (rearranging the order of signals) and recorded on the disc.In a disc player that produces disc YxH, error detection and correction of the reproduced digital signal, and dinter 9-league are performed. (The signals are returned to their original order, etc., are further converted to VcD-A, and the music information 2 is reproduced.

By the way, when I'm in Nyu, I use E (AM, g) to perform a dinter jeep.When writing to or reading from this RAM, the addresses are written in the correct order in vC. Therefore, in the state VC where the infiltration address and the read address are waiting for a certain relationship, Nyu is performed, and then the normal This will allow you to obtain playback information. However, the optical pickup may become distorted in the radial direction of the disc. This may result in information from addresses that are not full being read out, or information from addresses that have not yet been read out. Situations such as VC, 11I and other information may occur, causing noise in the reproduced information during fast forwarding.

Therefore, in the case of fast forwarding 1st life, the playback information is usually ? Muting is being done. In a digital audio disc system, in addition to certain sound information, control information is also recorded, so using this control information, you can easily find the beginning of a song or play it from the middle of the song. Therefore, there is no need to output reproduction information during fast forwarding.

However, actually operating a disc player in one prefecture? Considering this, it is preferable to search for the desired V and position in the VC during fast forwarding, just like the birth information 'a: irl'.

e9 The aim of the invention is to output reproduction information even during fast forwarding, and to mute this when noise occurs.

5) A means for comparing the four-input address and the continuation address in the memory for performing the configuration dinterleap of the seventh son was provided, and by this means, it was confirmed that the relationship between the two addresses no longer satisfies the predetermined condition. In response to the detection of the address, the resetting means for setting both addresses to the 03 period state is driven, and the muting means for muting the reproduced information for a certain period of time is driven.

((E) Embodiment of the Invention After the data picked up from the disc is waveform-shaped, it is processed as reproduced data by the data extraction circuit (1) and the clock pulse generator tffi (+11hB (2J). Circuit (2) is the main rP
It is composed of LL, etc., and creates clock pulses from reproduced data. This clock pulse is the data extraction concave u (1
) and 4υ] are applied to the detection circuit (3). Data extraction time i@ [l1iC extracts playback data and same 4υ] detection l! At TIJ 'l1lr' [, 3), the synchronous IH signal is detected from the reproduced data. The playback data is stored in the data-containing circuit (after 4 steps, RAM (5)
VC is involved. On the other hand, the data successively output from F(AM(5)) is sent to the data reading circuit (6) and gate circuit (7).
The analog signal V
Cfm is done. Thus, the original information is reproduced. Before the digital data is subjected to D-A conversion, an error detection and correction circuit (9) performs error detection and 1 correction.

Now, let's talk about data intrusion into RAMf5).
Let me explain about the series. Data is 1 unit (e.g. 8
A series of old items for each [bit]? It is assumed that 11 synchronization signals are added to 8 units of data. It is assumed that the interleaving is performed so that each unit of data is not shifted by one frame (an interval of 1 row period No. 48).

Then, eight pieces of data (A, B, C.

D, E, F, G, H) structure [1st row is (-7°-
6, -5, -4, -6, -2, -1, 0). In other words, the H-th data Z5 constituting one frame; the data VC of the 0th frame and the 0th frame of the drunken J to be interleaved
, the G-th data is the G-th data of the 11th frame (the previous frame),
Similarly, the A-th data is the A-th data of the 17th frame (seven frames before). Therefore, the total amount of data for one frame is 8
One frame's worth of writing has been completed and it is nine days.

Now, as shown in Figure 2, the address of RAM+5)? , r
Place address? The data consists of 6 bits and the upper address is 4 bits, and the data is in one address VC1 unit? shall be recorded. Then 1. This means that 16-128 pieces of data it and ax can be recorded. And, as mentioned above, considering interleague, one frame after interleague?
The 8 pieces of data that make up the address are from address (0, 0) to (7,
7) Write diagonally at t. As can be seen from Figure 2 (b), all the data at the upper address, address 15, is y.
When loaded, it can be seen that all the data from the 0th frame to the 8th frame is complete. Therefore, at this point, if one frame whose upper address is from address 7 (0th frame) to address 15 (8th frame) is read in the horizontal direction iC, all data of one frame is read. I can put it out.

In general, taking into account jitter components etc., the upper address 1
When the writing up to address 5 is completed, that is, when the upper address returns to address O again, read the upper address 11 in the horizontal direction.
Read out. In addition, in Figure 2 (a), it can be seen by multiplying the length of RAM + 5) t by 2 times, and the data in the shaded area indicated by 1"VC is actually the upper white triangular part vC layered. Therefore, the address of the ring upper address address o shown in FIG. 2(b) and the phantom upper address address 0 shown above indicate the same part.

Now, returning to FIG. 1, address designation will be explained. The address of the blue color is determined based on the synchronization signal output from the synchronization detection circuit 13.

Synchronous e ”j it k is applied to the counter 1101 and counted up. The output of the counter IIIN is applied to the RAM[5) VC through the address selection circuit συ, and the address at the time of writing is determined.

On the other hand, the address at the time of reading is determined based on the timing pulse output from the reproduction system timing pulse generation circuit u3. This circuit α2 includes a crystal oscillator and outputs a timing pulse having the same period as the synchronizing signal. This timing pulse is printed on the counter fi31ic and counted up.

The output of counter 03 passes through address selection circuit GIJY,
RAJ5), and the address at the time of reading is determined. A write/continue output switching signal is applied to the address selection circuit σD, and a write/continue output address is mutually selected for each unit of data.

If you leave it to the normal reproduction pattern, the write address will be thick.
There is only a slight variation depending on the component, but the loading address and the reading address have a substantially normal relationship, and data is sequentially and correctly outputted from RAM+5J. In Figure 5, (
(a) shows the output V of the synchronization detection circuit 13, and (C) shows the output of the reproduction system timing pulse generation circuit α, respectively.
The relationship between the two is constant.

However, if the fast forward state is set at timing ('I), the synchronization signal read from the disk will be disturbed, and the output of the counter Ill, that is, the hidden address will be disturbed. If the write address is greatly disturbed and even data that has not yet been read is rewritten, noise will occur in the reproduced output.

Therefore, in the VC of the present invention, the relationship between the write address and the read address, that is, the counter 11c1 and the counter (1 to
A comparison means a4 is provided for comparing the outputs of the two. In this comparison means (I4), when both 7 dresses tζ are closer than necessary and when β11E is more than necessary, the pulse (
Figure 6b) is output. This pulse (b) causes the counter 11. [N is reset to off state.

Further, the counter (151) starts counting the +1JI signal, and the flip-flop 11.1ρ is set.

Correspondingly, the counter 1151 outputs a low level signal (Fig. 6 d), the gate circuit 17 is closed, and the output of the D-A converter (8) continues the output at point 7. Output. In other words, it becomes a muting state. Man,
The set output of the flip-flop (16) causes the set state to be established.

Now, the counter 1151 counts 15 synchronization signals.
(At this time, the output of counter flα is also @ 15 II
), the output of the counter (151) is inverted to high level.Then, the flip )a knob 1 mark is reset, and in response, the counter t+311: ″11
" is set, and counting up starts from this value. In other words, a new read starts from the point when the initial relationship is returned to 15 for the write upper address and 11 for the read upper address. Then, the counter (Due to the high level output of 19, the gate (7) is also driven, and the successive output of RAM +5 is marked 7JO on the DA converter (8), and the muting state is released.

(f) Constantly monitoring the relationship between the effect of the invention and the read address,
Since it is designed to perform muting when a predetermined condition is exceeded, it is important to obtain a noise-free playback output.

[Brief explanation of the drawing]

Figure 1 shows misfire 1:! FIG. 2 is a diagram showing a RAM, and FIG. 6 is an operation waveform diagram. U 滲 is a hidden means, (7) 1151 is a muting hand r
&? The gate circuits and circuits constituting the circuit, tt6)l, are set up in the initial state.

Claims (1)

[Claims] (1) What is the memo 9 for performing digital interleaving?In addition to the digital audio player Vc, an address comparison unit is provided to compare the input address and the subsequent address to the memory, and this address comparison means is used to compare the two addresses. muting for driving an initial state setting means for setting the destination to a cut-off state in response to detection that the first egg no longer satisfies a predetermined condition, and muting reproduction information for a certain period of time; A muting device configured to drive a handshake.