JPH0557674B2 - - Google Patents
Info
- Publication number
- JPH0557674B2 JPH0557674B2 JP13286780A JP13286780A JPH0557674B2 JP H0557674 B2 JPH0557674 B2 JP H0557674B2 JP 13286780 A JP13286780 A JP 13286780A JP 13286780 A JP13286780 A JP 13286780A JP H0557674 B2 JPH0557674 B2 JP H0557674B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- field
- index
- pcm
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010521 absorption reaction Methods 0.000 claims 1
- 230000008707 rearrangement Effects 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
- G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
- G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
- G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
- G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Management Or Editing Of Information On Record Carriers (AREA)
Description
【発明の詳細な説明】
本発明は、PCM記録再生装置の再生出力デー
タの編集或いはテープ頭出し装置として使用して
好適な編集用データフラグ回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an editing data flag circuit suitable for editing playback output data of a PCM recording/playback device or for use as a tape cue device.
日本電子機械工業会技術フアイルSTC−007に
基づく民生用PCMエンコーダ・デコーダに於い
ては、デコーダ入力信号の１フイールド
（262.5H）中に１個の制御信号ブロツク（1H）
が設けられており、この制御信号ブロツク（128
ビツト）中には28ビツトで構成されるアドレス信
号ワード（以下単にアドレスデータという）があ
る。即ち１フイールド中のデータに対して１個の
アドレスデータが付けられている。通常、編集、
頭出し用としてはこのアドレスデータが用いられ
るが、上記１フイールド中のデータは、テープ再
生時における連続したワード誤りによる原信号の
復元不可或いは雑音発生を防止するため、記録時
にワードの配列替えを行なつた所謂インターリー
ブされたデータであり、更にこれらのデータは一
旦PAM等の記憶手段に記録され、再生糸で本来
の配列に戻す即ちデインターリーブされて出力さ
れる。この為このデインターリーブ処理等により
遅延を受けるので遅延された出力データと入力時
に抽出されたアドレスデータとのタイミングが必
ずしも一致しなくなり、編集用等としてのアドレ
スデータの精度、信頼度が満足されなかつた。こ
のタイミング不一致について第１図を用いて説明
する。第１図イフイールドの配列構成図即ちデー
タ信号であり、各フイールドFo、Fo+1……は、そ
のデータ区間の先頭に配置された１個（1H）の
制御信号ブロツクCo、Co+1……と、それに続く
245個（245H）のデータブロツクDo、Do+1……
により構成される。前述の如く、アドレスデータ
は制御信号ブロツクCo、Co+1……の中に入つてお
り、第１図ロに示すようにアドレスデータADDo
は、抽出されると次のフイールドFo+1の制御信号
ブロツクCo+1迄持続される。 In the consumer PCM encoder/decoder based on the Japan Electronics Industry Association technical file STC-007, one control signal block (1H) is generated in one field (262.5H) of the decoder input signal.
is provided, and this control signal block (128
There is an address signal word (hereinafter simply referred to as address data) consisting of 28 bits. That is, one piece of address data is attached to data in one field. Usually, edit,
This address data is used for cueing, but the data in the above one field must be rearranged during recording to prevent the original signal from being restored or noise to occur due to continuous word errors during tape playback. This data is so-called interleaved data, and furthermore, these data are once recorded in a storage means such as PAM, and then returned to the original arrangement using a regenerated yarn, that is, deinterleaved, and then output. For this reason, since there is a delay due to this deinterleaving process, the timing of the delayed output data and the address data extracted at the time of input does not necessarily match, and the accuracy and reliability of the address data for editing etc. are not satisfied. Ta. This timing mismatch will be explained using FIG. 1. Fig. 1 is a diagram of the array configuration of if fields, that is, data signals, and each field F o , F o+1 . . . is one (1H) control signal block C o , Co +1 ...and so on
245 (245H) data blocks D o , D o+1 ...
Consisted of. As mentioned above, the address data is contained in the control signal blocks Co , Co +1 , etc., and as shown in FIG .
When extracted, it is maintained until the control signal block C o+1 of the next field F o+1 .
次に、１データブロツクは左、右チヤンネル各
３個ずつの合計６個の標本化信号ワード、誤り訂
正ワードＰ及びＱ各１個及び誤り検出ワード
（CRC）１個の９ワードからなり、標本化信号ワ
ードについて言えば、アドレスデータADDoのフ
イールドFoでは、前記インターリーブにより左
チヤネルデータはBo-238からBo+684迄、右チヤネ
ルデータは、Ao-190からAo+732迄のデータが含ま
れている。これらのデータは、RAM等により所
定の遅延を受け、例えばデータAoでは、第１図
ハの出力データに示すように所定の遅延ｄを受け
る。ここで同図ハの斜線の部分は、隣り合つたフ
イールド（フレーム）のデータが入つてくる部分
を示す。 Next, one data block consists of nine words: a total of six sampled signal words (three each for the left and right channels), one each of error correction words P and Q, and one error detection word (CRC). Regarding the conversion signal word, in field F o of address data ADD o , the left channel data is from B o-238 to B o+684 and the right channel data is from A o-190 to A o+732 due to the interleaving. contains data. These data are subjected to a predetermined delay by a RAM or the like. For example, data Ao is subjected to a predetermined delay d as shown in the output data in FIG. 1C. Here, the diagonally shaded area in FIG.
以上のことを第２図により更に詳しく説明す
る。 The above will be explained in more detail with reference to FIG.
第２図イに示すように、フイールドFo内の245
個のデータブロツクのうち最初のデータブロツク
Do As shown in Figure 2 A, 245 in field F o
first data block of data blocks
D o
Claims (1)
信号ワードを含む情報データブロツクを１フイー
ルド中に複数存在させ、この情報データブロツク
に対して制御データを設けて１フイールドとし、
このフイールドを単位とした複数のフイールドか
らなるPCM信号を再生するPCM再生装置におい
て、再生した前記PCM信号内の各フイールドに
おいて同じ所定データブロツク内の同じ所定信号
ワードを、前記各フイールド内における他の信号
ワードと区別する指標を生成する指標生成手段
と、再生した前記PCM信号内の前記複数の信号
ワードに前記指標生成手段で生成した指標を付加
して元の配列に戻すデインターリブおよびジツタ
吸収の処理を行う記憶手段と、前記記憶手段から
出力される前記指標にあわせて前記制御データを
保持する保持手段を備えたことを特徴とする
PCM再生装置。 ２ 特許請求の範囲第１項において、前記指標生
成手段は、各フイールドにおいて最初のデータブ
ロツク内の先頭信号ワードを、前記各フイールド
内における他の信号ワードと区別する指標を生成
するPCM再生装置。[Scope of Claims] 1. A plurality of information data blocks including a plurality of interleaved signal words with word rearrangement are present in one field, and control data is provided for the information data block to form one field,
In a PCM reproducing device that reproduces a PCM signal consisting of a plurality of fields with this field as a unit, the same predetermined signal word in the same predetermined data block is reproduced in each field in the reproduced PCM signal, and the same predetermined signal word in the same predetermined data block is An index generation means for generating an index to distinguish it from a signal word, and processing for deinterleaving and jitter absorption by adding the index generated by the index generation means to the plurality of signal words in the reproduced PCM signal and returning the same to the original arrangement. The present invention is characterized by comprising a storage means for performing the above, and a holding means for holding the control data in accordance with the index outputted from the storage means.
PCM playback device. 2. The PCM playback device according to claim 1, wherein the index generating means generates an index that distinguishes the leading signal word in the first data block in each field from other signal words in each field.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13286780A JPS5758274A (en) | 1980-09-26 | 1980-09-26 | Data flag circuit for editing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13286780A JPS5758274A (en) | 1980-09-26 | 1980-09-26 | Data flag circuit for editing |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4106594A Division JP2503151B2 (en) | 1992-04-24 | 1992-04-24 | PCM recording / reproducing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5758274A JPS5758274A (en) | 1982-04-07 |
| JPH0557674B2 true JPH0557674B2 (en) | 1993-08-24 |
Family
ID=15091396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13286780A Granted JPS5758274A (en) | 1980-09-26 | 1980-09-26 | Data flag circuit for editing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5758274A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2706937B2 (en) * | 1987-09-17 | 1998-01-28 | 旭光学工業株式会社 | Dubbing device |
| JP2711352B2 (en) * | 1988-02-04 | 1998-02-10 | 松下電器産業株式会社 | Time information recording and playback device |
-
1980
- 1980-09-26 JP JP13286780A patent/JPS5758274A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5758274A (en) | 1982-04-07 |
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