JPS61156573A - Digital magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To make a scale of a circuit small, and to convert it to an IC by switching successively reproducing signals of al tracks by a switching means, and thereafter, executing an automatic adjustment of a gain of the reproducing signal at every track by one attenuator, an analog-to-digital converter, and adder and subtracter, etc. CONSTITUTION:Signals of an (n) track portion reproduced from a magnetic head group 1 are amplified by an amplifier group 2, respectively, switched and outputted successively by being synchronized with a clock from an input terminal 3 in a multiplexer 4, and converted to a digital signal by an A/D converter 6 through an attenuator 5. In case when it has exceeded the first reference value, a comparator 10 supplies a subtrahend '1' to an adder and subtracter 8, a value which has subtracted '1' from a gain constant which a shift register 9 has outputted is outputted, and it is supplied to the attenuator 5. On the other hand, in case when said signal is smaller than the first reference value and larger than the second reference value, a value which has added '1' to a constant by the adder and subtracter 8 is outputted and supplied to the attenuator 5. On this way, the digital signal from the A/D converter 6 is adjusted automatically by the attenuator 5 so that it goes in between the first and the second reference values.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital magnetic recording and reproducing apparatus for reproducing digital signals recorded on a magnetic recording medium such as a magnetic tape using a multi-track magnetic head.

BACKGROUND OF THE INVENTION Recently, attempts have been made to perform digital magnetic recording and reproduction of stereo audio using a fixed head system using a compact cassette and at a low tape speed of 4.7 e cm/sec, but the recording density is limited. Due to this relationship, the information is distributed and recorded on the magnetic tape into approximately 20 tracks. Therefore, for reproduction, magnetic heads and reproduction amplifiers are required as many as the number of tracks.

By the way, there are differences in the characteristics of magnetic tapes due to differences in magnetic materials.
Alternatively, variations in the reproduction output may occur due to variations in the magnetic head between tracks, and in extreme cases, this may cause the circuit system to become saturated or the output to be insufficient, resulting in a worsening of the error rate.

Therefore, in the past, a variable resistor for gain adjustment was inserted into a part of each regenerative amplifier, or an automatic gain control circuit using the time constant of a capacitor and a resistor was built into a part of each regenerative amplifier. The output voltage was kept within a certain range by

Problems to be Solved by the Invention However, if the intention is to commercialize a digital recording/reproducing device for consumer use, providing the automatic gain control circuit with a built-in variable resistor or capacitor for approximately 20 tracks requires a large circuit area. It was also large and unsuitable for IC implementation.

In view of the above-mentioned problems, the present invention provides a digital magnetic recording and reproducing apparatus that can automatically adjust the gain of a reproduced signal and is suitable for IC implementation.

Means for Solving the Problems In order to solve the above problems, the digital magnetic recording and reproducing apparatus of the present invention includes a switching means for sequentially switching and selecting reproduction signals reproduced from a plurality of tracks, and a switching means for sequentially switching and selecting reproduction signals reproduced from a plurality of tracks; an attenuator whose output is increased or decreased by increasing or decreasing a preset gain constant while attenuating the reproduced signal; a first storage means for storing the gain constant for each track; and a first storage means for storing the gain constant for each track; It consists of an analog-to-digital converter for converting the digital signal into a signal, and an adder/subtractor for decreasing or increasing the gain constant of the low track held in the first storage means in relation to the magnitude or magnitude of the digital signal. Further, in the digital magnetic recording and reproducing apparatus of the present invention, the digital signal is a first
an adder/subtractor that detects that the gain constant of the track exceeds a reference digital value and decreases the gain constant of the corresponding track held in the first storage means; A reference digital value is provided for each track, and the digital signal is provided for each track.
a second storage means that switches to a set state for each corresponding track by detecting that the reference digital value of the second storage means has been exceeded; and a pulse generation means that generates a pulse that resets the second storage means at regular intervals; and an adder/subtracter that operates only when the contents of the second storage means immediately before being reset are in a reset state to increase the gain constant of the corresponding track.

According to the above-described structure, the present invention sequentially switches the reproduction signals of all the tracks using the switching means, and then automatically adjusts the gain of the reproduction signal for each track using one attenuator, analog-to-digital converter, adder/subtractor, etc. The circuit size can be small. Further, since the present invention increases the gain by synchronizing the pulse generating means with pulses, it does not require a capacitor, and is therefore suitable for IC implementation.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 shows one embodiment of the present invention, and FIG. 2 shows one embodiment of a part of FIG. 1 in more detail. Also.

FIGS. 3 and 4 are tying waveform diagrams in the configurations of FIGS. 2 and 1, respectively.

In FIG. 1, 1 is a magnetic head group for reproduction consisting of n pieces (n is an integer), and 11, 12111kI11n are the 1st, 2nd, kth, and nth magnetic heads (
k is 1, 2. . . . n) is a magnetic head for reproducing tracks.

2 is a regeneration amplifier group consisting of n pieces, 21, 22, 2k
・2n is each amplifier of amplifier group 2, and magnetic head 1k
Each magnetic head of the magnetic head group 2 is connected to each amplifier of the amplifier group 2, such that the magnetic heads of the magnetic head group 2 are connected to the amplifier 2k.

3 is a clock input terminal to which a clock is input, and the clock is input to a multiplexer 4, which will be described later,
The digital converter 6 is connected to be supplied to the detector 31.

4 is a multiplexer which sequentially switches and outputs n types of signals output from the amplifier group 2 in synchronization with the supplied clock and repeats this operation.

That is, a signal is selectively outputted to a certain amplifier 2 from the multiplexer 4 for one clock period every n clocks.

5 converts the signal output from multiplexer 4 to 2m (m
6 is an analog-to-digital converter (hereinafter referred to as an A/D converter) that converts the signal output from the attenuator 5 into a digital signal in synchronization with the supplied clock. 7 is A/D
This is the output terminal of the converter 6. Although not shown in this embodiment, the digital signal output from the output terminal 7 is sent to an equalizer circuit. Further, it is assumed that the A/D converter 6 has a resolution of, for example, about 8 bits and includes a sample and hold circuit.

8 is an adder/subtractor that performs addition and subtraction in units of m bits;
Reference numeral 9 denotes a shift register that performs parallel shifts in units of m bits in synchronization with the supplied clock and has n stages, and the output of the nth stage of the shift register 9 is input to the adder/subtractor 8 in units of m bits. input to the terminal.

1o is a comparator that outputs a subtractor by '1' to the adder/subtractor 8 when the output of the A/D converter 6 is less than the first reference digital value. is set to a level slightly lower than the maximum output value of the A/D converter 6, for example.

3o is a decoder that converts the m-bit binary code output from the (n-1)th stage register of the shift register 9 into 2m different values and outputs it to the attenuator 5; If the value of is large (small), the attenuator 5
Assume that the degree of attenuation of is small (large).

31 indicates 1 to the adder/subtractor 8 when the output of the A/D converter 6 changes at a level lower than a second reference digital value, which will be described later.
A more specific embodiment of the detector 31 is shown in FIG. 2.

In FIG. 2, numeral 31 is a clock input terminal connected to clock input terminal 3, and numeral 32 is a clock input terminal connected to clock input terminal 3, and numeral 32 is a clock input terminal that divides the frequency of the clock supplied from clock input terminal 31 to time 1. (However, t, = n
to, here t. is one period of the clock) and outputs an H level signal for a certain time t2 (t2>t,
), and 33 is a differentiating circuit that outputs a reset pulse of an H level signal at the falling edge and the rising edge of the output of the frequency divider 32. Incidentally, a timing waveform diagram regarding the functions of the frequency divider 32 and the differentiating circuit 33 is shown in FIG. a, b, c in Fig. 3 are the second
The waveform at the same code point in the figure is shown.

34 is a terminal connected to the output of the A/D converter 6;
A comparator 5 outputs an H level signal when the output of the A/D converter 6 input from the terminal 34 is greater than the second reference digital value. Note that the second reference digital value is set to a lower level than the first reference digital value.

36 is an OR gate; 37 is an n-stage shift register which inputs the output of the OR gate 36 and operates in synchronization with the clock supplied from the clock input terminal 31; Reset with reset pulse.

Furthermore, the outputs of both the comparator 35 and the shift register 37 are input to the OR gate 36.

38 is an inverter that inverts the output of the OR gate 36;
9 is an AND gate that outputs an H level signal when both the outputs of the frequency divider 32 and the inverter 38 are H level signals, and 40 is the output terminal of the AND gate 39, which is used only when an H level signal is output from the output terminal 4o. , 1 for adder/subtractor 8
” are connected in such a way that they supply an addend.

The digital magnetic recording/reproducing apparatus configured as above will be explained below with reference to FIGS. 1 to 4. FIG. 4 is a timing waveform diagram in the configuration of FIG.
d, e, f, and g in the figure show examples of waveforms having the same code points in FIG. 1. Also, t represents the time axis, TI r T
2 +...Tn, Tn+1. . . . each represents a time interval (period io) for each clock.

1 and 4, signals for n tracks reproduced from a magnetic head group 1 are each amplified by an amplifier group 2 and input to a multiplexer 4. In FIG. multiplexer 4
, each input signal is sequentially switched in synchronization with the clock of waveform d, and each input signal is switched at a time t. output. That is, the signal reproduced from the k-th track by the magnetic head 1k is amplified by the amplifier 2 to have a waveform θ.

The waveform eu is selected in a section T by the multiplexer 4, and the shaded portion of the waveform e appears on the output side of the multiplexer 4 as shown in the waveform f. Note that in the interval T2 to Tn, signals of other tracks are selected by the multiplexer 4 and appear in the waveform f, but these are omitted in FIG.

The signal of each track selected by the multiplexer 4 is attenuated by the attenuator 5. Note that the value determining the degree of attenuation of the attenuator 5 is held in the shift register 9 in units of m bits for every four tracks. Here, if the value that determines the attenuation degree of the th track is a constant aGk, then in the interval , the constant Gk appears in the output of the (n-1)th stage register of the shift register 9. shall be. Therefore, the waveform f of the signal of the th track is attenuated by the attenuator 5 by the value obtained from the constant Gk via the decoder 30 in the interval t1. Note that the larger (smaller) the constant Gk is, the smaller (larger) the degree of attenuation is.

The signal attenuated by the attenuator 6 is converted into a digital signal by the MU/D converter 6 in synchronization with the rising edge of the clock. That is, the digital signal of the k-th track is output in two sections as shown by waveform g. In addition, the waveform g
It is assumed that the peak value of represents the magnitude of the digital signal.

Further, in the section T3 to Tn+1, digital signals of other tracks appear in waveform C, but are omitted in FIG.

Now, the operation of this embodiment depending on the magnitude of the output of the A/D converter 6 will be explained below. The detector 31 will be explained with reference to FIG. 1st set separately in comparator 10.35. The second reference digital values are respectively r, , r2 on the waveform g.
Shown as

First, consider the case where the waveform g exceeds the first reference digital value r1 in the section T2. Comparator 1o subtracts ``1''
'' is output. Also, since the comparator 36 outputs an H level signal, it is clear that the output of the AND gate 39 will be an L level signal regardless of the frequency divider 32 and shift register 37. The adder/subtractor 8 does not receive an addend.Therefore, the adder/subtractor 8 is supplied with the subtractor "1".

At this time, the addend/subtractor input terminal of the adder/subtractor 8 is supplied with the constant Gk from the output of the nth stage of the shift register 9, so the adder/subtractor 8 outputs the constant Gk'(Gk'=Gk-1). The signal is output from the shift register 9.

The constant σ' is shifted in synchronization with the clock by the shift register 9, and the (n-1)th clock interval ' from interval T2 is
At rn+1, the signal is output from the (n-1)th stage register of the shift register 9, and is supplied to the attenuator 6 via the decoder 3o. On the other hand, in the same <Tn+1 interval, the signal of the track 4 appears again at the output of the multiplexer 4 as shown in the waveform f, so the waveform f is changed to the attenuator 5 by the constant Gk'(Gk'=Gk-1). is attenuated by At this time, since Gk'<Gk, the output level of the attenuator 6 decreases and is converted into a digital signal by the digital/digital converter 6.

Similarly, the waveform g of the output of the A/D converter 6 is
It is clear that the above operation is repeated as long as the reference digital value r is exceeded, and the constant σ decreases by one step at every time t1 (t,=l'1to).

Next, consider a case where the waveform g is smaller than the first reference digital value r in the interval T2 and is larger than the second reference digital value r2. Since waveform g is smaller than the second reference digital value, comparator 1o does not output a subtraction. Also, since the waveform g is larger than the second reference digital value, the comparator 36 outputs an H level signal, and the output of the AND gate 39 becomes an L level signal regardless of the outputs of the frequency divider 32 and shift register 37. , the adder/subtractor 8 is not added.

As described above, the constant Gk input to the addend/subtractor input terminal of the adder/subtractor 8 is output as is and input to the shift register 9. Therefore, in interval Tn+1, shift register 9
The output of the (n-1)th stage register is a constant Gk as in the interval T, and the degree of attenuation of the attenuator 6 does not change.

Note that when the waveform g exceeds the second reference digital value r2 in the interval T2, the OR gate 36 outputs an H level signal and supplies it to the shift register 37, so the H level signal is output in the interval Tn+2 n clocks later. The signal is output from the shift register 37 and input to the shift register 37 again via the OR gate.

Similarly, once the H level signal is output from the OR gate 36, the H level signal is always outputted to the OR gate 36 every n clocks, regardless of the output of the comparator 35.
h, and this state continues until the reset pulse shown in waveform C is output from the differentiating circuit 33. During this time,
Output terminal 40id regardless of the output of frequency divider 32
Since it is an L level signal, no addend is output to the adder/subtractor 8. In other words, even if the second trunk digital signal output from the A/D converter 6 changes to various levels, if the peak value exceeds the second reference digital value r2, at least the reset pulse ( The value of constant Gk does not change until waveform C) occurs. Furthermore, even if the waveform g is below the second reference digital value r2 in section 2, it is clear that if it exceeds it in another section, for example 'rn++, the constant Gk will not change in the same way.

Next, consider the case where the waveform g changes at a level equal to or lower than the second reference digital value r2. In interval T2, the comparator 10 does not output the subtraction value, and the output is the iL level signal of the comparator 35. At this time, the shift register 37 has been reset by the reset pulse (waveform C) and the output is an L level signal, so the output of the OR gate 36 is an L level signal. Furthermore, since this is the dL level signal output from the shift register 37 when n clocks have elapsed from the interval T2, the output from the OR gate 36 is also an L level signal.

Similarly, the output of the OR gate 36 becomes an L level signal every n clocks.

Under such conditions, the frequency divider 32 outputs a waveform of H as shown in
When the level signal is output, the output of the AND gate 39 becomes an H level signal in the section where the digital signal of the k-th track is input to the A/D converter (this section is set as section 27), and the adder/subtractor 8 Therefore, the output of the adder/subtractor 8 is the constant Gk//(Gk//=Gk
+1) is output and input to the shift register 9. The constant Gk'' is shifted in synchronization with the clock in the shift register 9, and in the (n-1)th clock period from the period T2' (this is referred to as T'n+I), the constant Gk'' is shifted in the shift register 9 in synchronization with the clock. ) is outputted from the register in the second stage and supplied to the attenuator 5 via the decoder 30. On the other hand, in the same interval 'r'n++, the signal of the th track appears again at the output of multiplexer 4, and the constant G
Attenuator 5 attenuates by k'' (+1 to Gk'-〇).At this time, since gk'>Gk, attenuator 5
The output level is increased by one step and converted into a digital signal by the A/D converter 6. Note that the output of the frequency divider 32 has a waveform C
As shown in , the H level signal is generated at time t+ (t+=nt-
o), the output of the AND gate 39 is an H level signal at time t, which corresponds to one clock period.

Similarly, if the waveform C is always below the second reference digital value r2, the above operation is repeated every period of time t2, and it is clear that the constant σ increases every time t2. .

Therefore, the digital signal output from the A/D converter 6 is automatically adjusted by the attenuator 5 so that it falls between the first reference digital value r1 and the second reference digital value r2. As for the other tracks, the level of the digital signal of each trunk is automatically adjusted so as to fall within a certain range, as in the case described above.

As described above, according to this embodiment, the shift registers 9, 3
7 only needs to have n stages, and the length of the H level signal of the frequency divider 32 only needs to be the time t, and it is not necessary to align the switching address and the initial value of the multiplexer 4, so the circuit configuration is simple. be converted into

Furthermore, the repetition period t2 of the frequency divider 32 output is
The frequency division ratio can be freely set by selecting the frequency division ratio, so there is a large degree of freedom in design.

Note that in this embodiment, the first. The second reference digital value is r
. In this case, detection accuracy is further improved.

Further, some MU/D converters output positive and negative input over-detection signals, but the logical sum of these signals may be constructed and the output may be supplied to the adder/subtracter 8 as a subtracted number. In this case, there is no need to separately provide the first reference digital value, and the comparator 1° becomes unnecessary.

Furthermore, the exclusive OR of the upper two bits of the output value of the MU/D converter 6 may be constructed and provided in place of the comparator 35. In this case as well, the circuit configuration becomes simple.

Effects of the Invention The present invention includes a switching means for sequentially switching and selecting reproduction signals reproduced from a plurality of tracks, and a method for attenuating the reproduction signal selected by the switching means and increasing or decreasing the output by increasing or decreasing a preset gain constant. an attenuator that increases or decreases the gain constant; a first storage means that stores the gain constant for each track; an analog-to-digital converter that converts the output of the attenuator into a digital signal; In addition, by including an adder/subtracter that decreases or increases the gain constant of the corresponding track held in the first storage means, the gain of the reproduced signal can be automatically adjusted and a capacitor is not required. This is advantageous in that the number of output terminals of the device can be reduced. Also,
By providing an adder/subtracter that detects that the digital signal exceeds the first reference digital value and decreases the gain constant of the corresponding track held in the first storage means, the structure is simple and Overlevels can be quickly detected and suppressed. Further, a second reference digital value having a lower level than the first reference digital value is provided for each track, and detecting that the digital signal exceeds the second reference digital value;
a second storage means that switches to a set state for each corresponding track; a pulse generation means that generates a pulse that resets the second storage means at regular intervals; By including an adder/subtractor that operates only when the contents of the track are in a reset state and increases the gain constant of the corresponding track, underrange can be corrected reliably with a simple configuration. This makes it possible to realize a digital magnetic recording and reproducing device that can obtain many excellent effects such as miniaturization.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital magnetic recording/reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram of a part thereof, FIG. 3 is a timing waveform diagram in the configuration of FIG. 2, and FIG. 2 is a timing waveform diagram in the configuration of FIG. 1. FIG. 1... Magnetic head group, 2... Amplifier group, 3, 31... Clock input terminal, 4...
...Multiplexer, 5...Attenuator, 6...
... Analog-digital converter, 8... Adder/subtractor, 9, 37... Shift register, 10.
35...Comparator, 3o...Decoder,
31...Detector, 32...Frequency divider, 3
3...Differential circuit, 36...OR gate, 38...Inverter, 39...AND gate. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure g---7rrJr-y491) Mugon Jr'-f 2nd
Figure 3

Claims (3)

[Claims] (1) A switching means that sequentially switches and selects reproduction signals reproduced from a plurality of tracks, and attenuation that attenuates the reproduction signal selected by the switching means and increases or decreases its output by increasing or decreasing a preset gain constant. a first storage means for holding the gain constant for each track;
an analog-to-digital converter that converts the output of the attenuator into a digital signal; and an analog-to-digital converter that reduces or increases the gain constant of the corresponding track held in the first storage means in relation to the magnitude or magnitude of the digital signal. A digital magnetic recording and reproducing device characterized by comprising an adder/subtractor. (2) A patent characterized by comprising an adder/subtractor that detects that the digital signal exceeds a first reference digital value and decreases the gain constant of the corresponding track held in the first storage means. A digital magnetic recording and reproducing apparatus according to claim 1. (3) A second reference digital value having a lower level than the first reference digital value, and a second reference digital value provided for each track, and detecting that the digital signal exceeds the second reference digital value, and a second storage means that switches to a set state; a pulse generation means that generates a pulse that resets the second storage means at regular intervals; and a state in which the contents of the second storage means immediately before being reset are set to a reset state. 2. The digital magnetic recording and reproducing apparatus according to claim 1, further comprising an adder/subtractor that operates only when the gain constant of the corresponding track is increased.