JPH04252472A - Digital signal recording system - Google Patents

Abstract

PURPOSE:To heighten recording density and to suppress the final clock frequency from remarkably increasing when digital data is recorded. CONSTITUTION:The digital data DD of 16 bits consisting of two pairs of data DA1, DA2 of eight bits is converted into codes DF, DG that is the codes of 23 bits and in which no '1' is continued. Control codes rb, db of three bits for DC component control are attached on a converted code of 23 bits, and a code DE of 26 bits consisting of the converted code of 23 bits and the control code of three bits is recorded after NRZI modulation is applied.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording system suitable for application to, for example, a recording and reproducing apparatus that performs encoding (channel coding) on digital data for recording.

0002

[Prior Art] When recording in a digital VTR or
During the manufacture of D-ROM disks, digital data is encoded, ie, channel coded, to match the characteristics of each recording system. Channel coding increases the recording density of the original data,
Frequency characteristics are controlled and self-clocking becomes easier. However, in order to efficiently record a large amount of data such as so-called high-definition video information, a channel coding method is required that can increase the recording density of original data compared to conventional methods. The following will explain the case of a magnetic recording system as an example.

FIG. 7 shows a recording/reproducing system of a digital VTR. In FIG. 7, digital data outputted from a processing circuit 1 of the recording system is subjected to channel coding in a modulator 2. The recorded signal is transmitted to the recording amplifier 3, the rotary transformer 4, and the magnetic head 5.
The data is recorded on the magnetic tape 6 via the magnetic tape 6. Further, the signal reproduced from the magnetic tape 6 by the magnetic head 7 is supplied to a waveform equalizer 10 via a rotary transformer 8 and a regenerative amplifier 9, and is subjected to amplitude compensation and phase compensation in this equalizer 10. A reproduced signal is supplied to a PLL circuit 11 and a synchronization circuit 12. A clock extracted by the self-clock method in the PLL circuit 11 is supplied to the synchronization circuit 12, and serial digital data extracted from the reproduced signal in synchronization with this clock is decoded in the demodulator 13, and the decoded data is is supplied to the processing circuit 14 of the reproduction system.

The main conditions required for channel coding in the above magnetic recording system are as follows. (b) DC components and low frequency components are small. Since the magnetic recording system has differential transfer characteristics and signals are transmitted via a rotating transformer, it is desirable to use a modulation method that minimizes low-frequency power spectrum components as much as possible. In this regard,
DSV (Digital Sum Var) is a parameter corresponding to the DC component of serial digital data.
) is used. DSV is the cumulative addition of the target digital data, with the code “1” considered as +1 and the code “0” as -1.
The closer the value of V is to 0, the smaller the DC component is. In addition, the DSV in a code word of one word is expressed as CDS (CODE WOR
D DIGITAL SUM), and the DSV is obtained by integrating this CDS.

(b) The recording density of the original data is high. Let T1 be the clock cycle when the original data is serially converted and transferred, and Tm be the minimum magnetization reversal interval converted into time when data after channel coding is recorded on a magnetic recording medium. , the density ratio DR can be expressed as DR=Tm/T1. Even if the magnetization reversal interval is the same, the density ratio DR increases as the period T1 of the original data decreases, so the recording density increases as the density ratio DR increases. Since the density ratio DR is 1 when original data is simply NRZ-modulated and recorded, it is required to make the density ratio DR larger than 1.

(c) The clock frequency is relatively low. For example, when converting n-bit original data into an m-bit (m>n) code by channel coding, the final clock frequency will be increased by m/n times, but the smaller the clock frequency, the easier the circuit configuration will be. It is easy and the circuit operation is stable.

Conventional recording codes for 8-bit data include SNRZ (Scrambled NRZ) and SN
RZI, 8-8 conversion code, 8-9 conversion code, 8-10 conversion code, M2 (Miller squared) code, etc. are known, but 8-14 conversion code is a recording code that can further increase the density ratio DR. Proposed. As shown in Figure 8, in the case of 8-14 conversion, 8
Each bit of original data DA is converted into a 14-bit code DB, and this 8-14 converted code DB is further converted into NRZI(n
onreturn-to-zero Inverted
) is converted and recorded. In this case, the 13-bit code DC in the code DB is selected from a 13-bit pattern in which high level "1" and high level "1" are not consecutive. This is because in the NRZI conversion, magnetization reversal occurs only at the code "1" of the code DB, so the magnetization reversal interval is ensured by at least two bits of the code DB. Further, the last dummy bit eb of the code DB is fixed at a low level "0". This dummy bit eb is arranged at the boundary between one 14-bit code DB and the following 14-bit code, and is set between “1” and “1”.
1" is used to prevent consecutive occurrences.

[0008] There are 256 different pieces of data in the 8-bit original data DA, and there are 610 pieces of 13-bit code in which "1" and "1" are not consecutive. A code selected from the 13-bit code DC is assigned to the 256 pieces of original data. As for the allocation method, if CDS, which is the DSV in the word corresponding to the DC component in the 13-bit code, is 0, the 8-bit data DA and the 13-bit code D
It is allocated 1:1 with C. On the other hand, its CDS is 0
If not, a set of a positive CDS sign and a negative CDS sign are assigned to the predetermined 8-bit data DA. The method of selecting one code from the set of 13-bit codes is to select the code so that the DCV approaches 0 as much as possible.

Generally, each 8-bit original data DA is processed in parallel, but each 14-bit code DB is processed after parallel-to-serial conversion. Therefore, if the clock period when the original data DA is serially converted and processed is T1, and the clock period when the 14-bit code DB is serially processed is T2, as is clear from FIG. The number 1 holds true.

[Equation 1] 8・T1=14・T2 That is, T1/T
2=14/8=1.75 Therefore, the final clock frequency will be 1.75 times.

Next, to explain NRZI modulation,
Each simply contains 8-bit original data DA as shown in FIG. 9A.
When serially converting the signal and then converting it to NRZI, the NRZI code (that is, the recording signal itself) shown in FIG. 9B is obtained. In the NRZI code, the value is inverted when the original code is "1", and the value does not change when the original code is "0". In addition, at the stage of the original data DA, there are cases where "1" and "1" are adjacent to each other, and the NRZI
The code level changes from “1” to “0” or from “0” to “1”
”, magnetization reversal of the magnetic recording medium occurs. Then, the reproduced signal becomes a signal obtained by differentiating the recorded signal as shown in FIG. By setting the N part to "0", NRZI demodulation can be performed.
If the shortest interval between adjacent edges of the RZI code is T3, this T3 becomes the minimum magnetization reversal interval and is equal to the clock cycle T1 when serially processing the original data DA. Therefore, the density ratio DR (=
T3/T1) becomes 1.

[0011] Furthermore, the NRZI code corresponding to the code DB, which is a conversion code of each 14 bits shown in FIG. 10A, is shown in FIG. 10B.
The reproduced signal in this case is shown in FIG. 10C. In this code DB, "1" and "1" are never next to each other, so
Assuming that the shortest interval between adjacent NRZI codes is T4, this interval T4 is equal to the period of 2 bits of the code DB. Also, since the clock period T2 of the code DB has a relationship with the clock period T1 of the original data as shown in equation 1, the density ratio DR when this 14-bit code DB is NRZI converted is DR=T4/T1=2・T2/T1=8/7=1.14
becomes.

0012

[Problem to be solved by the invention] As mentioned above, 8-14
If the data is recorded by NRZI modulation after conversion, the density ratio DR will be approximately 1.14, and the final clock frequency will be 1.75 times the original frequency. However, recently there has been a demand for higher density recording, and a density ratio DR greater than 1.14 is required. Furthermore, its density ratio D
It is desirable that when R is increased, the final clock frequency does not become too large. In view of the above, it is an object of the present invention to provide a digital signal recording method that can increase the recording density more than the conventional method and also prevents the final clock frequency from becoming too large.

[0013]

[Means for Solving the Problems] A first digital signal recording method according to the present invention, as shown in FIG. The code is converted into codes DF and DG in which "1" is not consecutive, and 3-bit control codes rb and db for DC component control are added to the converted 23-bit codes DF and DG, and the conversion is performed. A 26-bit code DE consisting of a 23-bit code and its 3-bit control code is NRZI-modulated and recorded.

The second digital signal recording method according to the present invention, as shown in FIG. 1, converts the converted 23-bit code into m bits (1≦m≦22) The sign DF and n bits (n
=23-m) code DG, and insert a 2-bit control code db out of the 3-bit control codes rb and db between the m-bit code DF and the n-bit code DG. , arrange the remaining 1-bit control code rb of the 3-bit control code at the beginning or end of the 26-bit code,
This 1-bit control code rb is used to limit the run length.

[0015]

According to the first digital signal recording method according to the present invention, 16-bit digital data DD consisting of two sets of 8-bit data is converted into a 26-bit code DE. In this case, 3-bit control codes rb, db
By mixing "1" into the value, it is possible to adjust the DSV corresponding to the DC component. Further, assuming that the clock cycle when serially transferring the 16-bit digital data DD is T1, and the clock cycle when serially outputting the 26-bit digital data DE is T5, the following relationship holds true. 16・T1=26・T5 That is, T1/T5
=26/16=1.625 Therefore, the final clock frequency is lower than in the conventional 8-14 conversion.

[0016] Also, the code DE of the 26 bits is “1”
and "1" are never consecutive, so the minimum interval T6 between the edges of the signal obtained by NRZI conversion of the code DE (Fig. 1
(see C) is equal to 2·T5. For example, when applied to a magnetic recording system, the minimum interval T6 between edges becomes the minimum magnetization reversal interval, so the density ratio DR of the magnetic recording system is as follows. DR=T6/T1=2・T5/T1=16/13=
1.23 Therefore, the density ratio DR is larger than that of the conventional 8-14 conversion, and higher density recording is possible.

Furthermore, according to the second digital signal recording method, the converted 23-bit code is divided into an m-bit code DF and an n-bit code DG.
For example, one of the original two sets of 8-bit data DA1 and DA2 can be made to correspond to the m-bit code DF, and the other to the n-bit code, resulting in a total of 16 bits.
The influence of errors can be reduced compared to making the bit data DD correspond to a 23-bit code. Also,
The remaining 1-bit control code r of the 3-bit control code
By placing b at the beginning or end of a 26-bit code, and setting the control code rb to "1" when both the front and rear bits of the control code rb are "0", for example, " The run length, which is the number of times 0'' continues, can be limited, and self-clock operation can be performed reliably.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 5. In this example, the present invention is applied to channel coding in a digital VTR. The channel coding method of this example will be explained with reference to FIG. 1. In this example, 16-bit data DD consisting of two sets of 8-bit data DA1 and DA2 shown in FIG. 1A is used as a unit of conversion. . Each 8-bit data DA1, DA2, . . . is sequentially processed in parallel. Further, a synchronization block is formed by collecting 8-bit data in units of tens or hundreds, and recording and reproduction are performed on the magnetic recording medium in units of synchronization blocks. Hereinafter, 8-bit and 16-bit data before channel coding will be referred to as "original data." Then, the 16-bit original data D
Each of D is converted into a 26-bit code DE shown in FIG. 1B. That is, this example can be considered as a 16-26 conversion, and the 26-bit code after this conversion is hereinafter referred to as a "conversion code."

In the conventional 8-14 conversion shown in FIG. 8, it is necessary to add a dummy bit eb of "0" to every 8 bits of the original data, resulting in large redundancy, whereas in this example, two sets of 8-14 Since bit data is converted in pairs, the redundancy can be reduced and channel coding can be performed more efficiently. In this example, a series of 26-bit conversion codes DE are sequentially converted into serial data, and then further converted into the NRZI code shown in FIG. 1C.
A recording signal consisting of a ZI code is recorded on a recording medium. At this time, a synchronization signal with a predetermined number of bits and a pattern that does not occur under normal conditions is added to the recording signal for each synchronization block.

The 26-bit conversion code DE is sequentially converted from the 1st bit into a 1-bit run length control code rb,
It is divided into a 12-bit code DF, a 2-bit DSV control bit db, and an 11-bit code DG. That is, the DSV control bit db is inserted between code DF and code DG, but its run length control code rb
may be added to the 26th bit. In this case, the 8-bit original data DA1, DA2,... are each 25 bits.
Since there are 6 types, each 16-bit original data DD is 6
There are 5536 (=256·256) ways.

[0021] Also in this example, in order to ensure that the minimum edge interval is 2 bits when NRZI conversion is performed, the 26-bit conversion code DE is the code "1" and the code "1".
” are not adjacent to each other. In this case, there are 377 patterns in which “1” and “1” are not consecutive in the 12-bit code, and among them, the last bit There are 144 patterns in which "1" ends with "1".On the other hand, there are 233 patterns in which "1" and "1" are not consecutive in the 11-bit code, among which the first bit is "1". There are 89 patterns starting with .In addition, among these 12-bit codes and 11-bit codes, "1" and "1" are not consecutive, and the last bit of the 12-bit code is "1". And part 1
Codes obtained by excluding codes whose first bit is "1" become a 12-bit code DF and an 11-bit code DG, respectively.

The number of different combinations of the codes DF and DG is calculated by the following equation. (377.233) - (144.89) = 75025 Therefore, 65 codes were selected from these 75025 codes.
536 codes to 16-bit original data DD 1:1
Assign it with However, in order to allocate these codes DF and DG to the original data DD, one 8-bit original data DA1 in the original data DD should independently correspond to one code DF, and the other 8-bit original data DA2 is made to independently correspond to the other code DG. If the original data DA1 and DA2 are made to correspond to the codes DF and DG independently in this way, even if a random error etc. is mixed into one code, it will only affect one of the original data DA1 or DA2. Therefore, there is an advantage that the error correction probability can be improved.

Specifically, in the 12-bit code DF, "1" and "1" are not consecutive, and the last bit is "
There are 233 (=377-144) patterns that end with "0", and for these patterns, the first bit of the 11-bit code DG can be "1". Therefore, in the 12-bit code DF, By using only those whose last bit is “0”, the 8-bit original data D
233 pieces of A1 and 233 pieces of 8-bit original data DA2 are independently converted into 12-bit codes DF and 11 bits.
It can be made to correspond to the bit code DG. and,
The remaining 13 (=256-233) pieces of original data DA1 and the remaining 13 pieces of original data DA2 are made to correspond as a whole to 23-bit data consisting of code DF and code DG as 16-bit data. do. When the entire code is made to correspond in this manner, the last bit of the 12-bit code DF is "1".

Further, the DSV control bit db in the conversion code DE plays the role of bringing the DSV corresponding to the DC component of the series of codes as close to 0 as possible, so that the DC component approaches 0. Since the recording signal of this example is NRZI modulated, its DSV is the DSV of the NRZI code obtained by further NRZI modulating the converted code DE after 16-26 conversion. Since the level of the NRZI code is inverted when the original data (conversion code DE in this example) is "1", by setting the initial value, the DSV after NRZI conversion can be determined in advance even at the stage of the conversion code DE. can be calculated. For example, if the previous DSV is positive and the contribution of the NRZI code corresponding to the 11-bit code DG to the entire DSV is also positive when the DSV control bit db is “00”, the code To change the contribution to DCV corresponding to DG to negative, its control bit db is set to “10” or “01”.
Set to . At this time, when the last bit of the 12-bit code DF is "1", the bit db is "01".
is selected, and when the last bit is "0", "10" is selected as bit db. In this example, since two DSV control bits db are provided, it is possible to control the DSV value and set it to "1".
can be prevented from occurring two times in a row.

[0025] Regarding the run length control code rb, the initial value in each synchronization block is set to "0", and thereafter, as an example, the codes before and after the code rb are both set to "0". When the code rb is set to “1”, at least one of the preceding and succeeding codes is “1”.
If so, the code rb is set to "0". In the NRZI code, magnetic flux reversal does not occur in the portion where the original data is "0", so if the original data continues to be "0", the clock component for self-clock cannot be extracted. In this example, the code rb prevents consecutive "0"s.

Another example of the run length control code rb is the 11-bit code D before the code rb.
When the 23-bit code consisting of G and the subsequent 12-bit code DF includes, for example, 16 consecutive bits of "0" before and after the code rb, the code rb may be set to "1". . Note that in order to limit the run length of "0", it is possible to select only codes that do not contain more than a predetermined number of consecutive "0"s at the stage of selecting the 12-bit code DF and the 11-bit code DG. Often, such selection and setting of the run length control code rb may be used together.

As mentioned above, in this example, the original data DA1,
By sequentially applying 16-26 conversion to DA2, . . . 2 bytes at a time, a 26-bit conversion code DE with no consecutive "1s" is generated, and the series of conversion codes DE is converted into serial data and further NRZI conversion is performed. By doing so, an NRZI code (FIG. 1C) as a recording signal is generated. Assuming that the clock cycle is T1 when each 8-bit original data DA1 etc. is serially converted and recorded as is, and the clock cycle when the 26-bit conversion code DE is serially converted and sequentially converted to NRZI is T5, as shown in FIG. Therefore, the following equation 2 holds true.

[Math. 2] 16・T1=26・T5 That is, T1/T5
=26/16=1.625If the clock frequency (original frequency) when serially processing the original data DA1 etc. is f1, and the final clock frequency in this example is f5, then f5/f
Since 1=T1/T5 holds true, the final clock frequency in this example is 1.625 times the original frequency according to equation 2. This is an improvement compared to 1.75 times in the case of the conventional 8-14 conversion method.

Further, if the minimum interval between adjacent edges of the NRZI code is T6, this minimum interval T6 is equal to 2 bits of the converted data DE, and T6=2·T5 holds true. Furthermore, since the minimum magnetization reversal interval on the magnetic recording medium is T6, the density ratio DR in this example is calculated as follows using Equation 2. DR=T6/T1=2・T5/T1=16/13=
1.23 This density ratio DR is improved compared to 1.14 in the case of 8-14 conversion, and 16-2 in this example.
Compared to the 8-14 conversion method, the 6-to-14 conversion has the advantage that higher density recording can be performed at a lower clock frequency.

An example of an encoder for performing 16-26 conversion as shown in FIG. 1 will be explained. This encoder corresponds to modulator 2 in the example of FIG. In addition, this encoder uses a 23-bit code consisting of an 11-bit code DG before the code rb and a 12-bit code DF as the run-length control code rb.
Assume that a code is generated that sets the code rb to "1" when 16 consecutive bits of "0" are included before and after b.

FIG. 2 shows the encoder for 16-26 conversion of this example. In FIG. 2, 15 is a frequency dividing circuit with a frequency division ratio of 1/2, and 16 to 19 are parallel 8-bit input/output delays, respectively. A circuit in which delay circuits 17 to 19 are successively connected to a delay circuit 16, and a clock CP1 for original data is divided into a frequency dividing circuit 1.
5 and the clock terminals of each of the delay circuits 16 to 19, and each 8-bit original data DA is supplied to the input section of the first frequency dividing circuit 16. As a result, the output parts of the delay circuits 16 to 19 are supplied with 1 to 4 clocks from the original time, respectively.
The 8-bit original data before the clock is output. Also,
A frequency dividing circuit 15 divides the clock CP1 at a frequency division ratio of 1/2 to generate a clock CP2. This frequency dividing circuit 15 can be reset at any time by a reset pulse RP to synchronize the conversion of the original data DA into 2-byte pairs and sequentially into 26-bit codes.

Reference numerals 20 and 21 indicate parallel 16-bit input/output delay circuits, which supply the output data of delay circuits 16 and 17 in parallel to delay circuit 21, and delay circuits 18 and 19.
is supplied in parallel to the delay circuit 20, and a clock CP is supplied to the clock terminals of these delay circuits 20 and 21, respectively.
Supply 2. Since the frequency of the clock CP2 is 1/2 that of the clock CP1, the delay circuit 20 outputs 16-bit original data P consisting of two sets of 8-bit original data.
1 is output, and the delay circuit 21 outputs 16-bit original data P2 delayed from the original data P1 by two clocks in terms of clock CP1. The original data P1 is supplied to a code map circuit 22 consisting of a read only memory (ROM) and a first CDS detection circuit 23 consisting of a ROM. The code map circuit 22 generates a 23-bit conversion code P3 corresponding to the 16-bit original data P1, and converts this conversion code P3 into a parallel-serial (P-S)
It is supplied to the input section of the conversion circuit 24.

The CDS detection circuit 23 is supplied with a 3-bit code P4 consisting of a run-length control code and a DSV control bit added to the 23-bit conversion code P3, and this first CDS detection circuit 23 Figure 1
control data S1 indicating the CDS of the signal after NRZI conversion of the 11-bit code DG, and control data S2 indicating how many last bits are consecutively "0" in the code DG are generated. 25 is the second part consisting of ROM.
The second CDS detection circuit 26 similarly represents a control bit generator made of ROM, and this second CDS detection circuit 25 is supplied with the 16-bit original data P2 and the 3-bit code P4 output from the delay circuit 21. And this second
The CDS detection circuit 25 of FIG.
Control data S3 indicating the CDS of the signal after NRZI conversion and control data S4 indicating how many first bits are consecutively "0" in the code DF are generated, and control data S1, S2, S3 are generated. and S4 to the control bit generator 26.

This control bit generator 26 includes:
Furthermore, the control data S6 indicating the DSV up to the 12-bit code DF in FIG. C of
The pattern information of the 13-bit code DG in the 26-bit conversion code of FIG. 1B is supplied via the DS detection circuit 23. Correspondingly, the control bit generator 26 generates a 3-bit code P4 consisting of a 2-bit DSV control bit db and a 1-bit run length control code rb for bringing the DSV closer to 0, This code P4 is supplied to the input section of the P-S conversion circuit 24. Further, the control bit generator 26 calculates and outputs the CDS from the 2-bit DSV control bit db of FIG. 1B in the current processing cycle to the 12-bit code DF in the next processing cycle.

Reference numeral 27 indicates a delay circuit, and the delay circuit 27
A clock CP2 is supplied to the clock terminal of the control bit generator 26, and the CDS outputted from the control bit generator 26 is supplied to the DSV accumulator 28 via the delay circuit 27 as control data S5. This DSV accumulator 2
Step 8 calculates DSV by integrating the CDS up to that point. Further, the clock CP2 is supplied to one input terminal of the phase comparator 29, and the clock CP3 outputted from the voltage controlled oscillator (VCO) 30 is applied to a frequency dividing circuit 3 with a frequency division ratio of 1/26.
1 to the other input terminal of the phase comparator 29 as a clock CP4, and the error output of the phase comparator 29 is fed back to the VCO 30. The frequency of the clock CP3 output from the VCO 30 is 26 times the frequency of the clock CP2.

The clocks CP2 and CP3 are supplied to a hold terminal and an output clock terminal of a P-S conversion circuit 24, each having a 26-bit input and a 1-bit output. This allows P
-S conversion circuit 24 sequentially holds the 26-bit conversion code DE in FIG. A recording signal that is an NRZI code is output from the modulation circuit 32. Furthermore, a predetermined bit of synchronization signal is added to the beginning of each synchronization block of the recording signal by a circuit not shown.

FIG. 3 shows the overall operation of the encoder shown in FIG.
In this example, as shown in FIG. 3A, 8-bit original data is divided into DA1, DA2, DA3,
These original data are supplied to the delay circuit 16 in FIG. 2 in the order of . . . and these original data are paired in the order of DA1+DA2, DA3+DA4, .
It shall be... Then, a series of 16 bits of original data DDi (i=‥‥, 1, 2, 3, ‥‥) are each 16
-26 conversion is performed to form a 26-bit converted code DEi, and each converted code DEi has a 1-bit run length control code rbi, a 12-bit code D
It is assumed that the control bit is composed of Fi, a 2-bit DSV control bit dbi, and an 11-bit code DGi.

In this case, the original data P1 output from the delay circuit 20 of FIG. 2 is DA1+DA as shown in FIG. 4A.
2 (=DD1), DA3+DA4, ..., the original data P2 output from the delay circuit 21 changes in the order of DA3+DA4, DA5+D as shown in FIG. 4B.
The converted code P3 that changes in the order of A6, . . . and is output from the code map circuit 22 is DF1+ as shown in FIG. 4C.
It changes in the order of DG1, DF2+DG2,... For example, considering a processing cycle in which the original data P1 is DA1+DA2, the control data S1 output from the first CDS detection circuit 23 becomes the CDS with code DG1, and the second
The control data S3 output from the CDS detection circuit 25 becomes a CDS with code DF2.

Furthermore, the control data S5 output from the delay circuit 27 is the CDS of DG0+DF1 as shown in FIG. 4D.
(actually also includes CDS such as control code rb1), and control data S6 indicating DSV up to code DF1 is supplied from the DSV accumulator 28 to the control bit generator 26. Therefore, the control bit generator 26 determines the value of the DSV control bit db1 so that the value of the DSV approaches zero. Furthermore, since the run length control code rb2 of the next cycle is uniquely determined by the control data S2 and S4, the value of the code P4 supplied from the control bit generation circuit 26 to the P-S conversion circuit 24 is as shown in FIG. 4E. As shown in , db1+rb2. run length control code rb
, a delay circuit is provided at the input section of the P-S conversion circuit 24, and data rb1 from one cycle before is used. Then, from time t1 at the beginning of the next cycle, code DE1 in FIG. 3B is serially output from the P-S conversion circuit 24.

Thereafter, in the next processing cycle in which the original data P1 that is the output of the delay circuit 20 is DA3+DA4, the converted code P3 that is the output of the code map circuit 22 is
is DF2+DG2, the control data S1 output from the first CDS detection circuit 23 is a CDS with code DG2, and the control data S3 output from the second CDS detection circuit 25 is code DF3 (not shown in FIG. 3B). ) becomes the CDS. Further, the control data S5 outputted from the delay circuit 27 is the CDS of DG1+DF2 obtained in the previous cycle, and the DSV from the DSV accumulator 28 to the control bit generator 26 up to code DF2.
Control data S6 indicating this is supplied. Therefore, the control bit generator 26 outputs the DSV control bit db
2 can be determined, and the run length control code rb3 for the next cycle can also be determined from the control data S2 and S4.

Next, an example of the configuration of a decoder that performs the inverse transformation of the 16-26 transformation of this example will be explained. In the example of FIG. 7, this decoder includes a PLL circuit 12, a synchronization circuit 12, and a demodulator 1.
Corresponds to a circuit system consisting of 3. FIG. 5 shows the decoder of this example. In FIG. 5, 33 is a PLL circuit, 34 is an N
This is an RZI demodulation circuit, and these PLL circuits 33 and NR
The reproduced data is supplied to the ZI demodulation circuit 34, and the PLL circuit 3
The reproduced data is converted into demodulated data which is serial digital data in the NRZI demodulation circuit 34 in synchronization with the clock CP5 extracted in step 3. This demodulated data corresponds to data obtained by serially converting the conversion code DE in FIG. 1B, but a 26-bit synchronization pattern is added to the beginning of each synchronization block.

D1 to D26 are cascade-connected 1-bit input/output delay circuits, 35 is a synchronization pattern detection circuit, and the demodulated data of the RRZI demodulation circuit 34 is supplied to the first delay circuit D1. Clock CP5 is supplied to the clock terminals of D26 to D26, respectively. A series of 26-bit demodulated data is output in parallel from these delay circuits D1 to D26, and this parallel-output 26-bit demodulated data DJ is supplied to the input section of the synchronization pattern detection circuit 35. This synchronization pattern detection circuit 35 generates a synchronization pattern detection signal that becomes "0" when demodulated data matches a predetermined synchronization pattern. Further, the 26-bit demodulated data DJ is supplied to the input section of a delay circuit (latch circuit) 38 having a 26-bit input and a 23-bit output.

Further, the clock CP5 outputted from the PLL circuit 33 is supplied to a frequency dividing circuit 36 with a frequency division ratio of 1/13, and the clock CP6 outputted from this frequency dividing circuit 36 is supplied with a frequency division ratio of 1/2. is supplied to the frequency dividing circuit 37, and this frequency dividing circuit 3
The clock CP7 output from the delay circuit 38 is supplied to the clock terminal of the delay circuit 38. The frequencies of clocks CP6 and CP7 are 1/13 and 1/2 of the frequency of clock CP5, respectively.
However, according to the relationship shown in FIG. 1, the clock CP6 is equal to the clock when 16-bit original data DD is transferred in parallel, and the clock CP6 is equal to the clock when 8-bit original data is transferred in parallel. The synchronization pattern detection signal of the synchronization pattern detection circuit 35 is supplied to the negative logic reset terminals of the frequency dividing circuits 36 and 37, respectively.

Reference numeral 39 denotes a code map circuit with 23-bit input and 16-bit output, and the 23-bit data output from the delay circuit 38 is supplied to the input section of the code map circuit 39. This code map circuit 39 converts 23-bit input data into 16-bit data by performing the reverse conversion of the code map circuit 22 in FIG.
-8 is supplied to the input section of the conversion circuit 40. A clock CP6 is connected to each of the two clock terminals of this 16-8 conversion circuit 40.
and CP7. This 16-8 conversion circuit 40 is
The input 16-bit data is latched in synchronization with clock CP7, and the latched data is outputted 8 bits at a time in synchronization with clock CP6. Each of these 8-bit output data is the original data DA.

To explain the overall operation of the decoder of FIG. 5, when a synchronization pattern is detected by the synchronization pattern detection circuit 35, the frequency division circuits 36 and 37 are reset. Then, when the clock CP5 advances by 26 pulses, the next 26 bits of demodulated data DJ are latched by the delay circuit 38 serving as a latch circuit. This latched demodulated data DJ is equal to the 26-bit conversion code DE of FIG. 1B. Further, this delay circuit 38 removes 3-bit data corresponding to the run length control code rb and DSV control bit db of FIG. 1B from the input data and outputs the data. Therefore, the code map circuit 39 uses the code D in the conversion code.
F and DG are supplied, and the code map circuit 39 outputs the 16-bit original data DD of FIG. 1A. Then, when the clock CP5 further advances by 26 pulses, the original data DD is latched into the 16-8 conversion circuit 40,
Then, the 16-8 conversion circuit 40 sequentially outputs 8-bit original data DA1 and DA2 at a frequency twice as high as the frequency at which the original data DD is latched.

Next, see FIG. 6 for another example of 16-26 conversion.
Explain with reference to. In this example, as shown in FIG. 6A, 2
The 16-bit original data DD, which is a pair of the 8-bit original data DA1 and DA2, is used as a unit of conversion, and the 26-bit conversion code DH shown in FIG. 6B is assigned to each of the original data DD. Serial conversion and N
A recording signal is obtained by performing RZI conversion. However, in this example, the conversion code DH is divided into a DSV control bit fb consisting of 3 consecutive bits of data and a code DI consisting of 23 consecutive bits of data.

The 23-bit code DI is selected from 23-bit data in which "1" and "1" are not consecutive. “1” and “1” with 23-bit data
There are 75,025 ways in which the and is not consecutive, and the 65,536 codes DI selected from these are 1:1 and 16
Correspond to the bit original data DD. Also, the 3-bit DSV control bit fb is both “0” before and after.
”, and the central bit
Further, assuming that bit X is "0", when the CDS based on the code DI following these control bits fb is positive, the bit X is set to "1" in order to invert the polarity of the CDS based on the code DI. In this case, since both the front and rear of the bit X are "0", the 26-bit conversion code DH does not have consecutive "1"s as a whole.

In this way, the 26-bit conversion code D of this example
Similarly to the example of FIG. 1, H also does not have consecutive "1"s, so when NRZI conversion is performed, the minimum interval between the edges of the NRZI code becomes a cycle of 2 bits. Therefore, the density ratio DR and the final clock frequency are equal to those of the 16-26 conversion in FIG.
Compared to the -14 conversion method, higher density recording is possible, the circuit configuration is easier, and the operation is more stable.

It should be noted that the present invention is limited to the above-described embodiments, and it goes without saying that various configurations may be made without departing from the gist of the present invention, such as application to the recording of digital data onto an optical disc.

[0049]

According to the present invention, the final clock frequency can be lowered compared to the 8-14 conversion method, and the density ratio DR can be increased when applied to a magnetic recording medium. Therefore, there are advantages in that higher density recording is possible, the circuit configuration is easy, and the operation is stable.

Furthermore, when the converted 23-bit code is divided into an m-bit code and an n-bit code, data in a predetermined range of the two original 8-bit data sets are divided into different codes. By allocating the 8-bit data to 8-bit data, for example, there is an advantage that the probability that a 1-bit error during reproduction affects both of the two sets of 8-bit data can be reduced.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of 16-26 conversion according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of an encoder for 16-26 conversion.

FIG. 3 is a diagram showing the correspondence between a series of original data and conversion codes in the 16-26 conversion.

FIG. 4 is a timing chart diagram for explaining the operation of the circuit in FIG. 2;

FIG. 5 is a configuration diagram showing an example of a decoder for inverse transformation of the 16-26 transformation (16-26 inverse transformation).

FIG. 6 is an explanatory diagram of 16-26 conversion according to another embodiment of the present invention.

FIG. 7 is a configuration diagram showing an example of a recording/reproducing system of a digital VTR.

FIG. 8 is an explanatory diagram of 8-14 conversion.

FIG. 9 is an explanatory diagram when original data is NRZI-modulated as it is.

FIG. 10 is an explanatory diagram when converting codes are NRZI modulated.

[Explanation of symbols]

DD 16-bit original data DA1, DA2 8-bit original data DE 26-bit conversion code DF 12-bit conversion code DG 11-bit conversion code DH 26-bit conversion code DI 23-bit conversion code rb Run-length control code db DSV control bit fb DSV control bit

Claims (2)

[Claims] [Claim 1] 16 data consisting of two sets of 8-bit data
Convert the bit digital data into a 23-bit code with no consecutive 1's, and convert the converted 2
A 3-bit control code for DC component control is added to the 3-bit code, and the 26-bit code consisting of the converted 23-bit code and the 3-bit control code is converted into NRZI.
A digital signal recording method characterized by modulating and recording. Claim 2: The converted 23-bit code is m
Sign of bit (1≦m≦22) and n bit (n=23−
m) code, insert a 2-bit control code of the 3-bit control code between the m-bit code and the n-bit code, and insert a 2-bit control code of the 3-bit control code 2. The digital signal recording system according to claim 1, wherein the remaining 1-bit control code is placed at the beginning or end of the 26-bit code, and the 1-bit control code is used to limit the run length.