JPH0355902B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a data conversion apparatus for converting data bits into channel bits for feeding onto a serial medium.

The invention further relates to a data conversion apparatus for converting channel bits received from a serial medium into data bits.

In the present invention, the medium is a magnetic tape that can be driven along a read/write head. This medium also relates to a data transmission channel. Since data (information) bits can have the value "0" or "1" without any restrictions, there are no restrictions on encoding by the information source. The constraints placed on this data bit are that it be the correct length and that it must occur synchronously. Also, data bits appear in bit cells each time. That is, data bits appear within time intervals of a certain length. A bit cell is empty if one data bit does not occur. There are no restrictions on the generation of data bits. In other words, the generation of data bits is
As is known, it is determined depending on the signal level, the presence or absence of a state change, the waveform in a predetermined direction, etc.

Code elements occur within a series of channel symbols. The channel symbol is a time interval of constant length in which a change of state occurs or does not occur. Preferably, the clock pulse information falls within the stream of channel symbols. In this case, there is no need to use separate tracks or channels for each write, read or transfer. The accuracy of detection during reading or reception of a code element is largely determined by the accuracy of the clock pulses contained in the signal. To this end, the invention preferably introduces as many state changes as possible per a certain number of channel symbols so that a reliable clock signal can be recovered during reading and reception by suitable equipment. Solutions that introduce multiple state changes require the use of encoding that generates multiple state changes.

Prior Art Japanese Patent Publication No. 50-19252 discloses such encoding means for encoding 5-bit information words into 8-bit code words. Each code word has a value "1" as the first code element indicating a change of state. The absolute disadvantage of such a coding scheme is that one code word always has to start with one code element with a change of state. This limitation makes the encoding efficiency relatively low. That is, when encoding a 5-bit information word into an 8-bit code word, the efficiency is (5/8×100)=62.5%.

DISCLOSURE OF THE INVENTION It is an object of the present invention to provide a data conversion device that introduces as many state changes as possible per fixed number of channel symbols and performs relatively efficient encoding.

The data conversion device of the present invention has the features as described in the claims.

By inserting a 1-bit separation pattern between directly consecutive code words using a separation means (keying device), the efficiency of coding can be increased by (8/10 x 100) = 80.
%. This separation pattern introduces a one-state change, so that one-state change can exist between directly consecutive code words.

Furthermore, good storage density can be obtained with non-return to zero modulation.

In order to retrieve the data words from the stored code words, it is necessary to unkey and decode the stored channel symbols.

In the case of receiving an NRZ modulated signal, it is preferable to provide the filter means with a dual binary filter, and in the case of the NRZ-1 modulated signal, the filter means is further provided with a precoder, which is cyclically coupled and thereby Allows a delay of one channel symbol to be introduced. Therefore, the configuration and arrangement can be simplified. For both of these modulation signals it is advantageous to add a full-wave rectifier.

Examples of the invention The present invention will be explained below with reference to the drawings.

The data conversion device of the present invention shown in FIG. Amplifier 9, information shift register 10, complementer (inverter) 12, flip-flop 1
3. It has a precoder 14 and an information terminal 15.

A clock signal source 5 supplies clock pulses at regular intervals in synchronization with the data (information) bits from the information source 1. This synchronization is controlled by a signal on the clock pulse conductor 6, but in this case, the mutual relationship between the information source 1 and the clock signal source 5 as to master/slave is not important and will not be described here. This correlation is shown only by the two-way arrow on the clock pulse conductor 6. The data bits are therefore supplied to the address register 3 in series or in parallel via the multiplex/input signal terminal 2 until the total number of data bits per operating cycle of the device shown in FIG. 1 is m=8. Decoder 4
is activated once per operating cycle under the control of the clock pulses on pulse lead 7 to set the eight data bits of address register 3 to 1.
out of 256 code, thereby addressing the read-only memory (ROM) 8. At the output of this read-only storage device 8 nine code bits are generated which are stored in an information shift register 10 via a read amplifier 9 activated by a signal on the clock pulse line 7. The clock pulse conductor 7 is multiplexed to operate the decoder 4, read amplifier 9 and flip-flop 13 at different times. A read-only memory 8, an address register 3, a decoder 4, a read amplifier 9 and an information shift register 10 constitute an encoder by means of which an 8-bit data word can be converted into a 9-bit code word. do.

Therefore, the capacity of the read-only memory (ROM) 8 is at least 9×256=2354 bits.

Such storage can be arranged in a known manner, for example, in the form of nine memory chips of 256 bits each. Also, read-only storage 8 may be provided with other word locations or other bit locations per word, which may be used for other specific applications. A clock signal source 5 provides equally spaced clock pulses via conductor 11, ten pulses per operating cycle of the apparatus of FIG. Therefore, the information shift register 10 is a flip-flop 1
3 in series and operates as a shift register. The shift pulses are made to not coincide with the read pulses due to interference reasons so that there can be one undisturbed code element per cell of the device 10/13 when one shift pulse appears. When the first shift pulse associated with a given code word appears on line 11, flip-flop 13 is held at the logic value "1", for example under the control of the signal appearing at the branch point of line 7, shown in dotted lines. The 9-bit code word from read-only storage 8 is suitably constructed such that two or more code elements "1" cannot be directly consecutive to each other. The relevant conversion algorithm in this case will be explained below. Information shift register 1
Complementor (inverter) for the sign bit of 0
12, the theoretical value “0” becomes the theoretical value “1”
or vice versa. Therefore, the code element "1" stored in the read-only storage device eventually becomes a non-state-changing element of the medium, and the code element "0"
finally becomes the state change element of the medium. Such a change of state may occur, for example, at the beginning of such an element, such that the element itself assumes one of two values of state. The code word is also suitably constructed so that two or more code elements "0" cannot directly follow each other. In this case, the complementer 12 can be omitted. Flip-flop 13 output signal of complementer 12
and can be supplied for further processing. Complementor 12 and flip-flop 13 constitute a separation (keying) device for generating additional code elements to form separation bits between two successive code words.

The elements stored in the read-only memory are capable of holding a constant value, which can be detected, for example, as a voltage level at their output. The code word containing the additional "1" separation pattern thus formed is passed through a precoder 14, which supplies code elements to the output terminal 15 in accordance with the bit-like code without returning to the zero level. do. In this case, there are two types of means shown below.

(a) NRZ code.

In this case, the first value of the medium state is “0”,
The second value is set to "1". Therefore, a change in the state of the medium results in a 0-1 or 1-0 change in information.

(b) NRZ-1 code.

In this case, the logical value is "1" when there is a change between the two values of the state of the medium, and the logical value is "0" when there is no change.

Precoder 14 is constructed with a feedback loop corresponding to elements 19 and 20, which will be explained later with reference to FIG. If the delay time corresponds to one bit cell, an NRZ-1 code is generated. If the delay time (element 19) corresponds to a 2-bit cell, an NRZ code is generated. The output of the precoder 14 is provided with a transmission amplifier and, in the case of magnetic media, a write coil/write amplifier, these elements not being shown separately.

Code words of other lengths can be formed in a manner similar to that described above. There are two ways to form the code word in this case instead of using a read-only storage device. First of all, the sign bit can only be formed by combinatorial logic. Such measures are extremely rapid. This is because the logic depth of the associated circuitry becomes limited to, for example, 3 to 5 gate delay times. This requires a very large number of gates and is therefore complex in structure, resulting in various problems when designing a suitable integrated circuit, for example by means of an electronic computer, and making testing for errors difficult. Code words can also be formed arithmetically by sequential subtraction operations. Therefore, the code word can be formed using a simple circuit, and the code bits can also be easily generated sequentially. Sequential generation of such code bits is usually not easily accomplished.

Figure 2 shows a code word consisting of nine elements, i.e. directly consecutive values "0" within one code word.
A case is shown in which at most two code elements having . For the sake of convenience, a description of the code element "1" will be omitted here. The first 127 codewords shown in FIG. 2 are asymmetrical, but do not include any associated mirror image codewords. The last 20 codewords are symmetrical, so there are a total of 2x127+20 = 274 codewords. This number is greater than 256 (2 ⁸ ) so that any data word of 8 bits can be correctly translated into such a 9-bit code word. The code conversion algorithm (i.e. the selection of code word/data word combinations) uses sequential weights 1, 2, 4, 7, 13, 24,
This can be achieved by assigning 44, 81 and 149 to the code elements. The properties of these numbers forming part of the infinite series {bj} are bi+b(i+1)+b(i+
2)=b(i+3). This is why the binary number 201
The representation of (11001001) can be calculated as shown below. 201-149=52; 52-44=8; 8-7
= 1, so the representation as a code word is
It becomes 101001001. This means that three or more code elements "1" cannot be directly consecutive to each other. The reason is that if three or more code elements "1" appear directly in succession, bi = b (i + 1) = b (i + 2)
= 1, and therefore the value of b(i+3) automatically becomes 1 according to a predetermined algorithm. Therefore, with such a code, the value 0 to (149 +
81+24+13+4+2)=273 can be displayed. These symbols are shown in FIG. In principle, a very large number of combinations are possible for translating an 8-bit information word into a 9-bit code word.

As mentioned above, the code word is inverted to 10 code bits by one additional code element (j code bit element). This additional code element causes constant state changes and thus limits the distance between successive state change instants from changing. Since the signal bandwidth cannot be extended to zero frequency, the systematic level shift (bias distortion) is so small that it is almost unaffected.

In this way 8 data bits can be converted by one element into one code word which is inverted into ten code elements. In this way an efficiency of 80% can be obtained. This efficiency is a good percentage in practice. Also, because the lengths of data words and code words are limited, the capacity of, for example, the read-only storage device 8 of FIG. 1 does not need to be extremely large. Furthermore, since the code words are each separated from each other by one additional code element, the risk of error propagation between the various data words is also reduced. Alternatively, two or more additional code elements can be inserted between each pair of code words, for example by doubling the flip-flops 13. Still other conversions may be used, such as 7 data bits to 8 code bits. In this case, the efficiency is limited to 7 pairs (8+1)=about 78%. However, it is not possible to convert, for example, 10 data bits into 11 code bits. The reason is that in this case the code word is 927.
Furthermore, when converting 10 data bits to 12 code bits, the efficiency is as low as 10:(12+1)=77%. In this regard, FIG. 4 shows the relationship between n, p, q, m and s. where n is the number of code bits, p is the number of different code words that can be formed by at most two directly consecutive code elements "0", q is the highest power of 2 equal to at most p, m is
2lnq and s represent m pairs (n+1), respectively. It is clear that various advantageous combinations can be obtained from these factors. That is, the conversion for m = 8 is only effective for long codewords, and for n = 17 it requires 6 x 10 ⁵ bits of read-only storage for an efficiency improvement of, say, 4%. . However, in some cases this may be useful. There are also cases where 2/2 conversion (converting 2 information bits into 2 code bits) is extremely effective. The reason is that only extremely simple equipment may be required. In this case, the read-only storage device 8 of FIG. 1 can be omitted, and the terminal 2 is therefore directly connected to the shift register 10. In this way, an efficiency of 2/3 is obtained. Of course, various other properties are also maintained, such as limiting bandwidth and preventing error propagation.

FIG. 3 shows an apparatus for reading or receiving data bits according to the present invention. The left device is input terminal 1
6, dual binary filter 17, modulo 2 device 18, delay element 19, modulo 2 addition element 20, clock pulse extractor 21, clock pulse generator 22, clock pulse conductor group 2
3, 23A, address register 24, decoder 2
5, read-only storage device 26, read amplifier 27, information shift register 28 and information output terminal 29
It is composed of

Between the terminals 15 (FIG. 1) and 16 (FIG. 3) there is interposed an information carrying medium, for example a magnetic layer, on one side of which a write head and associated write amplifier are arranged, and on the other side, the read side Alternatively, a read head and read amplifier are placed on the receiving side. This type of read head exhibits differential operation, so that a change in the state of the medium between two values results in a response that can be expressed as, for example, f(t) = f ₀ versus (1 + t ² /t ² / ₀ ). become. where t is the time, t ₀ is the characteristic length of time determined by the joint effect of the characteristics of the medium and the information transfer rate to the reading/receiving point and the reading device, such as the read head and read amplifier, and f ₀ is the characteristic length of time. It is a constant of proportionality. This waveform arrives at input terminal 16. Magnetic change is 1/T=
When occurring at a rate of 1/k·t ₀ (where T is the minimum separation time), the entire signal arriving at the input terminal 16 can be expressed as the sum of a number of terms as shown below.

s(t)= _+N 〓 ^n=-N _ao・f(t−nT) In this case _ao = ± depending on whether or not a change of state occurs in one direction or the other at the relevant point. Set to 1 or 0. This state change occurs at an integer multiple of the time interval T from point t=0. The summation in the above equation only needs to be performed over a limited number of state change pulses, taking into account that the apparent effects of noise are always present. Further, k indicates the interval between each separate state change for the temporally expanded effect. For low-density transmission or storage, the value of k is high, for example greater than 3. For high-density transmission or storage, the value of k is low, for example approximately equal to 1, so that interference occurs between successive state changes. Such interference effects can be limited by using a filter 17. As such a filter, it is preferable to use a filter that has the characteristics expressed by the following equation and responds entirely to changes in state.

x(t)=4/π・cos(πt/T)/1−4t ² /T
² This causes a time-sensitive signal to appear on the output side of the filter. This function can be normalized by an initial factor of 4/π. FIG. 8 shows a response characteristic curve when such a filter is used. In FIG. 8, t/T is plotted on the horizontal axis, and the value of x(t) is plotted on the vertical axis. As is clear from this curve, when t/T=0, x(t)=
4/π, t/T=1/2, x(t)=1, t/T=
1, x(t)=4/3π, t/T=3/2, 5/2
Then x(t)=0..., and the amplitude of x(t) is t/T
= 2, 3, etc., it decreases rapidly. This response curve is shown as an example, and it goes without saying that other response curves can be used. This filter is called a transversal filter. Such transversal filters are known. This filter can be implemented using, for example, the bucket brigade shift register described in the article "Bucket Brigade Delay Line" by F.L.G. It is advantageous to form. Regarding this, Figure 5 shows a bucket filter as a transversal filter.
An example of a Brigade filter is shown. This filter circuit consists of five transistors 30-34 and 5
Each capacitor has one plate as one plate and one or two plates as the other plate. Control conductor 4
5 and 47 are alternately connected to the transistor-capacitor pair and activated to turn on the transistor connected thereto and charge the plate of the capacitor connected thereto. In this state, the charges of the odd-numbered and even-numbered capacitors are shifted one position at a time. transistor 30
and capacitor 35 constitute an input buffer stage. Circuit elements 31, 32, 36 and 37
The first shift register stage is configured by the first shift register stage. The capacitors 36 and 37 have a second plate connected to the control conductors 45 and 47 as well as another second plate 4.
1 and 42 are provided, respectively, and these plates 41 and 42 are connected to first and second summing conductors 48 and 46, respectively. The relative surface area of plate 41 is smaller than the relative surface area of plate 42 so that a negative weighting factor is provided to summing leads 48,46. Circuit elements 33, 34, 38, and 39 constitute a second shift register stage. In addition, the electrode plate 4
The relative surface area of plate 44 is larger than the relative surface area of plate 44 so that the positive weighting coefficients are applied to the same connection of the two shift register stages.
Other shift register stages are not shown to simplify the drawing.

FIG. 6 shows a general configuration of a transversal filter. This filter is connected to signal input terminal 4.
9, seven shift register stages 50-56, signal output terminal 57, seven weighting elements 58-64,
It has a summing amplifier 65 and a signal output terminal 66. The time-sensitive signal to be converted arrives at input terminal 49, is sampled and clocked twice.
The period of the pulse, in this example seven periods, is shifted under the control of a clock pulse system, not shown, until it appears at the output terminal 57 for further processing as desired. Each shift register stage is comprised of weighted elements 58-64 similar to those shown in FIG. 5 by capacitor pairs 36/37 and 38/39.
The output signals of these weighted elements are sent to a summing amplifier 65.
can be summed instantaneously or under clock pulse control. In this case, positive or negative weighting factors are retained as described above. The filter signal thus formed becomes available at the output terminal 66 for further processing. If the number of filter stages is odd, the weighting factors will be symmetrical with respect to the center stage of the shift register.

FIG. 7 shows multiple weighting factors for a 19-stage shift register. That is, from the center stage to the previous stage, the weighted factors gradually become smaller, but their symbols change periodically. The number of register stages is determined by considering the accuracy of the conversion, the simplicity of construction, and the possibility of improving accuracy above the level of ever-present interference. The shape of the signal emanating from the receiving head can be improved by a dual binary or Nyquist filter. The invention can also use other types of filters, other shapes of response curves, and other numbers of shift register stages besides the examples described above. Duo binary filter 17 in Figure 3
will be explained in more detail.

For convenience of explanation, FIG. 9 shows a number of time-sensitive signals that occur when using the above-described filter. The second line in the figure shows state change values as an example. The first row shows the associated meaning of the code elements in the case of the NRZ-1 code. Arrange the logical symbols appropriately and set them to “1”
directly indicates the state change that is always relevant. The third line is
The relationship between code elements assigned to state changes in the case of an NRZ code is shown. The fourth line shows the signal obtained at the output of the transversal filter shown in FIG. 5, the curves representing the response to each separate state change. In the area indicated by the vertical dotted line, a response that is the algebraic sum of all responses is sampled. This response is shown in the fifth line with three values: +1, 0, -1.
It is therefore necessary to observe two state changes each time, one located directly before the instant 1/2T and one located directly after the interrogation instant. The reason is that the response at instants 3/2T, 5/2T, etc. is always equal to zero. Minor arrival time shifts are ignored as described above. The same applies for constant time shifts. A constant time shift means that the time axis shifts. Modulo 2 device 18 of FIG. 3 operates as a full wave rectifier thereby producing a signal having the values shown in line 6 of FIG. Full wave rectifiers are known.

The output signal of the modulo-2 device 18 is applied to one input terminal of a modulo-2 summing element 20, which is further supplied with the output signal of the summing element 20 delayed over a time interval of one channel symbol. This delay is performed by a delay element 19. Addition element 20 provides the signals shown in line 7 of FIG. That is, the state of the output signal is changed every time the signal "1" arrives. In this way, the signal of the code element shown in the first row of FIG. 9 is reproduced.

Other means different from those described above will now be described.
That is, the information shown in the first row of FIG. 9 is supplied to one input of a modulo-2 addition element, and the output signal of the same addition element delayed by one channel symbol is supplied to the other input of this addition element. .
In this way, the signal shown in the third row of FIG. 9 is formed, and this signal is transmitted or stored in encoded form as an NRZ code. In this case, the information in the first row of FIG. 9 is directly reproduced on the output side of the Modulo 2 device 18. Therefore, in this example, the delay element 19 and the modulo-2 addition element 20 can be omitted.

The output signal of the modulo-2 adder 20 is supplied to a clock pulse extractor 21. This clock
The pulse extractor is constructed, for example, by a resonant circuit which can be adjusted to the repetition frequency of the channel signal by means of a signal pulse train arriving at the circuit itself. Ten channel symbols occur each time during the operating cycle of the device shown in FIG. The same number of clock pulses generated by the clock pulse generator 22 are supplied to the address register 24 via the conductor 23A. In this case, the first separating bit appearing at the output of this address register configured as a shift register disappears. A clock pulse extractor 21 and a clock pulse generator 2 provide an unkeying device for extracting the additional code elements inserted by the separator during the recording process.
Consisting of 2. After the 10th clock pulse arrives, a complete address is present and conductor 2
When the decoder is activated by the signal 3, the decoder converts 9 address bits into a 1 out of 256 code. As a result, these nine address bits include a redundant code. By introducing such redundancy, 1 out of 512
When forming a code, error signals can be stored in "invalid" word locations. For example, it is possible to store words containing only 0 or "1" in the reserved additional bit positions per word. The word thus addressed is read and amplified by read amplifier 27 before being stored in information shift register 28 via conductor 23. An error detection system, not shown, provides an actuation signal to a clock pulse generator 22 when an error signal is detected so that the pulse generator can delay the separation between two sequential operating cycles by one channel signal. Make it. After one delay period, the correct word location in read-only storage 26 is addressed. A clock pulse generator then sequentially supplies eight equally spaced clock pulses per operating cycle to sequentially reproduce at output terminal 29 the information originally supplied at input signal terminal 2 of FIG. This output terminal 29 can be connected to a utilization device (not shown), for example, a computer. Register 28 can be configured to generate information in parallel and can also be configured to have a buffer function for storing multiple words of information.

The medium can also be, for example, a disk storage device. In this case, the information source 1 and the utilization device in FIG. 1 can have the same configuration. 1st
A large number of circuit elements shown in FIGS. and 3 can be used in common. Furthermore, the clock pulse extractor 21, the clock pulse generator 22 and the utilization device can also be interconnected synchronously.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an example of a data conversion device used in a data bit storage or transmission device according to the present invention, FIG. 2 is an explanatory diagram showing a set of code words, and FIG. FIG. 4 is a block diagram illustrating the construction of an example of a data conversion device for use in reading or receiving information bits; FIG. Fig. 5 is a connection layout diagram showing an example of a bucket brigade used in the device of the present invention, Fig. 6 is a block diagram showing the configuration of an example of a filter used in the device of the present invention, and Fig. 7 is a diagram showing the filter coefficient 1 of such a filter. FIG. 8 is a characteristic diagram showing an example of a response curve of such a filter, and FIG. 9 is a characteristic diagram showing an example of a time-responsive signal when such a filter is used. 1... Information source, 2... Input signal terminal, 3... Address register, 4... Decoder, 5... Clock signal source, 6, 7... Clock pulse conductor, 8
... Read-only storage device, 9 ... Read amplifier, 10
...Information shift register, 11...Clock
Pulse conductor, 12... Complementor, 13...
Flip Flop, 14... Precoder, 15
... Information terminal, 16 ... Input terminal, 17 ... Duo binary filter, 18 ... Modulo 2 device, 19 ... Delay device, 20 ... Modulo 2 adder, 21 ... Clock pulse extractor, 2
2...Clock pulse generator, 23, 23A...
...Clock pulse conductor, 24...Address register, 25...Decoder, 26...Read-only storage device, 27...Read amplifier, 28...Information register, 29...Information output terminal.

Claims (1)

[Scope of Claims] A data conversion device for converting one data bit into channel bits for supplying to a serial medium, comprising: a) receiving said data bits, from which each 8
input means for forming successive data words of bits at a first output; b encoding means supplied from said first output for translating the content of each respective data word into a new code word of nine code bits; and in said new code word of 9 code bits, the maximum number of direct successive code bits with a particular value is equal to 2, and the direct successive number of code bits with the other value is an unlimited number of bits having the other value, such that the sign bit of this other value necessarily causes a change of state in the medium; separating means for forming and inserting the same between two directly consecutive code words; d code bits for each code word supplied by said encoding means and said separating means and separated by said separating bits; 2. A data conversion device comprising: modulation means for performing non-return-to-zero modulation of said state under control of a train of said states and providing said same in the form of channel bits to said medium. 2. A data conversion device for converting channel bits received from a serial medium into data bits, comprising: a) input means for receiving a channel bit string in a non-zero return modulation form; b. receiving the channel bit string from the input means; demodulating means for demodulating the code bits to form alternating sequences of 9-bit code words and 1-bit separation patterns, wherein the direct sequence of code bits having a particular value within any code word is is equal to 2, and the number of directly consecutive code bits having the other value is unlimited, and the other value necessarily causes a change of state in the medium, and the separation pattern is such that the number of sign bits having the other value is c is further supplied from the demodulation means, and the 9
extraction means for extracting the bit code word and blocking said 1-bit separation pattern; d new 8-bit data supplied by said extraction means, decoding the contents of the 9-bit code word and supplying it to the user output; 1. A data conversion device comprising: decoding means for forming words.