CA1095166A - Device for transmitting digital information - Google Patents
Device for transmitting digital informationInfo
- Publication number
- CA1095166A CA1095166A CA278,802A CA278802A CA1095166A CA 1095166 A CA1095166 A CA 1095166A CA 278802 A CA278802 A CA 278802A CA 1095166 A CA1095166 A CA 1095166A
- Authority
- CA
- Canada
- Prior art keywords
- code
- information
- medium
- bits
- words
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Dc Digital Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
PHN. 8407.
ABSTRACT:
The invention provides a coding and decoding system for use with a medium having a bivalent state, for example, a magnetisation direction. Information bits can be received without restriction on an input. The information bits are grouped to form information words of eight bits which are translated to code words of nine bits. The translation is so that no more than two code bits of which none would imply a state transition in the medium directly succeed each other. In the case of a high storage density of means on the receive of the read side, for example, a Nyquist-II filter. In order to enable the said restriction to be maintained also between successive code words, a bit is inserted by a keying device on the transmission side between each pair of successive code words, the said bit implying a state transition in the medium. This bit is extracted again on the receive side. A code conversion is thus realised with a coding efficiency of 80%, for which a limited code alphabet suffices. Resynchronisation can be effected with a high accuracy on the basis of the quickly recur-ring transition instants.
ABSTRACT:
The invention provides a coding and decoding system for use with a medium having a bivalent state, for example, a magnetisation direction. Information bits can be received without restriction on an input. The information bits are grouped to form information words of eight bits which are translated to code words of nine bits. The translation is so that no more than two code bits of which none would imply a state transition in the medium directly succeed each other. In the case of a high storage density of means on the receive of the read side, for example, a Nyquist-II filter. In order to enable the said restriction to be maintained also between successive code words, a bit is inserted by a keying device on the transmission side between each pair of successive code words, the said bit implying a state transition in the medium. This bit is extracted again on the receive side. A code conversion is thus realised with a coding efficiency of 80%, for which a limited code alphabet suffices. Resynchronisation can be effected with a high accuracy on the basis of the quickly recur-ring transition instants.
Description
~095166 PHN. 8407.
The invention relates to a device Eor transmitting via a medium or for storing in a medium, through a bivalent state of this medium, the information of binary inormation bi-ts which can be received in a non-restricted succession of bit cells in an input of a provided coding device, each time successive groups ~information words) of _ information bits being formed from the said information bits received in order to form there-from, by means of the coding device, each time agroup of _ code elements (code word), correspon-ding to an information word, in a succession of channel symbols, the value of n being larger than the value of m, the number of successive code ele-ments which'do not imply a state transition withina code word always being smaller than an upper limit below the value of n. The medium may be a magnetisa-ble tape which'can be'driven along a read and/or write head. It may also concern a channel for data transmission. The'invention ~its may have the value "O" or "1" without restriction, so that no further restrictions aré imposed as regards the coding by the information ~ource.' The in$ormation bits need -.
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merely have the correct length and must occur syn-chronously. The information bits each time appear in bit cells, i~e. time intervals of a fixed length in which an information bit occurs or not.
In the latter case, the bit cell is void. No further restrictions are imposed as regards the appearance of the information bits; the appear-ance may consist of a signal level, the ab~ence or presence of a transition, a waveform having a given direction, etc. in accordance with known techniques.
The code elements occur in a succession of channeI sym~ols. A channel symbol is a time in-terval of fixed length in which a state transition occurs or not. It is desirable to incorporate clock pulse information in the flow of channel sym-bbls; in that case it is not necessary to use a separate track or channel which must also be written or read or transm~tted. The~detection accuracy dur-2Q ing reading or receiving of the code eIements isdetermined to a su~stantial degree by the accuracy o~ the clock incorporated in the signal. Therefore, one`of the objects of the invention is to introduce as many state transitions as possible per fixed num-ber 03e channel symbols, in order to enable an appro-priate de~ice to restore a reliable clock signal during reading~Feceiving. To this end, it is known .
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to impose an upper limit as regards the number of suca-e~sive transition-less channel symbols. A suitable code is disclosed in the artlcle by T. Tamura et al.
A coding method in digital magnetic recording, IEEE
S Transactions on magnetics, September 1972, pages 612-613. According to the MNRZ1 coding described therein, four information bits are converted into five code bits, successive occurrence of at the most tWo transi-tion-less code elements being allowed. At the begin-ning and at the end of a code word, at the most one transition-less code element may occur, and in tha-t case there are seventeen feasible code words. This is sufficient to translate information words of four bits, because'there are only sixteen different possi-bilities for this purpose. The one additional codeword can then be reserved for a special purpose.
Thus, five code bits are required for the transla-tion of four information bits; this 4 : 5 ratio is defined as the'efficiency, which in this case amounts to 80~o. The'code words can be linked with-out restriction, because'a succession o~ more than tWo transition-l~ss code~elements will never occur.
Obviously~ this is ad~antageous because only simple control is then recIuired. On the othèr hand, there is a drawback in that in the receive~read device it cannot readil~ be'det'ected which position is to be assignecl the separation betwe'en two successive words.
, .
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Once this choice is incorrect, it can be corrected on~y after detection of a beginning or end of a code word having two successive transition-less code elements and if, moreover, the correct posi-tion of the separation has then been found. Thismay be rather time-consuming, and consti-tutes a major drawback of the known method.
Furthermore, the use of such a code gives rise to problems if a high bit density is used; in that case interference occurs between adjoining channel symbols. Suitable filters are then required for the reception or reading of the information in order to counteract this interference. This necessity occurs notably if reading is effected in a differentiating manner, as is the case for information storage in a mag-netisable medium, It has been found that the restriction as described above tnever more than two successive transition-less code eIements) is t~en affected. This gives rise to the risk of serious errors.
Thè invention has for its object to provide a coding device for the described surroun-dings in which filters of this kind can be used without the said code restriction being affected.
.
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The invention has for its object -to provide a sys-tem for information transmission with optimum ' hiqh transmission density, and with a favourable bandwidth of the required frequency spectrum.
One of the objects in accordance with the inven-tion is to avoid with ce:rtainty the propagation of storage errors from code word to code word.
Storage errors of this kind are always possible, for example, under the influence of e~ternal dis-turbances. The invention has also for its objectto provide a simple coding and decoding device as a result of the use of comparatively short code words.
The invention has for its object to provide high-efficiency storage.' The objects in accordance with the invention are achi'eved in that the output of the coding device is connected to an input of a key-ing device for separating successive code words each time by a num~er of ~ code elements, at least one'of thè said ~ code'eIements implyin~ a transi-tion in the'said state, an output of the said keyingdevice being connected,` via a modulator, to an input ~ of the medium~ the'said modulator controlling a :' modulation of the said state whi'ch does not return to zero. ~he~modulation ~hich does not return to zero~ moreover, offers a favourable'storage density.
An NRZ or an NRZ - 1 modulation may be concerned. ~ ' .
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Preferably, if j = 1 and if m = 8, n = 9, the largest number of consecutively occurring code elements within a code word without at least one of these elements implying a transition of the said state being equal to two. Thus, the same èfficiency (8Q~) is obtained as in the describ.ed system, whilst the said attractive aspects of the invention are main-tained.
Preferably the weights of the relevant elements of a code word relate as the numbers 1, 2, 4, 7, 13, 24, 44, 81, 149. This enables a harmonic and simply programmabIe`translation of the informà-tion words.
The invention also relates to a device lS for receivinq or reading information, comprising an ; input which can be connected to the medium and an output for generating thereon the restored informa-tion bits for further use, the said input being connected to an input of a demodulator which com-2Q prises filtering means and which is associated with the said modulator, an unscrambIing device being connected to the said demodulator for extracting the said i additional code eIements per code word, a decod:ing device being connected to the said output~
The transmission storage device thus obtains an attract:ive Fendant-.
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When an NRZ modulated signal is received, the fil~ering means preferably comprise a duo-binary filter; in the case of an NRZ-l singal, they moreover comprise a precoder which is coupled end-round and which introduces a delay of one channelsymbol. A simple arrangement is thus sufficient.
The addition of a full-wave rectifying member is advan-tageous in both cases.
Coding and decoding are preferably effecte~
while utilising a random access read-only memory.
On the other hand, i~ m = 2, preferably n = 3, a predetermined code element in a code word having the same sequence number in all code words always implying a transition in the said state and not containing information as such, the two other code eIements being assigned to the two information bits ; of the information word in the same sequence and con-taining the information thereof per bit, an output of the coding device being connected, via a modulator, 2Q to an input of the medium, the said modulator con-trolling a modulation of the said state which does not return to zero. A 1:1 correspondence between information bits and information-carrying code ele-ments, obviàusly, makes for a very simple construc-tion o~ the coding device.~ As a result of the intro-duction of an additional information-less code element, the` efficiency of the code becomes 2 : 3, which is not :
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exceptionally low. If a simple coding device is desired, this simple code offers an attractive solution.
The invention will be described in detail hereinaEter with reference to some figures.
Fig. 1 shows a device for the storage or transmis-sion of information bits in accordance with the invention. Fig. 2 shows a set of code words. Fig.
3 shows a device for reading or receiving informa-tion bits in accordance with the invention. Fig. 4 shows a number of reIevant quantities for different lengths of information words and code words. Fig. 5 shows an example of a bucket brigade for use in accordance with the invention. Fig. 6 shows an embodiment of a filter for use in a device in accor-dance with the invention. Fig. 7 shows an example of filter coefficients of such a filter. Fig. 8 shows an example of a response curve of such a fil-ter. Fig. 9 shows an example of time-dependent signals when use is made`of such a filter.
Fig. 1 shows a device for storing or - transmitting information bits in accordance with the invention, comprising a source device 1, an input signal terminal 2, an address register 3, a decoder 4, a clock 5, clock pulse lines 6, 7, 11, a reaa-only memory 8, a read amplifier device 9l , -an information shift register 10, a complementer 12, a flipflop 13, a precoder 14 and an informa-tion terminal 15.
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~ PHN. 8407.
The clock 5 supplies clock pulses at fixed intervals in synchronism with the presenta-tion of information bits by the source device 1.
Signals on the line 6 control ~his synchronisa-tion, the mutual relationship as master and slaveof the units 1 and 5 not being important in this respect. This is indicated by the two-way arrow on the connection 6. The information bits presented are applied in series or in parallel, via the possi-bility multiple connection/input signal terminal 2,to the address register, up to a total of m = 8 information bits per operation cycle of the device shown in Fig. 1. Under the control of a clock pulse on the line 7, the decoder 4 is activated once per said operation cycle, so that the eight information bits in the'address register 3 are converted into a l-out-of-256 code'whereby thè read-only memory 8 is then addressed. The output of t~is read-only memory supplies nine'code bits which are stored,- via 20 the read amplifier 9 which is co-activated by a sig-nal on the'line`7, in the information register 10.
The'line 7 may be of a multiple construction for separate'actuation in time of the eIements 4, 9 and 13 tsee hereinaftert. The read-only memory 8 con-stitute~s, together wi`th'the'elements 3 4, 9 10 con-nected thereto, the encoder for converting the eight bit information words into nine-bit code words.
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Thus, the read-only memory 8 has a capacity of at least 9 x 256 = 2354 bits. This may be realised in known manner, for example, in the form of nine memory chips of 256 bits each. On the other hand, the memory 8 may also comprise further word positions or further bit positions per word which are used for specific other purposes or notO Via the line ll, the clock 5 supplies uniformly spaced clock pulses to a total of ten pulses per operation cycle of the device shown in Fig. 1. As - lQ a result, the information register 10 is operated as a shift register, in series with the flipflop 13. The shift pulses, obviously, do not coincide in an inter-fering manner with the read pulses, so that when a shift pulse appears, a non-disturbed code element is each time pres~ent per cell of thé units 10/13. When the first shift pulse associated with a given code word appears on the lines 10/ll, the flipflop 13 con-tains a logic "1", for example, under the control of a signal then occurring on the branch of the line 7 2Q which is denoted by a broken line. The nine-bit code words from the'read-only memory 8 may be composed so that never more'than two code elements "1" can directly succeed each'other; a relevant converslon algorithm will be'given hereinafter. Subsequently, the code bits of the information register 10 are complemented by the complementer 12, so that "zeroos" are converted ~ ' . ,.,.:, :
~L~9~ PHN . 8 4 0 7 .
into "ones" and vice~ versa. I t .is assumed that a code element "1" stored in the read-only memory ultimately implies a transition-less element in the medium; a code eIeme!nt "0", however, ulti-mateIy implies an eIement with a transition in themedium. A transition of this kind then occurs, for example, at the beginning of such an element, the element itself implying one of the said two values of the state. On the other hand, the code words may also be composed so that never more than two code elements "0" can directly succeed each other;
in that case the complementer 12 can be dispensed with. The output signals of the complementer are then applied to the flipflop 13 for further pro-cessing. The elements stored in the read~only memory obviously maintain a stationary value which can be detected, for example, as a voltage level ; on the output thereof. The code words thus formed, including the additional "1" separation bits, are 2a passed through the precoder 14 which applies the code eIements to the output terminal 15 in accor-dance with a bit-wise code, without return to a zero level. The`re are two possibilities in this respect;
a) The NRZ-code, where the first value of the state of the medium implies a "Q" and the ~ -second value implies a "1". A transition in the ; ` ~
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PHN. 8407.
state of the medium thus is a 0-1 or a 1-0 change over of the information.
b) The NRZ-l code, where a transition between the two values of the state of the medium implies a logic l'l", and the absence of such a transition implies a logic "0". The precoder may comprise a feedback loop which corresponds to the elements 19, 20 of Fig. 3 to be described herein-after. If the delay time amounts to one bit cell, an NRZ-l code occurs. If the delay time (element 19) amounts to two bit ceIls, an NR2 code arises. On the output side of the precoder 14 there may be provided a transmission amplifier or, in the case of a magne-tisable medium, a write coil,/write amplifier, but these elements are not separately shown.
: ; . .
The formation of code words of other lengths can be realised in the same manner as des-cribed above. Instead of the formation by means of a read-only memory, two o~her possibilities exist.
First of all, the code bits can be formed exclusively by means of combinatory logic. On the one hand, this is very fast, because the logic depth of a relevant network may remain limited to, for example, 3, to 5 gate delay times. On the other hand, a very large number of gates is then required, with a very irreg-ular structure, so that the design (for example, by a computer) of a suitable integrated circuit involves serious problems and the testing for possible :
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errors is also difficult. Furthermore, the code words (see hereinafter) can also be arithmeti-cally formed by a number of sequential subtraction operations. This results on the one hand in realisation by means of a simple circuitO On the other hand, the sequential generating of the code bits results in slow opexation. The latter will generally involve insurmountable problems.
Fig. 2 shows a survey of the possible code words of nine elements, at the most two code elements having a value "0" occurring in direct succession within a code word. Most elements "1"
have ~een omitted for the sake of simplicity. The first 127 of the code words shown are non-symmetri-cal, whilst the code words corresponding theretoas a mirror image are not included. The last 20 code words are symmetrical, so that there are
The invention relates to a device Eor transmitting via a medium or for storing in a medium, through a bivalent state of this medium, the information of binary inormation bi-ts which can be received in a non-restricted succession of bit cells in an input of a provided coding device, each time successive groups ~information words) of _ information bits being formed from the said information bits received in order to form there-from, by means of the coding device, each time agroup of _ code elements (code word), correspon-ding to an information word, in a succession of channel symbols, the value of n being larger than the value of m, the number of successive code ele-ments which'do not imply a state transition withina code word always being smaller than an upper limit below the value of n. The medium may be a magnetisa-ble tape which'can be'driven along a read and/or write head. It may also concern a channel for data transmission. The'invention ~its may have the value "O" or "1" without restriction, so that no further restrictions aré imposed as regards the coding by the information ~ource.' The in$ormation bits need -.
- - 2 ~
..
~ 5~ PHN. 8407.
merely have the correct length and must occur syn-chronously. The information bits each time appear in bit cells, i~e. time intervals of a fixed length in which an information bit occurs or not.
In the latter case, the bit cell is void. No further restrictions are imposed as regards the appearance of the information bits; the appear-ance may consist of a signal level, the ab~ence or presence of a transition, a waveform having a given direction, etc. in accordance with known techniques.
The code elements occur in a succession of channeI sym~ols. A channel symbol is a time in-terval of fixed length in which a state transition occurs or not. It is desirable to incorporate clock pulse information in the flow of channel sym-bbls; in that case it is not necessary to use a separate track or channel which must also be written or read or transm~tted. The~detection accuracy dur-2Q ing reading or receiving of the code eIements isdetermined to a su~stantial degree by the accuracy o~ the clock incorporated in the signal. Therefore, one`of the objects of the invention is to introduce as many state transitions as possible per fixed num-ber 03e channel symbols, in order to enable an appro-priate de~ice to restore a reliable clock signal during reading~Feceiving. To this end, it is known .
- 3 - ~
. .
'. '. - ' : .: : .
- . -: .
- : - :
~ Ç~ PHM. 8407.
to impose an upper limit as regards the number of suca-e~sive transition-less channel symbols. A suitable code is disclosed in the artlcle by T. Tamura et al.
A coding method in digital magnetic recording, IEEE
S Transactions on magnetics, September 1972, pages 612-613. According to the MNRZ1 coding described therein, four information bits are converted into five code bits, successive occurrence of at the most tWo transi-tion-less code elements being allowed. At the begin-ning and at the end of a code word, at the most one transition-less code element may occur, and in tha-t case there are seventeen feasible code words. This is sufficient to translate information words of four bits, because'there are only sixteen different possi-bilities for this purpose. The one additional codeword can then be reserved for a special purpose.
Thus, five code bits are required for the transla-tion of four information bits; this 4 : 5 ratio is defined as the'efficiency, which in this case amounts to 80~o. The'code words can be linked with-out restriction, because'a succession o~ more than tWo transition-l~ss code~elements will never occur.
Obviously~ this is ad~antageous because only simple control is then recIuired. On the othèr hand, there is a drawback in that in the receive~read device it cannot readil~ be'det'ected which position is to be assignecl the separation betwe'en two successive words.
, .
~9 ~16 ~ PHN. 8407.
Once this choice is incorrect, it can be corrected on~y after detection of a beginning or end of a code word having two successive transition-less code elements and if, moreover, the correct posi-tion of the separation has then been found. Thismay be rather time-consuming, and consti-tutes a major drawback of the known method.
Furthermore, the use of such a code gives rise to problems if a high bit density is used; in that case interference occurs between adjoining channel symbols. Suitable filters are then required for the reception or reading of the information in order to counteract this interference. This necessity occurs notably if reading is effected in a differentiating manner, as is the case for information storage in a mag-netisable medium, It has been found that the restriction as described above tnever more than two successive transition-less code eIements) is t~en affected. This gives rise to the risk of serious errors.
Thè invention has for its object to provide a coding device for the described surroun-dings in which filters of this kind can be used without the said code restriction being affected.
.
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~ 9 ~ PHN. 8407.
The invention has for its object -to provide a sys-tem for information transmission with optimum ' hiqh transmission density, and with a favourable bandwidth of the required frequency spectrum.
One of the objects in accordance with the inven-tion is to avoid with ce:rtainty the propagation of storage errors from code word to code word.
Storage errors of this kind are always possible, for example, under the influence of e~ternal dis-turbances. The invention has also for its objectto provide a simple coding and decoding device as a result of the use of comparatively short code words.
The invention has for its object to provide high-efficiency storage.' The objects in accordance with the invention are achi'eved in that the output of the coding device is connected to an input of a key-ing device for separating successive code words each time by a num~er of ~ code elements, at least one'of thè said ~ code'eIements implyin~ a transi-tion in the'said state, an output of the said keyingdevice being connected,` via a modulator, to an input ~ of the medium~ the'said modulator controlling a :' modulation of the said state whi'ch does not return to zero. ~he~modulation ~hich does not return to zero~ moreover, offers a favourable'storage density.
An NRZ or an NRZ - 1 modulation may be concerned. ~ ' .
.: .
~ PHN. 8407.
Preferably, if j = 1 and if m = 8, n = 9, the largest number of consecutively occurring code elements within a code word without at least one of these elements implying a transition of the said state being equal to two. Thus, the same èfficiency (8Q~) is obtained as in the describ.ed system, whilst the said attractive aspects of the invention are main-tained.
Preferably the weights of the relevant elements of a code word relate as the numbers 1, 2, 4, 7, 13, 24, 44, 81, 149. This enables a harmonic and simply programmabIe`translation of the informà-tion words.
The invention also relates to a device lS for receivinq or reading information, comprising an ; input which can be connected to the medium and an output for generating thereon the restored informa-tion bits for further use, the said input being connected to an input of a demodulator which com-2Q prises filtering means and which is associated with the said modulator, an unscrambIing device being connected to the said demodulator for extracting the said i additional code eIements per code word, a decod:ing device being connected to the said output~
The transmission storage device thus obtains an attract:ive Fendant-.
:
`: :
.,. . . . . : . . . . .
~ fi9~ PHN. 8407.
When an NRZ modulated signal is received, the fil~ering means preferably comprise a duo-binary filter; in the case of an NRZ-l singal, they moreover comprise a precoder which is coupled end-round and which introduces a delay of one channelsymbol. A simple arrangement is thus sufficient.
The addition of a full-wave rectifying member is advan-tageous in both cases.
Coding and decoding are preferably effecte~
while utilising a random access read-only memory.
On the other hand, i~ m = 2, preferably n = 3, a predetermined code element in a code word having the same sequence number in all code words always implying a transition in the said state and not containing information as such, the two other code eIements being assigned to the two information bits ; of the information word in the same sequence and con-taining the information thereof per bit, an output of the coding device being connected, via a modulator, 2Q to an input of the medium, the said modulator con-trolling a modulation of the said state which does not return to zero. A 1:1 correspondence between information bits and information-carrying code ele-ments, obviàusly, makes for a very simple construc-tion o~ the coding device.~ As a result of the intro-duction of an additional information-less code element, the` efficiency of the code becomes 2 : 3, which is not :
: :
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:' ' , - ~
:~O~S;~ PHN . 8 4 0 7 .
exceptionally low. If a simple coding device is desired, this simple code offers an attractive solution.
The invention will be described in detail hereinaEter with reference to some figures.
Fig. 1 shows a device for the storage or transmis-sion of information bits in accordance with the invention. Fig. 2 shows a set of code words. Fig.
3 shows a device for reading or receiving informa-tion bits in accordance with the invention. Fig. 4 shows a number of reIevant quantities for different lengths of information words and code words. Fig. 5 shows an example of a bucket brigade for use in accordance with the invention. Fig. 6 shows an embodiment of a filter for use in a device in accor-dance with the invention. Fig. 7 shows an example of filter coefficients of such a filter. Fig. 8 shows an example of a response curve of such a fil-ter. Fig. 9 shows an example of time-dependent signals when use is made`of such a filter.
Fig. 1 shows a device for storing or - transmitting information bits in accordance with the invention, comprising a source device 1, an input signal terminal 2, an address register 3, a decoder 4, a clock 5, clock pulse lines 6, 7, 11, a reaa-only memory 8, a read amplifier device 9l , -an information shift register 10, a complementer 12, a flipflop 13, a precoder 14 and an informa-tion terminal 15.
: ' :
, . . . . . . .
~ PHN. 8407.
The clock 5 supplies clock pulses at fixed intervals in synchronism with the presenta-tion of information bits by the source device 1.
Signals on the line 6 control ~his synchronisa-tion, the mutual relationship as master and slaveof the units 1 and 5 not being important in this respect. This is indicated by the two-way arrow on the connection 6. The information bits presented are applied in series or in parallel, via the possi-bility multiple connection/input signal terminal 2,to the address register, up to a total of m = 8 information bits per operation cycle of the device shown in Fig. 1. Under the control of a clock pulse on the line 7, the decoder 4 is activated once per said operation cycle, so that the eight information bits in the'address register 3 are converted into a l-out-of-256 code'whereby thè read-only memory 8 is then addressed. The output of t~is read-only memory supplies nine'code bits which are stored,- via 20 the read amplifier 9 which is co-activated by a sig-nal on the'line`7, in the information register 10.
The'line 7 may be of a multiple construction for separate'actuation in time of the eIements 4, 9 and 13 tsee hereinaftert. The read-only memory 8 con-stitute~s, together wi`th'the'elements 3 4, 9 10 con-nected thereto, the encoder for converting the eight bit information words into nine-bit code words.
. , ; .
, ~,, .
. ~ :
-~5~-~36 PHN. 8407.
Thus, the read-only memory 8 has a capacity of at least 9 x 256 = 2354 bits. This may be realised in known manner, for example, in the form of nine memory chips of 256 bits each. On the other hand, the memory 8 may also comprise further word positions or further bit positions per word which are used for specific other purposes or notO Via the line ll, the clock 5 supplies uniformly spaced clock pulses to a total of ten pulses per operation cycle of the device shown in Fig. 1. As - lQ a result, the information register 10 is operated as a shift register, in series with the flipflop 13. The shift pulses, obviously, do not coincide in an inter-fering manner with the read pulses, so that when a shift pulse appears, a non-disturbed code element is each time pres~ent per cell of thé units 10/13. When the first shift pulse associated with a given code word appears on the lines 10/ll, the flipflop 13 con-tains a logic "1", for example, under the control of a signal then occurring on the branch of the line 7 2Q which is denoted by a broken line. The nine-bit code words from the'read-only memory 8 may be composed so that never more'than two code elements "1" can directly succeed each'other; a relevant converslon algorithm will be'given hereinafter. Subsequently, the code bits of the information register 10 are complemented by the complementer 12, so that "zeroos" are converted ~ ' . ,.,.:, :
~L~9~ PHN . 8 4 0 7 .
into "ones" and vice~ versa. I t .is assumed that a code element "1" stored in the read-only memory ultimately implies a transition-less element in the medium; a code eIeme!nt "0", however, ulti-mateIy implies an eIement with a transition in themedium. A transition of this kind then occurs, for example, at the beginning of such an element, the element itself implying one of the said two values of the state. On the other hand, the code words may also be composed so that never more than two code elements "0" can directly succeed each other;
in that case the complementer 12 can be dispensed with. The output signals of the complementer are then applied to the flipflop 13 for further pro-cessing. The elements stored in the read~only memory obviously maintain a stationary value which can be detected, for example, as a voltage level ; on the output thereof. The code words thus formed, including the additional "1" separation bits, are 2a passed through the precoder 14 which applies the code eIements to the output terminal 15 in accor-dance with a bit-wise code, without return to a zero level. The`re are two possibilities in this respect;
a) The NRZ-code, where the first value of the state of the medium implies a "Q" and the ~ -second value implies a "1". A transition in the ; ` ~
,, . .: . ` ; -. . . `: . `
PHN. 8407.
state of the medium thus is a 0-1 or a 1-0 change over of the information.
b) The NRZ-l code, where a transition between the two values of the state of the medium implies a logic l'l", and the absence of such a transition implies a logic "0". The precoder may comprise a feedback loop which corresponds to the elements 19, 20 of Fig. 3 to be described herein-after. If the delay time amounts to one bit cell, an NRZ-l code occurs. If the delay time (element 19) amounts to two bit ceIls, an NR2 code arises. On the output side of the precoder 14 there may be provided a transmission amplifier or, in the case of a magne-tisable medium, a write coil,/write amplifier, but these elements are not separately shown.
: ; . .
The formation of code words of other lengths can be realised in the same manner as des-cribed above. Instead of the formation by means of a read-only memory, two o~her possibilities exist.
First of all, the code bits can be formed exclusively by means of combinatory logic. On the one hand, this is very fast, because the logic depth of a relevant network may remain limited to, for example, 3, to 5 gate delay times. On the other hand, a very large number of gates is then required, with a very irreg-ular structure, so that the design (for example, by a computer) of a suitable integrated circuit involves serious problems and the testing for possible :
~ .....
:
Lfi~ PHN . 8 4 0 7 .
errors is also difficult. Furthermore, the code words (see hereinafter) can also be arithmeti-cally formed by a number of sequential subtraction operations. This results on the one hand in realisation by means of a simple circuitO On the other hand, the sequential generating of the code bits results in slow opexation. The latter will generally involve insurmountable problems.
Fig. 2 shows a survey of the possible code words of nine elements, at the most two code elements having a value "0" occurring in direct succession within a code word. Most elements "1"
have ~een omitted for the sake of simplicity. The first 127 of the code words shown are non-symmetri-cal, whilst the code words corresponding theretoas a mirror image are not included. The last 20 code words are symmetrical, so that there are
2 x 127 + ~0 = 274 possibilities. This number is larger than 256 (28~, so that any information ~ord of eight bits can he correctly translated to such a 9-~it code word. An algorithm for the code conversion -ti.e. the choice of the combination code word ~ information word~ can be found by assigning the successive weights 1, 2, 4, 7, 13, 24, 44, 81 and 149 to the code eIements. These numbers, ~orming part of an in~inite series bj~ , ~ave the property that bl + b(i + 1~ + b ~î + 2~ = b~i ~ 3). The representation of the .
.
~ $ ~ PHN. 8~07.
binary number 201 (11001001) is calculated as follows:
201 - 149 = 52; 52 - 44 = 8 ; 8 - 7 = l, the repre-sentation as code word then being : 101001001. It can be demonstrated that more than two code elements "1" can never directly succeed each other. This is because, if this were so, bi = b (i + l) = b (i -~2) = 1, so that the value of b (i ~3) in accordance with the given algorithm would automatically have been l.
The code thus enables representation of the "values"
0 to ~149 + 81 + 13 + 4 + 2)= 273 before more than three successive "l" appear. These codes are shown indeed in Fig. 2. In principle a very large number of translations of eight-bit information words to nine-bit code words are possible.
As has already been stated, the code words are complemented to ten-code bits by means of an additional code element. The additional code element always implies a state transition and .
hence the variation in the distance between succes-sive transition instants is limite`d. Notably the bandwidth of the signal does not extend to zero , ~ frequency, so that int`er alia systematic level `~ shifts ~bias distortions) have little or no effect.
Thus, always eight information bits are translat:ed to one code word, complemented to ten ~ code elements by one element. An efficiency of 80~ ~ ~
`` ~ ::: :~ ~: : ;
.
:
, :
f;6 PHN . 8 4 0 7 .
is thus obtained. This has been found to be an attractive percentage in practice. On the other hand, the lengths of the information words and code words are limited, so -that, for example, the capacity of the read-only memory 8 of Fig. 1 need not be very high. l`he code words are each time separated from each other by an additional code element, so that the risk of propagation of errors between the various information words is low. It is alternatively possible to insert two or more additional code elements between each pair of code words, for example, by doubling the flip-flop 13. It is furthermore possible to use other translations, for example, 7 information bits to 8 code bits. The'efficiency is then limited to 7 :
t8 * 1) = approximately 78~. On the other hand, the translation of, for example, 10 information bits to 11 code'bits is not possible, because in that case`there'are only 927 code words. The trans-lation 10/12 offers a lower efficiency of 10 :
C12 ~ 1~ ~ 77%. In this respect, Fig. 4 illustrates the relationship between _ : the number of code bits, p : the numbe`r of different code words which can be'formed thèrefrom with at the most two directly successlve'code'elements "0", ~ : the highest power of 2 whi;ch is at thè most equal to' p,' _ = 2 ln ~, and s - m : (n + 1~; thése factors are shown for some advantagebus com~inations. It has been found that ': . , ,. : , . ': . ' .
~5~ PHN. 8407.
the translation for m = 8 has a favourable yield which is slightly surpassed only for long code words; for n = 17~ for example, a read-only memory of 6 x 105 bits is required for an efficiency improvement of 4%. In some cases this will be jus-tified. On the other hand, a 2/2 translation may in some cases be very attractive, because then only a very simple device is required. Notably the read-only memory 8 of Fig. 1 can be dispensed with, whilst the terminal 2 is connected directly to the shift register 10. In this case an efEiciency of 2/3 iS
still achieved, whilst the other attractive proper-ties of the invention are maintained : limited bandwidth and prevention of error propagation~
Fig. 3 shows a device for reading or receiving information bits in accordance with the invention. The device'comprises an input terminal 16, a duo-bi'nary filter 17, a modulo-2 device 18, a delay element 19, a modulo-2 adding element 20, 2Q a clock pulse~extractor 21, a clock pulse generator .~ 22~ a clock pulse'lLne arrangement 23~ 23Ar an address register 24/ a decoder 25, a read~only memory 261 a read amplifier 27~ an information registe~r 2g and an information output terminal 29.
Between the'terminals 15 (Fig. 1) and 16 the actual information carrying medium is situated, for example,' em~odied in a magnetic layer, on one : ::
~` ' ' ' :
- . . . . .
~ 5~ ~ ~ PHN . 8 4 0 7 .
side of which a write head and associated write ampli~ier are arranged, whilst on the read side or receive side a read head with read ampli~ier is arranged. A read head of this kind often has a differentiating operation, so that a transition between the two values of the state of the medium results in a response which can be represented for example, approximately as f(t) = fo : (1 + t22 ), in which + is the time, to is a characteristic time length which is determined by the cooperating effects of the properties of the medium, the transport speed of the information relative to the read/receive point, and the read means such as the said head and the amplifier , fo is a proportionality constant.
This waveform arrives on the input terminal 16. If the magnetic transitions (can) occur at a rate :
l~T = l/k.to ~wherein T is their minimum separation in the time~, the total signal received on the termi-nal 16 can be written as a sum of a number of terms-~N
sCtt~ = an f(t-nT~
n=~N
Therein, an = + 1 or = O, depending on the occurrence of a state transition in one or the other direction at the`relevant point, or on the absence thereof, respectiveIy. The transitions can~
; 25 occur at integer multiples of the time interval T, ` ~ ~ `', - 18 ~
: :
`: :
~ , PHN. 8407.
as from the point t = 0. Summing need be effected only over a limited number of -transition pulses, on account of the disguising effect of the noise always present. The said quantity k provides the spacing of the individua:L transitions in the rala-tion to their effect which is widened in the time.
For transport or storage at low density, the value of k is high, for example, larger than 3. In the case of high'density, the value of k is lower, for example, approximateIy equal to 1, so that between successive transitions interference phenomena arise.
Symbol interference may then also become detrimen-tal. It has been found that the effect of such interference can be limited by using a filter 17.
An attractive'choice is formed by a filter having a overall response'to a said transition in the state as follows:
x~t~ = 4 cos (~ t/T) ~ 1-4t2~T2 Thus, this represents the time-dependent ; 20 signal on the'output of the filter. The'function i5 normalised by a preliminary factor 4/~T. Fig. 8 shows the response'curve'when such a filter is used.
t/T is horizontally plotted, whilst the value of x(t) is vertically plotted. For tjT = 0, x(t) = 4/ ~ ;
25 for t/T = 1/2, xtt~ = 1; for t/T = 1 : x(t) = 4/3~
for t/T = 23' 25 always x(t~ = 0 etc.~ while the ampli-tude of x(t) at t/T = 2, 3 ... rapidly decrease. The .
- 19 - : ' - . - . - - :.
-. . , , -, ~ . . . .: :'- ' . : ,: .
.. . .
~5~ PHN. 8407.
response curve shown is given by way of example, but other respons~s may also be advantageous. The fil-ter may be embodied in a transversal filter.
Generally, transversal ~:ilters are well-known. An advantageous embodiment is formed by a bucket brigade shift register as described, ~or example, in the article by F.L.J. Sangster, "The bucket-brigade delay line"~ Philips Technical Review 31 (1970), No. 4, p. 51 ff. In this respect, Fig. 5 shows an embodiment of such a bucket brigade as a transversal filter. The circuit comprises five transistors 30-34 and five capacitors 35-39, each of which comprises one first capacitor plate and one or two second capacitor plates.
The`'control lines 45 and 47 are alternately activated, so that the transistors connected thereto become con-ductive and, moreover, the potential of the capacitor plates connected thereto is changed. The charges of the capacitors of odd and even sequence number are then .
shifted by one position. The elements 30 and 35 form 2Q an input buffer stage. The`'eIements 31, 32, 36~ 37 form the' first shi'ft registex stage.' The capacitors 36 and 37 each'comprise,' besides the second capacitor plates connected to the control lines 45, ~7, a further second capacitor plate 41 and 42, respectlvely, which are connected to the'~irst and the second sum-ming line (48, 46~, respectively~ The relative surface - 20 - ~
,, ~95~6~ PHN. 8407.
area of the plate 41 i5 smaller than that of the plate 42, so that a negative weighting coefficient tdefined as such) arises in view of the connection to the summing lines. The elements 33, 34, 38, 39 form the second shift register stage. The relative surface of the plate 43 3.S larger than that of the plate 44, so that a positive weighting coefficient arises in view of the identical connection pattern of the two stages shown. Further stages are not shown for the sake of simplicity.
Fig. 6 is a general survey of a transver-sal filter. This ~ilter comprises a signal input 49, seven shift register stages 50-56, a signal output 57, seven weighting elements 58-64, an adding ampli-fier 65, and a signal output 66. The time-dependent signals to be transformed are received on the input, are are sampled and are shifted, under the control of a clock pulse system not shown, until they appear for further~ use, if desired, on t~e output 57 a~ter, in this case seven,~periods of the double clock pulse.
Each stage comprises-a symbolically denoted weighting element 58 - 64, an embodiment of which is shown in Fig. 5 (capacitor pairs 36/37, 38/39). The output signals of the weighting eIements are summed instan-taneously or in a clocked manner in the addingamplifier 65, the positive/negative weighting factors~
'..
21 -~
:. - ' ' :' ~ G PHN. 8407.
being maintained. The filtered signal thus formed appears on the output 66 for further use. In the case of an odd number of filter stages, the weight-ing factors are symnetrical relative to the central stage of the shift register. Fig. 7 shows a number of weighting factors for a shift register comprising 19 stages. Proceeding from the centre, weighting factors gradually become smaller, be it that period-ically changes of sign occur. The number of stages is determined by considerations as regards accuracy of the transformation on the one hand an simplicit~
of construction and the impossibi'lity of improving the accuracy beyond the leveI of ~he interference always present on thè'other hand. The shape of the signal originating from the receive head -is improved by the duo-binary or Nyquist II filter thus described.
The'invention can in principle'also be`used with' other types of filter, other types of response curves or other numbers of shift register stages. The'ele-ment 17 of ~lg. 3 is thus further elaborated.
For further clarification, Fig. 9 sho~sa number of time-dependent signals occurring when use is made of a filter as described. The'second line shows the'variation of thè values'of the~stater by way of example.' The''first line shbws the'asso-ciated 3neaning of ~he code'elements in the case'of .
, - "
~ PHN. 8~07.
an NR2-1 code. The arrallgement of -the l~gic symbols is chosen for optimum clarity : ~ones~ are always shown directly above the associated state transition.
~he third line shows the meaning of the code elements assigned to the change of state in the case of an NRZ-code. The fourth line shows the signal obtained on the output of the transversal filter shown in Fig. 5, the curves representing the respollses to the individ-ual transitions. At the area of the vertical broken -10 lines, the response (being the algebraic sum of the - total response) is samplea. This response may have the three values +1, O, -1 shown on the fifth line.
Each time only two feasibIe transitions need be observed, i.e. thb5e which are situated directly before ~1/2T~ and directly behind the instant of interrogation, hecause the response at tAe instants
.
~ $ ~ PHN. 8~07.
binary number 201 (11001001) is calculated as follows:
201 - 149 = 52; 52 - 44 = 8 ; 8 - 7 = l, the repre-sentation as code word then being : 101001001. It can be demonstrated that more than two code elements "1" can never directly succeed each other. This is because, if this were so, bi = b (i + l) = b (i -~2) = 1, so that the value of b (i ~3) in accordance with the given algorithm would automatically have been l.
The code thus enables representation of the "values"
0 to ~149 + 81 + 13 + 4 + 2)= 273 before more than three successive "l" appear. These codes are shown indeed in Fig. 2. In principle a very large number of translations of eight-bit information words to nine-bit code words are possible.
As has already been stated, the code words are complemented to ten-code bits by means of an additional code element. The additional code element always implies a state transition and .
hence the variation in the distance between succes-sive transition instants is limite`d. Notably the bandwidth of the signal does not extend to zero , ~ frequency, so that int`er alia systematic level `~ shifts ~bias distortions) have little or no effect.
Thus, always eight information bits are translat:ed to one code word, complemented to ten ~ code elements by one element. An efficiency of 80~ ~ ~
`` ~ ::: :~ ~: : ;
.
:
, :
f;6 PHN . 8 4 0 7 .
is thus obtained. This has been found to be an attractive percentage in practice. On the other hand, the lengths of the information words and code words are limited, so -that, for example, the capacity of the read-only memory 8 of Fig. 1 need not be very high. l`he code words are each time separated from each other by an additional code element, so that the risk of propagation of errors between the various information words is low. It is alternatively possible to insert two or more additional code elements between each pair of code words, for example, by doubling the flip-flop 13. It is furthermore possible to use other translations, for example, 7 information bits to 8 code bits. The'efficiency is then limited to 7 :
t8 * 1) = approximately 78~. On the other hand, the translation of, for example, 10 information bits to 11 code'bits is not possible, because in that case`there'are only 927 code words. The trans-lation 10/12 offers a lower efficiency of 10 :
C12 ~ 1~ ~ 77%. In this respect, Fig. 4 illustrates the relationship between _ : the number of code bits, p : the numbe`r of different code words which can be'formed thèrefrom with at the most two directly successlve'code'elements "0", ~ : the highest power of 2 whi;ch is at thè most equal to' p,' _ = 2 ln ~, and s - m : (n + 1~; thése factors are shown for some advantagebus com~inations. It has been found that ': . , ,. : , . ': . ' .
~5~ PHN. 8407.
the translation for m = 8 has a favourable yield which is slightly surpassed only for long code words; for n = 17~ for example, a read-only memory of 6 x 105 bits is required for an efficiency improvement of 4%. In some cases this will be jus-tified. On the other hand, a 2/2 translation may in some cases be very attractive, because then only a very simple device is required. Notably the read-only memory 8 of Fig. 1 can be dispensed with, whilst the terminal 2 is connected directly to the shift register 10. In this case an efEiciency of 2/3 iS
still achieved, whilst the other attractive proper-ties of the invention are maintained : limited bandwidth and prevention of error propagation~
Fig. 3 shows a device for reading or receiving information bits in accordance with the invention. The device'comprises an input terminal 16, a duo-bi'nary filter 17, a modulo-2 device 18, a delay element 19, a modulo-2 adding element 20, 2Q a clock pulse~extractor 21, a clock pulse generator .~ 22~ a clock pulse'lLne arrangement 23~ 23Ar an address register 24/ a decoder 25, a read~only memory 261 a read amplifier 27~ an information registe~r 2g and an information output terminal 29.
Between the'terminals 15 (Fig. 1) and 16 the actual information carrying medium is situated, for example,' em~odied in a magnetic layer, on one : ::
~` ' ' ' :
- . . . . .
~ 5~ ~ ~ PHN . 8 4 0 7 .
side of which a write head and associated write ampli~ier are arranged, whilst on the read side or receive side a read head with read ampli~ier is arranged. A read head of this kind often has a differentiating operation, so that a transition between the two values of the state of the medium results in a response which can be represented for example, approximately as f(t) = fo : (1 + t22 ), in which + is the time, to is a characteristic time length which is determined by the cooperating effects of the properties of the medium, the transport speed of the information relative to the read/receive point, and the read means such as the said head and the amplifier , fo is a proportionality constant.
This waveform arrives on the input terminal 16. If the magnetic transitions (can) occur at a rate :
l~T = l/k.to ~wherein T is their minimum separation in the time~, the total signal received on the termi-nal 16 can be written as a sum of a number of terms-~N
sCtt~ = an f(t-nT~
n=~N
Therein, an = + 1 or = O, depending on the occurrence of a state transition in one or the other direction at the`relevant point, or on the absence thereof, respectiveIy. The transitions can~
; 25 occur at integer multiples of the time interval T, ` ~ ~ `', - 18 ~
: :
`: :
~ , PHN. 8407.
as from the point t = 0. Summing need be effected only over a limited number of -transition pulses, on account of the disguising effect of the noise always present. The said quantity k provides the spacing of the individua:L transitions in the rala-tion to their effect which is widened in the time.
For transport or storage at low density, the value of k is high, for example, larger than 3. In the case of high'density, the value of k is lower, for example, approximateIy equal to 1, so that between successive transitions interference phenomena arise.
Symbol interference may then also become detrimen-tal. It has been found that the effect of such interference can be limited by using a filter 17.
An attractive'choice is formed by a filter having a overall response'to a said transition in the state as follows:
x~t~ = 4 cos (~ t/T) ~ 1-4t2~T2 Thus, this represents the time-dependent ; 20 signal on the'output of the filter. The'function i5 normalised by a preliminary factor 4/~T. Fig. 8 shows the response'curve'when such a filter is used.
t/T is horizontally plotted, whilst the value of x(t) is vertically plotted. For tjT = 0, x(t) = 4/ ~ ;
25 for t/T = 1/2, xtt~ = 1; for t/T = 1 : x(t) = 4/3~
for t/T = 23' 25 always x(t~ = 0 etc.~ while the ampli-tude of x(t) at t/T = 2, 3 ... rapidly decrease. The .
- 19 - : ' - . - . - - :.
-. . , , -, ~ . . . .: :'- ' . : ,: .
.. . .
~5~ PHN. 8407.
response curve shown is given by way of example, but other respons~s may also be advantageous. The fil-ter may be embodied in a transversal filter.
Generally, transversal ~:ilters are well-known. An advantageous embodiment is formed by a bucket brigade shift register as described, ~or example, in the article by F.L.J. Sangster, "The bucket-brigade delay line"~ Philips Technical Review 31 (1970), No. 4, p. 51 ff. In this respect, Fig. 5 shows an embodiment of such a bucket brigade as a transversal filter. The circuit comprises five transistors 30-34 and five capacitors 35-39, each of which comprises one first capacitor plate and one or two second capacitor plates.
The`'control lines 45 and 47 are alternately activated, so that the transistors connected thereto become con-ductive and, moreover, the potential of the capacitor plates connected thereto is changed. The charges of the capacitors of odd and even sequence number are then .
shifted by one position. The elements 30 and 35 form 2Q an input buffer stage. The`'eIements 31, 32, 36~ 37 form the' first shi'ft registex stage.' The capacitors 36 and 37 each'comprise,' besides the second capacitor plates connected to the control lines 45, ~7, a further second capacitor plate 41 and 42, respectlvely, which are connected to the'~irst and the second sum-ming line (48, 46~, respectively~ The relative surface - 20 - ~
,, ~95~6~ PHN. 8407.
area of the plate 41 i5 smaller than that of the plate 42, so that a negative weighting coefficient tdefined as such) arises in view of the connection to the summing lines. The elements 33, 34, 38, 39 form the second shift register stage. The relative surface of the plate 43 3.S larger than that of the plate 44, so that a positive weighting coefficient arises in view of the identical connection pattern of the two stages shown. Further stages are not shown for the sake of simplicity.
Fig. 6 is a general survey of a transver-sal filter. This ~ilter comprises a signal input 49, seven shift register stages 50-56, a signal output 57, seven weighting elements 58-64, an adding ampli-fier 65, and a signal output 66. The time-dependent signals to be transformed are received on the input, are are sampled and are shifted, under the control of a clock pulse system not shown, until they appear for further~ use, if desired, on t~e output 57 a~ter, in this case seven,~periods of the double clock pulse.
Each stage comprises-a symbolically denoted weighting element 58 - 64, an embodiment of which is shown in Fig. 5 (capacitor pairs 36/37, 38/39). The output signals of the weighting eIements are summed instan-taneously or in a clocked manner in the addingamplifier 65, the positive/negative weighting factors~
'..
21 -~
:. - ' ' :' ~ G PHN. 8407.
being maintained. The filtered signal thus formed appears on the output 66 for further use. In the case of an odd number of filter stages, the weight-ing factors are symnetrical relative to the central stage of the shift register. Fig. 7 shows a number of weighting factors for a shift register comprising 19 stages. Proceeding from the centre, weighting factors gradually become smaller, be it that period-ically changes of sign occur. The number of stages is determined by considerations as regards accuracy of the transformation on the one hand an simplicit~
of construction and the impossibi'lity of improving the accuracy beyond the leveI of ~he interference always present on thè'other hand. The shape of the signal originating from the receive head -is improved by the duo-binary or Nyquist II filter thus described.
The'invention can in principle'also be`used with' other types of filter, other types of response curves or other numbers of shift register stages. The'ele-ment 17 of ~lg. 3 is thus further elaborated.
For further clarification, Fig. 9 sho~sa number of time-dependent signals occurring when use is made of a filter as described. The'second line shows the'variation of thè values'of the~stater by way of example.' The''first line shbws the'asso-ciated 3neaning of ~he code'elements in the case'of .
, - "
~ PHN. 8~07.
an NR2-1 code. The arrallgement of -the l~gic symbols is chosen for optimum clarity : ~ones~ are always shown directly above the associated state transition.
~he third line shows the meaning of the code elements assigned to the change of state in the case of an NRZ-code. The fourth line shows the signal obtained on the output of the transversal filter shown in Fig. 5, the curves representing the respollses to the individ-ual transitions. At the area of the vertical broken -10 lines, the response (being the algebraic sum of the - total response) is samplea. This response may have the three values +1, O, -1 shown on the fifth line.
Each time only two feasibIe transitions need be observed, i.e. thb5e which are situated directly before ~1/2T~ and directly behind the instant of interrogation, hecause the response at tAe instants
3/2T, 5/2T etc., was always identically equal to zero.
Small incidental time-shifts have been ignored in the foregoing; the same is applicable to a fixed time- -2Q shift. The latter~means only a shift of the time axis.
The modulo-2 device 18 of Fig. 3 now operates as`a full-wave rectifier whereby the signal values stated on the sixth line in Pig. 9 are produced. Full-wave rectifiers are known per se.
.
; 25The output signal of the unit 18 is applied to a modulo-2 adding element 2a / which :
': ~
~ ~ ' ~0~5~P~ PHN. 8407.
further receives the output signal of the same element 20 after delay over an interval of one channel symbol. The del~y time is introduced by the delay element 19. The element 20 then supplies the signal shown on the seventh line of Fig. 9 :
each arriving "l" produces a transition in the out-put signal. Comparison reveals that the first line of Fig. 9 has thus been reconstituted.
The following is a further possibility.
The information of the first line of Fig. 9 is applied to a modulo-2- adding eIement, which also receives its own output signal after deIay over one channel symbol. This results in the third line of Fig. 9; this signal is transmitted or stored in coded form as an NRZ-code. In thi~ case the infor-mation o~ the first line of Fig. 9 is directly recovered on the'output of the unit l$ and the units l9/20 can bè dispensed with.
The'output signal of the'unit 20 is 2~ applied to a clock'extractor 2I ~hich may comprise~, for example,' a resonant circuit which can be'adjusted to the repetition frequency of the channel symbols~
by the'series of signal pulses received by the cir-cuit itself. During an operation cycle of the device shown in Fig. 3, each~'time ten channel symbols occur.;
An equal numbe`r of clock pulses are'then applied by ,~ the clock pulse'generator 22, via the line'23A,, ~ 2~ -':
~ , . : ' ' .
~ PHN. 8~07.
to the address register 24 (where the first sepa-ration bit appearing on the output of this address register, constructed as a shift register, is lost).
After the arrival of the tenth clock pulse, a com-plete address is present and a signal on the line 23 activates the decoder, with the result that the latter converts the nine address bi-ts into a l-out-of-256 code. The nine address bits thus con-tain a redundance. It is possible to introduce this redundance in order to form a 1-out-of-512 ~ code, whilst an error signal is then stored in the "invalid" word positions (for example, a word com-prising exclusively zeroes or a "1" in a reserved additional bit position per word~. The word thus addressed is read and stored, the read amplifier 27 also being activated,.in the information regis-- ter 28 vià the line 23. ~n error detection device ~ is not sho~n, but in the case of detection of the .: said error signal, an activation signal can be 2Q applied to the clock pulse generator 22,.with the result that this generator delays the separation between two successive operation cycles by one chan-nel symbol. After a brlef period of time, a correct word position of thb read-only memory 26 is thus addressed~ The clock pulse generator then continu-ously supplies eight uni$ormly spaced clock pulse~
per operation cycle, with the result that the infor-mation originally applied to the input 2 of Fig. 1 is ~ PHN. 8407.
sequentially recovered on the output terminal 29.
The terminal 29 may be connected to a user device not shown, for example, a computer. The register 28 may also be construct0d to output the informa-tion in parallel form, and it may also have abuffer function ~or storing a number of information words.
It is to be noted that the medium may be, for example, a disk memory. In that case it is also possible for the source device 1 o~ Fig. 1 and the user device described in this context to be the same.
A number of elements of the`Figs. 1 and 3 may then be used in common. The` clock extractor 21, the clock 22 and the user device may also be interconnected by a synchronis~tion connection not shown.
~ ' '.
: .
Small incidental time-shifts have been ignored in the foregoing; the same is applicable to a fixed time- -2Q shift. The latter~means only a shift of the time axis.
The modulo-2 device 18 of Fig. 3 now operates as`a full-wave rectifier whereby the signal values stated on the sixth line in Pig. 9 are produced. Full-wave rectifiers are known per se.
.
; 25The output signal of the unit 18 is applied to a modulo-2 adding element 2a / which :
': ~
~ ~ ' ~0~5~P~ PHN. 8407.
further receives the output signal of the same element 20 after delay over an interval of one channel symbol. The del~y time is introduced by the delay element 19. The element 20 then supplies the signal shown on the seventh line of Fig. 9 :
each arriving "l" produces a transition in the out-put signal. Comparison reveals that the first line of Fig. 9 has thus been reconstituted.
The following is a further possibility.
The information of the first line of Fig. 9 is applied to a modulo-2- adding eIement, which also receives its own output signal after deIay over one channel symbol. This results in the third line of Fig. 9; this signal is transmitted or stored in coded form as an NRZ-code. In thi~ case the infor-mation o~ the first line of Fig. 9 is directly recovered on the'output of the unit l$ and the units l9/20 can bè dispensed with.
The'output signal of the'unit 20 is 2~ applied to a clock'extractor 2I ~hich may comprise~, for example,' a resonant circuit which can be'adjusted to the repetition frequency of the channel symbols~
by the'series of signal pulses received by the cir-cuit itself. During an operation cycle of the device shown in Fig. 3, each~'time ten channel symbols occur.;
An equal numbe`r of clock pulses are'then applied by ,~ the clock pulse'generator 22, via the line'23A,, ~ 2~ -':
~ , . : ' ' .
~ PHN. 8~07.
to the address register 24 (where the first sepa-ration bit appearing on the output of this address register, constructed as a shift register, is lost).
After the arrival of the tenth clock pulse, a com-plete address is present and a signal on the line 23 activates the decoder, with the result that the latter converts the nine address bi-ts into a l-out-of-256 code. The nine address bits thus con-tain a redundance. It is possible to introduce this redundance in order to form a 1-out-of-512 ~ code, whilst an error signal is then stored in the "invalid" word positions (for example, a word com-prising exclusively zeroes or a "1" in a reserved additional bit position per word~. The word thus addressed is read and stored, the read amplifier 27 also being activated,.in the information regis-- ter 28 vià the line 23. ~n error detection device ~ is not sho~n, but in the case of detection of the .: said error signal, an activation signal can be 2Q applied to the clock pulse generator 22,.with the result that this generator delays the separation between two successive operation cycles by one chan-nel symbol. After a brlef period of time, a correct word position of thb read-only memory 26 is thus addressed~ The clock pulse generator then continu-ously supplies eight uni$ormly spaced clock pulse~
per operation cycle, with the result that the infor-mation originally applied to the input 2 of Fig. 1 is ~ PHN. 8407.
sequentially recovered on the output terminal 29.
The terminal 29 may be connected to a user device not shown, for example, a computer. The register 28 may also be construct0d to output the informa-tion in parallel form, and it may also have abuffer function ~or storing a number of information words.
It is to be noted that the medium may be, for example, a disk memory. In that case it is also possible for the source device 1 o~ Fig. 1 and the user device described in this context to be the same.
A number of elements of the`Figs. 1 and 3 may then be used in common. The` clock extractor 21, the clock 22 and the user device may also be interconnected by a synchronis~tion connection not shown.
~ ' '.
: .
Claims (13)
THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Device for introducing the information of binary information bits into a medium through a bivalent state of this medium, comprising a coding having input means for receiving said information bits in a non-restricted succession of bit cells, said coding device having means for forming a concate-nation of successive groups of m information bits (information words) from the information bits received and for forming therefrom each time a group of n code elements (code word) corresponding to an information word, in a succession of channel symbols for subse-quent transfer to the output of the coding device, whereby the value of n is larger than the value of and the number of successive code elements which do not imply a state transition within a code word always being smaller than an upper limit below the value of n, said device comprising furthermore a keying device having an input connected to an output of the coding device and being adapted for separating successive code words each time by a number of ? code elements, at least one of the said ? code elements introducing a transition in the said state, an output of the said keying device being connected, via a modulator, to an input of the medium, said modulator controlling a non-return-to-zero modulation of said state.
2. A device as claimed in Claim 1, character-ized in that the modulator is an NRZ-modulator.
3. A device as claimed in Claim 1, character-ized in that the modulator is an NRZ-1 modulator.
4. A device as claimed in Claim 1, character-ized in that ? = 8 and ? = 9, the largest number of code elements successively appearing within a code word with-out at least one of these elements implying a transition in the said state being equal to two
5. A device as claimed in Claim 1 or 4, characterized in that the value of ? = 1.
6. A device as claimed in Claim 4, character-ized in that the weights of the relevant elements of a code word relate as the numbers 1, 2, 4, 7, 13, 24, 44, 81, 149.
7. A device as claimed in Claim 1, 2 or 3, characterized in that said coding device contains a code word alphabet which is stored in a read-only memory and which can be addressed by information words.
8 A device for extracting information bits from a medium, for use with a device as claimed in Claim I, comprising an input which can be connected to the medium and an output for generating thereon the restored information bits for further use, characterized in that said input is connected to an input of a demod-ulator which comprises filtering means and which is associated with the said modulator, an unkeying device being connected to said demodulator for extracting the said ? additional code elements per code word, a decoding device being connected to said output.
9. A device as claimed in Claim 8, character-ized in that in the case of reception of an NRZ-modulated signal, the said filtering means comprise a duo-binary filter.
10. A device as claimed in Claim 8, character-ized in that in the case of reception of an NRZ-1 modulated signal, said filtering means comprises a series connection of a duo-binary filter and a precoder which is coupled end-around and which introduces a delay of one channel symbol.
11. A device as claimed in Claim 9 or 10, characterized in that an output of said duo-binary filter comprises a full-wave rectifier element.
12. A device as claimed in Claim 8, 9 or 10, characterized in that said decoding device contains an alphabet of information words which is stored in a read-only memory and which can be addressed by code words.
PHN. 8407.
PHN. 8407.
13. A device for introducing into a medium through a bivalent state of this medium, the information of binary information bits which can be received in a non-restricted succession of bit cells on an information input, each time successive groups (information words) of ? information bits being formed from the said information bits received in order to form therefrom, by means of a coding device, each time a group of n code elements (code word), corresponding to an information word, in a succession of channel symbols, the value of ? being larger than the value of n, characterized in that ? = 2, ? = 3, a predetermined code element in a code word having the same sequence number in all code words always implying a transition in said state and not containing information as such, the two other code elements being assigned to the two infor-mation bits of the information word in the same sequence and containing the information thereof per bit, an output of the coding device being connected, via a modulator, to an input of the medium, the said modulator controlling a non-return-to-zero mod ulation of the said state.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL7605529A NL7605529A (en) | 1976-05-24 | 1976-05-24 | DEVICE FOR TRANSFERRING DIGITAL INFORMATION. |
| NL7605529 | 1976-05-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1095166A true CA1095166A (en) | 1981-02-03 |
Family
ID=19826248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA278,802A Expired CA1095166A (en) | 1976-05-24 | 1977-05-19 | Device for transmitting digital information |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS52143806A (en) |
| CA (1) | CA1095166A (en) |
| DE (1) | DE2721057C2 (en) |
| FR (1) | FR2353184B1 (en) |
| GB (1) | GB1575728A (en) |
| NL (1) | NL7605529A (en) |
| SE (1) | SE435124B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8601603A (en) * | 1986-06-20 | 1988-01-18 | Philips Nv | CHANNEL CODING DEVICE. |
| NL8702903A (en) * | 1987-12-03 | 1989-07-03 | Philips Nv | METHOD AND APPARATUS FOR RECORDING INFORMATION ON A RECORD CARRIER, AND AN APPARATUS FOR READING THE RECORDED INFORMATION. |
| KR0165441B1 (en) * | 1995-09-18 | 1999-03-20 | 김광호 | Digital data channel encoding and decoding method and its apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3337864A (en) * | 1963-08-01 | 1967-08-22 | Automatic Elect Lab | Duobinary conversion, reconversion and error detection |
| US3641525A (en) * | 1970-08-17 | 1972-02-08 | Ncr Co | Self-clocking five bit record-playback system |
-
1976
- 1976-05-24 NL NL7605529A patent/NL7605529A/en not_active Application Discontinuation
-
1977
- 1977-05-11 DE DE2721057A patent/DE2721057C2/en not_active Expired
- 1977-05-18 SE SE7705879A patent/SE435124B/en unknown
- 1977-05-19 CA CA278,802A patent/CA1095166A/en not_active Expired
- 1977-05-20 GB GB21299/77A patent/GB1575728A/en not_active Expired
- 1977-05-23 FR FR7715760A patent/FR2353184B1/en not_active Expired
- 1977-05-24 JP JP5951177A patent/JPS52143806A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2353184A1 (en) | 1977-12-23 |
| JPH0355902B2 (en) | 1991-08-26 |
| JPS52143806A (en) | 1977-11-30 |
| DE2721057C2 (en) | 1985-09-05 |
| DE2721057A1 (en) | 1977-12-15 |
| FR2353184B1 (en) | 1986-09-26 |
| SE435124B (en) | 1984-09-03 |
| NL7605529A (en) | 1977-11-28 |
| SE7705879L (en) | 1977-11-25 |
| GB1575728A (en) | 1980-09-24 |
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