DE2721057C2 - Arrangement for transmitting digital data - Google Patents

Description

The invention relates to an arrangement for transmitting the information of binary data elements over a medium or for storing this information in a medium by means of a two-valued state variable of this medium, the data elements being received in a sequence of bit cells at an input of a bait and successive groups therefrom (Data words) of m data elements can be formed in order to use the bait to form a respective group of π code elements (code word) corresponding to a data word in a sequence of channel symbols, the value of η being greater than the value of m and wherein in a code word the number of successive code elements which do not signify a state transition is always smaller than an upper limit lower than the value of n, as well as for recovering the information of the binary data elements from the state variable. The medium can be a magnetizable tape that can be driven along a read and / or write head. It can also be a channel for data transmission. The data elements can have the values "0" or "1" without restriction, so that no further restrictions are imposed on the coding by the data source. The data elements only need to have the appropriate length and appear synchronously. The data elements each occur in bit cells, that is, at time intervals with a fixed length, in which a data element occurs or not. In the second case the bit cell is empty. The appearance of the data

3 4

elements no restrictions imposed: anyone can have high data sequence density with low bandwidth

from a signal level, the possible occurrence: one by using relatively short code words

To indicate transition or a pulse shape of a certain direction,

exist, which corresponds to known techniques. According to the invention, this object is achieved by

The code elements occur in a sequence of channel 5 those in the characterizing part of claim 1

Symbols on. A channel symbol is a time interval specified feature.

vall with a fixed length, in which a state transition occurs. This solution according to the invention has the advantage that it occurs or not. Include such. For this a separate track or a memory error are not necessary per se, for example under the separate channel, which or the influence of external disturbances is always possible. A white must be written / read or transmitted. The advantage of the invention is that the aforementioned then the detection accuracy when reading or filtering to avoid interference between when receiving the code elements strongly from the neighboring channel symbols while maintaining the accuracy of the code restriction also included in the signal are applicable.
Clock pulse determines The modulation that does not return to zero is

In order to ensure reliable reading or receiving, there is also an advantageous storage density. It can

Clock signal through an arrangement provided for this purpose is restored by one NRZ or one NRZ-I module to be able to, are as many over - ..; act tion.

would be to introduce a fixed number of channel symbols. 20 It is advantageous if j = 1 and if m - 8 that

It is known that the number of consecutive π = 9 and that within a buzzword the

transition-free channel symbols an upper area ^.? to maximum number of closed occurring code elements

ben. A suitable code in US Pat. No. 3,641,525 is equal to two without at least one of which is one

described. In the MNRZ code status transition described here, this results in the same

four data bits are converted into five code bits 23 efficiency (80%) as with the previously mentioned system

with at most two seamless code elements star while maintaining the advantages mentioned earlier

may occur one after the other. At the beginning and on the invention.

The end of a code word must not exceed a transitional It is advantageous if the weights of the free Code element occur, and in this case there are different elements of a code word such as numbers seventeen possible code words. It is enough to respond to this 30 1, 2, 4, 7, 13, 24, 44, 81, 149. This gives a to map ten words of four bits, because there is only harmonic and easily programmable mapping The one of the data words gives sixteen different possibilities.

Additional code word can also be used for a special purpose. It is also expedient that this is used for the reconstruction purpose. So five code bits are required for the connection of the data elements to the demodulator : 5 is defined as the degree of efficiency, which is used as an advantageous addition,
In this case it is 80%. The code words can continue to be used when receiving an NRZ-modulated signal, because the filter is preferably a duo-binary filter, and when there are never more than two transition-free code elements, the NRZ-I signal also has a A channel symbol can be used to combine successively. Of course, this is a hesitant ring-coupled precoder. Geous in both cases, as this just a simple control is benö- ah addition of a full-wave rectifier is beneficial Untitled. On the other hand, this creates a disadvantage, such a two-way rectification is actually not known from the US Pat. No. 3,337,864 in the receiving / reading arrangement, although it cannot be detected in advance in which position the separation coding is used.

placed between two successive words' 45 encoding and decoding are preferably carried out must become. Once this WC synchronization has been lost using a read-only memory with optional memory, it can only be corrected using an access (ROM).

after a beginning or an end of a code word Another inventive solution of the

with two successive, transition-free code levels. Task in which the bait is built up as far as possible

elements detected and also that is now 50 is characterized in that m = 2, that η = 3,

Speaking position of the separation points found that in a code value a predetermined code element

has been. This can take some time to find the same order number in all code words.

which is a major disadvantage for the known method, always a transition in the mentioned state

means greetings oedeutet and as such no information

Further, such a code poses problems when it holds that the other two code elements are the same a high bit density is used: the sequence of the two data elements occurs when the data interference occurs between adjacent channel symbols. Word are assigned and bit by bit the Informa-In In this case, functions are included when receiving or reading, and that an output of the bait with suitable filters of the data to avoid this interfering with an input of the medium via a modulator necessary. This necessity exists, in particular, is the one that does not return to zero special when differentiating is read, such as B. controls when modulating the mentioned state variable. One Data storage in a magnetizable medium 1: 1 correspondence between data elements and It turns out that the aforementioned data-carrying code elements simplify self-restriction (Never more than two consecutive ones overshadowing the bait considerably. By inserting it aisle-free code elements) is not adhered to. This 65 of an additional code element is the efficiency of the gives the possibility of serious errors. Codes equal 2: 3, which is not very low If a

The object of the invention is to provide a system for data-simple bait is desired, this simple provides

Transmission and / or storage with a code as possible an advantageous solution.

Exemplary embodiments of the invention are explained in more detail below with reference to the drawing.

F i g. 1 shows an arrangement for storing or sending out data elements,

F i g. 2 a lot of code words.

F i g. 3 shows another arrangement for reading and receiving data elements,

F i g. 4 a number of important quantities for different lengths of data words and code words,

F i g. 5 shows an example of a bucket chain store to be used in the invention;

F i g. 6 shows an example of one in an inventive Arrangement of filters to be used,

F i g. 7 shows an example of filter coefficients of such a filter,

F i g. 8 shows an example of an impulse response of such a filter,

F i g. 9 shows an example of time-dependent signals using such a filter.

F i g. 1 shows an arrangement for storing or sending out the data elements according to the invention, the a source arrangement 1, an input signal terminal 2, an address register 3, a decoder 4, a clock generator 5, clock pulse lines 6, 7, 11, a read-only memory 8, a sense amplifier arrangement 9, a data shift register 10, a complementing unit 12, a flip-flop 13 and a precoder 14 as well as a data terminal IS contains

The clock generator 5 supplies clock pulses at regular time intervals synchronously with the representation of data elements by the source arrangement 1. Signals on the line 6 control this synchronization, which of the units 1 and 5 supplies the clock pulses or is controlled by them will. This is indicated by the two-sided arrow direction on the connection 6. The data bits offered are transmitted serially or in parallel via the possibly multiple connection / input signal terminal 2 up to a total of m -8 data bits per operating cycle of the arrangement according to FIG. 1 fed to the address register Under the control of a clock pulse on the line 7, the decoder 4 is activated once in the mentioned operation cycle, whereby the eight data bits in the address register 3 are converted into a 1-out-of-256 code and the read-only memory 8 is addressed. This read-only memory supplies the output with nine code bits which are stored in the data register 10 via the sense amplifier 9, which is also activated by a signal on the line 7. The line 7 can optionally be implemented several times here in order to be able to control the elements 4, 9 and 13 (see below) at separate times. The read-only memory 8, together with the elements 3, 4, 9, 10 connected to it, forms the bait for converting the eight-bit data words into nine-bit code words. The read-only memory 8 thus has a capacity of at least 9x256 = 2354 bits. This can be implemented in a manner known per se, for example in the form of nine memory chips of 256 bits each. On the other hand, the memory 8 can also contain further word positions or further bit positions per word for specific other purposes, or also unused. Via the line 11, the clock generator delivers 5 clock pulses with a uniform spacing up to a total of ten per operating cycle of the arrangement according to FIG. 1. As a result, the data register IG is operated in series scanning rank rrni your flip-flop 13 from a shift register. The pushing impulses are of course not disruptive the read pulses together, so that when a shift pulse occurs always per cell of the units 10/13 an undisturbed code element is available. When the first shift pulse assigned to a specific code word occurs on line 11, it contains the flip-flop 13 a logic "1", for example under the control of a signal occurring on the The dashed branch of the line 7. The nine-bit code words from the read-only memory 8 can It must be built up that never more than two code elements te (1) directly follow one another. A conversion algorithm for this is given below. The Code bits of the data register 10 are processed by the complementing unit 12 so that "zeros" are converted to "ones" are set and vice versa. It is assumed that a code element "1" stored in the read-only memory is a transition-free element in the medium Code element "0", on the other hand, means an element with a transition in the medium. Such a transition occurs, for example, at the beginning of such an element, the element itself bringing with it one of the two mentioned values of the state variable On the other hand, the code words can also be structured in such a way that never more than two code elements "0" follow one another directly, and in this case the complementing unit 12 can be omitted. The output signals of the complementing mechanism are fed to the flip-flop 13 for further transmission. of course a steady-state value, which can be detected, for example, as a voltage level at the output is. The code words formed in this way including the additional "1" separator bits are sent by the precoder 14 of the code elements the output terminal 15 after a bit-by-bit coding without returning to the zero level. There is there are two options:

a) The NRZ code in which the first value of the state variable of the medium means "0" and the second value is "1". A state transition in the medium is either a 0-1 or a 1 -0 transition of the information.

b) The NRZ-I code, in which a transition between the two values of the state variable of the medium means a logical "1" and the absence of such a transition means a logical "0" Pre-decoder can contain a feedback loop, which is to be described below. elements 19 and 20 according to FIG. 3 corresponds to If the delay time is 1 bit cell, an NPZ-I code can result. When the delay time (Element 19) is two bit cells, an NRZ code can result. On the exit side of the

Alternatively, a transmission amplifier or, in the case of a magnetizable medium, a write amplifier may be provided, but these elements are not shown

Code words with other lengths can be formed in the manner described above. Instead of the There are two other options for formation with the help of a read-only memory. In the first place, the code bits can only be formed with combinatorial logic. be det. On the one hand, this works very quickly because the logical Tkfc of a relevant network can remain limited, for example 3 to 5 gate delay times. On the other hand, a multitude of

number of gates with a very irregular structure required, so that the design (for example of a computer) of an integrated circuit in question is great Problems arise and controlling such errors is just as difficult. You can also use the code words (see below) also arithmetically formed by a number of sequential subtraction operations W / den. On the one hand this results in the realization of a simple circuit, on the other hand it is only achieved a slow effect due to the sequential generation of the code bits. The latter becomes insane. general bring insurmountable problems.

Fig. 2 gives an overview of the possible Code words of nine elements, with a maximum of two code elements with a value of "0" directly in one Code word appear closed. For the sake of simplicity, most of the "1" elements are omitted. Included are the first 127 of the reproduced code words

SSVm ^t Tl ^o ir ' ^t: ^^ ti / ähronri Atf Atirrh .ζηίρσρΐιιπσ pntKnrp-

% »^ J .. <« ■■ »·.,.,«. ........... ..._ .....— _, - _{o σ} - multiple code words are not included. The last 20 code words are symmetrical, so there are 2 χ 127 + 20 = 274 possibilities. This number is greater than 256 (2 ⁸ ), so that a data word of eight bits can be uniquely mapped onto such a code word of 9 bits. F.in algorithm for code conversion (i.e. the choice of the combination of code word and data word) can be found by giving the code elements successively the weights of 1, 2, 4, 7, 13, 24, 44, 8 and 149. These numbers, which are part of an infinite series {bj | form have the properties that bi + b (i + l) + b (i +2) -b (i +3). The binary number 201 (11001001) is represented as follows: 201-149 = 52; 52-44-8; 8—7 = 1, which means that the representation as a code word looks like this: 101001001. It can be shown that never more than two code elements "1" follow one another directly. If this should be the case, bi «= b (i +1) = b (i + 2) = 1, then according to the given algorithm the value of b (i + 3) would automatically =! become. The code can be used to represent the "values" from zero to (149 + 81 + 24 + 13 + 4+ 2) = 273 before more than two consecutive "1s" occur. These codes are actually shown inverted in FIG. In principle, a large number of mappings of eight-bit data words onto nine-bit code words are possible.

As already mentioned, the code words start with a additional code element added to up to ten code bits. The additional code element means always a state transition, and thus the variation in the distance between successive ones is limited Transition times. In particular, the bandwidth of the signal does not extend to zero, so that i.a. systematic level shifts (bias distortions) have little or no influence.

In the above-mentioned manner, eight data elements are always converted into one with a single element up to Ten code elements supplemented code word shown. An efficiency of 80% is thus achieved In in practice this proves to be an advantageous percentage. On the other hand, there are the lengths of data words and code words so that, for example, the size of the read-only memory 8 in FIG. 1 not very needs to be large. The code words are separated from each other by an additional code element isolated, reducing the possibility of error propagation between the different data words pi has become extremely small. It is also possible to insert two or more additional ones between each code word pair Insert code elements, for example by doubling the flip-flop Π It is also possible to use other representations, for example 7 data bits on 8 code bits. The efficiency is limited to 7: (8 + 1) = approximately 78%. On the other hand, it is not possible to display 10 data bits on 11 code bits, for example, because only 927 code words exist. The illustration 10/12 gives

ίο the lower efficiency of 10: (12 + 1) «= 77%. 4 shows the relationship between η equals the number of code bits, ρ equals the number of different code words in which there are at most two directly consecutive code elements "0", q equals the greatest power of 2, which equals at most p, m = * \ dq and s = m : (n +1), which applies to some advantageous combinations. It turns out that the representation for m = 8 provides a good yield that can only be exceeded somewhat for very long code words: for π = 17, for example, a read-only memory of 6 × 10 ⁵ bits is required for an efficiency improvement of 4%. In some cases this may be justified. On the other hand, a 2/2 representation can be advantageous in some cases in that only a very simple arrangement is required. In particular, for example in FIG. 1, the read-only memory 8 are omitted, while the connection 2 is connected directly to the shift register 10. In this case, too, an efficiency of ² Iz is achieved while maintaining the other advantageous properties of the invention: limited bandwidth and avoidance of error propagation.

F i g. 3 shows an arrangement for reading or receiving data elements according to the invention. the Station contains an input terminal 16, a duobinary filter 17, a modulo-2 arrangement 18, a delay element 19, a modulo-2 adding element 20, a clock pulse extractor 21, a clock pulse generator 22, a Clock pulse line 23, 23 / \, an address register 24, c-inen Decoder 25, a read-only memory 26, a sense amplifier arrangement 27, a data register 28 and a Data output terminal 29.

The actual data-carrying medium is located between the terminals 15 (FIG. 1) and 16, for example in a magnetic layer with, on the one hand, a write head and an associated write amplifier and embodied in a read head with read amplifier on the reading side or receiving side such a read head has a differentiating effect, so that a transition between the two values of the state variable of the medium has an effect which, for example, is approximately

/ W = Z ₀ :

can be reproduced, where t is the time, to a characteristic time value, which by the collaborating

Properties of the medium, the transmission speed of the data in relation to the reading / receiving point and the reading means, such as the mentioned head and the amplifier, is determined, / o is here a constant of proportionality. The signal form arrives at the input terminal 16. If the magnetic transitions now occur at a speed VT = i / kt o (where T "is their minimal temporal separation), this will occur at the terminal as a whole

16 received signal can be written as a sum of a number of terms:

+ N

s U)

a _n - / (t-nT).

η - -N

Here a “= ± ι or = 0, depending on the occurrence of a state transition in one or the other direction at the point in question or the absence of such a state transition. The transitions can occur with integer multiples of the time interval T from point f = 0. The summation only needs to take place over a limited number of transition pulses due to the concealment effect of the noise that is always present. The previously mentioned variable k indicates the mutual spacing of the individual transitions in relation to their temporal broadening. For a transmission process / storage process at low density, the value of k is large, for example greater than 3. At high density, the value of k is smaller, for example close to 1, so that interference phenomena occur between successive transitions. Symbol interference can also have a disruptive effect. It is found that the influence of such interference can be restricted by using a filter 17. An advantageous choice is a filter with an impulse response at an aforementioned transition in the state variable according to the form:

v /, 1 4 cos ^{X {t} '~ π 1-

This indicates the time-dependent signal at the output of the filter. The function is standardized by a prefactor 4 / Or F i g. 8 shows the impulse response when using such a filter. Horizontally t / T and vertically the value of x (t) is 0

t-yy-c "F« r t / T = 0

= 4 / ~ for i / 7 * = 1/2: 1

■ \ : 4 / 3λ ·, for t / T = y, y always = 0 etc., while

the amplitudes at t / T = 2.3 ... quickly decrease. The given filter curve is meant as an example, while other curves can also be advantageous. The filter can be implemented as a transversal filter. In their generality, transversal filters are in themselves. An advantageous embodiment is the bucket chain store or the bucket chain shift register, which is described, for example, in the article by FLJ Sangster "The bucket-brigade delay line", Phil. Technical Review 31 (1970) No. 4, p. 51 ff. In this context, F i g. 5 shows an embodiment of such a bucket chain store as a transversal filter.

The circuit contains five transistors 30 ... 34 and five capacitors 35 ... 39 each with a first plate and one or two second capacitor plates. the Control lines 45 and 47 are driven alternately, whereby the transistors connected therewith become conductive and also change the potential of the capacitor plates connected to them. Be there the charges of the capacitors with odd or even ordinal numbers shifted by one place. The elements 30 and 35 form an input buffer stage. The elements 31,32,36,37 form the first shift register stage. The capacitors 36 and 37 have, in addition to those connected to the control lines 45 and 47 second capacitor plates a further second capacitor plate 41 or 42, which is connected to the first or the second summing line (48, 46) are connected. The relative surface area of the plate 41 is smaller than that of plate 42, which gives a negative weight coefficient (defined as such) in view of the connection with the summing leads. The elements 33, 34, 38 and 39 form the second shift register stage. The relative surface of the plate 43 is just larger here than that of the plate 44, whereby a positive Weight coefficient arises in view of the identical connection pattern of the two stages shown.

ίο Further levels are not shown for the sake of simplicity been.

In this context, F i g. 6 shows a general overview of a transversal filter. It contains one Signal input 49, seven write register stages 50 ...

56, a signal output 57, seven weight elements 58 ... 64, an adding amplifier 65 and a signal output 66. The time-dependent signals to be transmitted arrive at the input, are scanned and there pushed further under the control of a clock pulse system, not shown, until they are in this case after seven periods of the double clock pulse appear at output 57 for possible further use. Each level is provided with a symbolically represented weighting element 58 ... 64, of which at Fig. 5 (capacitor pairs 36/37, 38/39) an embodiment is given. The output signals of the weighting elements are momentary or clocked in the adding amplifier 65 while maintaining the positive / negative weighting factors are summed up. The filtered signal formed in this way appears for the further Use at output 66. With an odd number of filter stages, the weighting factors are symmetrical with respect to the middle stage of the shift register. In this context, F i g. 7 a Number of weighting factors for a shift register with 19 stages. So starting from the center Weighting factors gradually smaller, however

number is derived from considerations of accuracy of transmission on the one hand and on the other hand determined by the simplest possible structure and the impossibility, to make the accuracy better than the level c.ets of any interference present. By that on this Way described duobinary or Nyquist II filter will take the form of that emanating from the receiving head Signal improved In principle, the invention can also be used with other types of filters, other filter curves and other numbers of shift register stages can be used. So is the element 17 according to FIG. 3 explained in more detail

so In this context, F i g. 9 a number of time-dependent signals for further illustration when using a filter as described above. The second line shows the course of the values of the State variable as an example. The first line gives the assigned meaning of the code elements in the case of a NRZ-1 codes. The representation of the logical symbols is chosen for optimal clarity: the »ones« are always directly above the state transition to the you belong. The third line gives the course of the

eo state variable given meaning of the code elements with an NRZ code.

The fourth line gives that at the output of the transversal filter according to FIG. 5 signal obtained, with the curves indicate the results at the individual transitions. At the point of the vertically drawn dashed-ΐβ « Lines the result (which is the algebraic sum of the total results) is queried for this result can have the three values + 1,0, -1, which are based on the

fifth line are given. Always only need two possible transitions to be noted, namely the transition immediately before (1/27]) and immediately after the . ', question moment, because the result was at the times 3 / 2Ti 5/27 etc. always identical to NuU. In the above description there are further minor random shifts in time are neglected, as is a fixed shift. The latter means yes just a shift in the time axis. The modulo-2 arrangement 18 according to FIG. 3 now works as a two-way rectifier, whereby the signal values of the sixth line in FIG. 9 arise.

The output signal of the unit 18 arrives at a modulo-2 adding element 20, which also receives the output signal of the same element 20 after which it is delayed by a time of a single channel symbol has been. This delay time is brought about by the delay element 19. The element 20 delivers the signal on the seventh line in FIG. 9. Every incoming »K causes a change in the output signal. A comparison shows that the first line in FIG. 9 is newly formed.

Another possibility is as follows. The information in the first line in FIG. 9 get to a modulo-2 adding element, which is further fed to its output signal delayed by one channel symbol. This gives the third line in Fig.9 and is encoded as an NRZ code sent or saved. In this case, the information in the first line in FIG. 9 recovered at the output of the unit 18 and the units 19/20 can now be omitted.

The output signal of the unit 20 passes on to a clock pulse extractor 21, which can contain, for example, an oscillating circuit which can be adjusted to the repetition frequency of the channel symbols by the signal pulse series it receives itself. In an operating cycle of the arrangement according to FIG. 3, ten riänalsyrnbüic occur. The clock pulse generator 22 sends the same number of clock pulses via the line 23Λ to the address register 24 (whereby the first separating bit arriving at the end of this address register, which is designed as a shift register, is lost). After the tenth clock pulse, a complete address is available and, via a signal on line 23, activates the decoder, which then converts the nine address bits into a 1-out-of-256 code. The nine address bits thus contain a redundancy. It is possible to introduce this redundancy in such a way that a 1-out-of-512 code is formed while an error signal is stored in the "invalid" word positions (for example a word consisting of all zeros or a "1" in an occupied additional bit position per word). The word addressed in this way is read and, with the activation of the sense amplifier arrangement 27, stored in the data register 28 via the line 23. An error detector arrangement is not specified, but when the aforementioned error signal is detected it can forward an activation signal to the clock pulse generator 22, which then delays the separation between two successive operating cycles by one channel symbol now always emits eight equally spaced clock pulses per operating cycle, whereby the originally at input 2 in FIG. 1 is sequentially newly formed at the output terminal 29. The terminal 29 can be connected to a data processing arrangement (not shown), for example a computer. The register 28 can also be constructed in such a way that it outputs the information in parallel, and can also have a buffer function for storing a number of data words.

It should also be noted that the medium, for example can be a disk storage.

In this case it is further possible that the source arrangement 1 in FIG. 1 and the data usage arrangement mentioned here are the same. A number of elements from FIGS. 1 and 3 together to be used. The clock pulse extractor 21, the clock generator 22 and the data utilization arrangement can still be connected to one another by a synchronization connection, not shown.

In addition 5 sheets of drawings

Claims (13)

Patent claims: 1. Arrangement for transmitting binary data elements over a medium or for storing such data elements in a medium by means of a two-valued state variable of this medium, the data elements being received in a sequence of bit cells at an input of a bait and, from this, successive groups (data words) of m data elements can be shaped in order to use the bait to form a respective group of η code elements (code word) corresponding to a data word in a sequence of channel symbols, the value of π being greater than the value of m and where in a code word the Number of successive code elements, which does not mean a state transition, is always smaller than an upper limit lower than the value of n, as well as to recover the information of the binary data elements from the state variable. characterized in that the output of the bait is connected to an input of an encryptor for the respective separation of successive code words by a number of j code elements, at least one of which means a state transition, and that an output of the encryptor is connected to an input of the medium via a modulator which controls a modulation of the state variable that does not return to zero, and that a decoder is connected to the demodulator corresponding to the modulator for the purpose of eliminating the j additional code elements per code word and a decoder is connected to the decoder which returns the. releases its data elements 2. Arrangement according to claim 1, characterized in that the modulator is an NRZ modulator 3. Arrangement according to claim 1, characterized in that the modulator is an NRZ-I modulator is 4. Arrangement according to claim 1, 2 or 3, characterized in that the value von./ = 1 5. Arrangement according to one of claims 1 to 4, characterized in that m = 8, that / 7 = 9 and that the maximum number of closed code elements occurring within a code word without at least one would mean a transition in the state variable mentioned, equal to two is. 6. Arrangement according to claim 5, characterized in that the weights of the corresponding Elements of a Koc word like the numbers 1,2,4,7, 13,24,44,8! and 149 cautious. 7. Arrangement according to one of the preceding claims, characterized in that in the A filter is connected upstream of the demodulator to recover the data elements. 8. Arrangement according to claim 7, characterized in that when receiving an NRZ-modulated Signals the filter is a duobinary filter. 9. Arrangement according to claim 7, characterized in that when receiving an NRZ-I-modulated If the filter signals a series connection of a duobinary filter and a channel symbol contains retarding ring-coupled precoder. 10. Arrangement according to claim 8 or 9, characterized in that an output of the duobinary Filter contains a full wave rectifying element. 11. Arrangement according to one of claims 7 to 10, characterized in that the decoder is stored in a read-only memory and of code words contains addressable data word alphabet 12. Arrangement according to one of claims 1 to 11, characterized in that the bait is a stored in a read-only memory and of data words addressable code word alphabet entM't 13. Arrangement for transmitting binary data elements over a medium or for storing such data elements in a medium by means of a two-valued state variable of this medium, wherein the data elements were received in a sequence of bit cells at an input of a bait and therefrom in each case successive groups (data words) of / n data elements can be shaped in order to use the bait to form a respective group of π code elements (code word) corresponding to a data word in a sequence of channel symbols, the value of π being greater than the value of m , characterized in that m = 2, that π = 3, that in a code word a predetermined code element with the same order number in all code words always means a transition in the mentioned state variable and as such no information. ' ^: on contains that the two other code elements are assigned in the same order to the two data elements of the data word and contain the information bit by bit, and that an output of the bait is connected to an input of the medium via a modulator of the one mentioned modulation that does not return to zero State variable controls