GB1575728A - Coding and decoding digital information - Google Patents

Description

(54) CODING AND DECODING DIGITAL INFORMATION (71) We, N.V. PHILIPS' GLOEILAMPENFABRIEKEN, a limited liability Company, organised and established under the laws of the Kingdom of the Netherlands, of Emmasingel 29, Eindhoven, the Netherlands, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to an arrangement of a kind for introducing the information of binary information bits into a medium through a bivalent state of this medium, comprising a coding device having input means for receiving said information bits in a non-restricted successsion of bit periods, said coding device having means for forming as information words successive groups of m information bits from the information bits received, and for forming from each group, as a code word, a group of n code elements corresponding to an information word, in a succession of channel intervals for subsequent transfer to the output of the coding device, the value of n being larger than the value of m, and the number of successive code elements which do not imply a state transition within a code word always being smaller than an upper limit below the value of n. The medium may be a magnetisable tape which can be driven past a read and/ or write head. The information bits may have the value "0" or "1" without restriction, so that no further restrictions are imposed as regards the coding by the information source. The information bits need merely have the correct length and must occur synchronously. The information bits each time appear in bit periods which are time intervals of fixed length in which an information bit occurs or not. In the latter case, the bit period is empty. No further restrictions are imposed as regards the appearance of the information bits; the appearance may consist of a signal level, the absence of presence of a transition, or a waveform having a given direction, etc. in accordance with known techniques.

The code elements occur in a succession of channel intervals. A channel interval is a time interval of fixed length in which a state transition occurs or not. It is desirable to incorporate clock pulse information in the succession of channel intervals; in that case it is not necessary to use a separate track or channel which must also be written or read or transmitted. The detection accuracy during reading or receiving of the code elements is determined to a substantial degree by the accuracy of the clock incorporated in the signal. Therefore, one of the objects of the invention is to introduce as many state transitions as possible per fixed number of channel intervals, in order to enable an appropriate device to restore a reliable clock signal during reading/receiving. To this end, it is known to impose an upper limit as regards the number of successive transition-less channel intervals. A suitable code is disclosed in the article by T. Tamura et al, A coding method in digital magnetic recording, IEEE Transactions on magnetics, September 1972, pages 612-613. According to the MNRZ1 coding described therein, four information bits are converted into five code bits, successive occurrence of at the most two transition-less code elements being allowed. At the beginning and at the end of a code word, at the most one transition-less code element may occur, and in that case there are seventeen feasible code words. This is sufficient to translate information words of four bits, because there are only sixteen different possibilities for this purpose. The one additional code word can then be reserved for a special purpose. Thus. five code bits are required for the translation of four information bits; this 4: 5 ratio is defined as the efficiency, which in this case amounts to 80%. The code words can be linked without restriction, because a succession of more than two transition-less code elements will never occur. Obviously, this is advantageous because only simple control is then required. On the other hand. there is a drawback in that in the receive/read device it cannot readily be detected which position is to be assigned the separation between two successive words. Once this choice is incorrect, it can be corrected only after detection of a beginning or end of a code word having two successive transition-less code elements and if, moreover, the correct position of the separation has then been found. This may be rather time-consuming, and constitutes a major drawback of the known method.

Furthermore, the use of such a code gives rise to problems if a high bit density is used; in that case interference occurs between adjoining channel intervals. Suitable filters are then required for the reception or reading of the information in order to counteract this interference. This necessity occurs notably if reading is effected in a differentiating manner, as is the case for information storage in a magnetisable medium. It has been found that the restriction as described above (never more than two successive transition-less code elements) is then affected. This gives rise to the risk of serious errors.

The invention has for its object to provide a coding device in which filters of this kind can be used without the said code restriction being affected. The invention has for an object to provide for information transmission with optimum high transmission density, and with a favourable bandwidth of the required frequency spectrum. Another of the objects in accordance with the invention is to aim at avoiding the propagation of storage errors from code word to code word. Storage errors of this kind are always possible, for example, under the influence of external disturbances. The invention has also for an object to provide a simple coding and decoding device as a result of the use of comparatively short code words. The invention has for a further object to provide high-efficiency storage. According to the invention an arrangement of the kind referred to is characterised in that the output of the coding device is connected to an input of a keying device which is adapted for separating successive code words each time by a number ofj code elements, at least one of the saidj code elements implying a transition in the said state. an output of said keying device being connected, via a modulator, to an input of the medium, said modulator controlling a non-return-to-zero modulation offers a favourable storage density. An NRZ or an NRZ - 1 modulation may be used.

Preferably. if j = I. and if m = 8 and n = 9, the largest number of consecutively occurring code elements within a code word without at least one of these elements implying a transition of the said state is equal to two. Thus. the same efficiency (80g) is obtained as in the arrangement described previously. whilst the said attractive aspects of the invention are maintained.

Preferably. the weights of the relevant elements of a code word relate as the numbers 1. 2.

4. 7. 13.24.44.81. 149. This enables a harmonic and simply programmable translation of the information words.

The invention also relates to an arrangement for receiving or reading information bits.

comprising an input for accessing the medium in an arrangement of the kind referred to and an output for generating thereon the restored information bits for further use, said input being connected to an input of a demodulator which comprises filtering means and which is associated with the said modulator. an unkeying device being connected to said demodulator for extracting saidj addition code elements per code word. a decoding device being connected to the said output.

When the NRZ modulated signal is received. the filtering means preferably comprise a duo-binary filter; in the case of an NRZ -1 signal. said filtering means may further comprise a precoder which is coupled end-round and which introduces a delay of one channel interval. A simple arrangement is thus sufficicnt. The addition of a full-wave rectifying member is advantageous in both cases.

Coding and decoding are preferably effected using a random acccss read-only memory.

The invention will be described by way of example in detail with reference to the accompanying drawings. in which: Figure 1 shows an arrangement for the storage or transmission of information bits in accordance with the invention. Figure 2 shows a sct of code words. Figure 3 shows an arrangement for reading or receiving information bits in accordance with the invention. Figure 4 shows a number of relevant quantitics for different lengths of information words and code words. Figure 5 shows an example of a bucket brigade for use in carrying out the invention. Figure 6 shows an embodiment of a filter for use in an arrangement in accordance with the invention. Figure 7 shows s an example of filter coefficients of such a filter.

Figure 8 shows an example of a response curve of such a filter. Figure 9 shows an example of time-dependent signals when use is made of such a filter.

Figure 1 shows an arrangement for storing or transmitting information bits in accordance with the invention. comprising a source device 1. an input signal terminal 2. an address register 3. a decoder 4. a clock 5. clock pulse lines 6. 7. 11. a read-only memory 8. a read amplifier device 9. an information shift register 10, a complementer 12. a flipflop 13. a precoder 14 and an information terminal 15.

The clock 5 supplies clock pulses at fixed intervals in synchronism with the presentation of information bits by the source device 1. Signals on the line 6 control this synchronisation, the mutual relationship as master and slave of the units 1 and 5 not being important in this respect. This is indicated by the two-way arrow on the line 6. The information bits presented are applied in series of in parallel, via, the (possibly multiple) connection/input signal terminal 2, to the address register 3, up to a total of m = 8 information bits per operation cycle of the arrangement shown in Figure 1. Under the control of a clock pulse on the line 7, the decoder 4 is activated once per said operation cycle, so that the eight information bits in the address register 3 are converted into a 1-out-of-256 code whereby the read-only memory 8 is then addressed. The output of this read-only memory 8 supplies nine code bits which are stored, via the read amplifier 9 which is co-activated by a signal on the line 7, in the information register 10. The line 7 may be of a multiple construction for separate actuation in time of the elements 4, 9 and 13 (see hereinafter). The read-only memory 8 constitutes, together with the elements 3 4, 9 10 connected thereto, the encoder for converting the eight bit information words into nine-bit code words. Thus, the read-only memory 8 has a capacity of at least 9 x 256 = 2354 bits. This may be realised in known manner, for example, in the form of nine memory chips of 256 bits each. On the other hand, the memory 8 may also comprise further word positions or further bit positions per word which are used for specific other purposes or not. Via the line 11, the clock 5 supplies uniformly spaced clock pulses to a total of ten pulses per operation cycle of the arrangement shown in Figure 1. As a result, the information register 10 is operated as a shift register, in series with the flipflop 13. The shift pulses, obviously, do not coincide in an interfering manner with the read pulses, so that when a shift pulse appears, a non-disturbed code element is each time present per cell of units 10/13. When the first shift pulse associated with a given code word appears on the lines 10,1, the flipflop 13 contains a logic "1", for example, under the control of a signal then occurring on the branch of the line 7 which is denoted by a broken line. The nine-bit code words from the read-only memory 8 may be composed so that never more than two code elements "1" can directly succeed each other; a relevant conversion algorithm will be given hereinafter. Subsequcntly. the code bits of the information register 10 are complemented by the complementer 12. so that "zeros" are converted into "ones" and vice versa. It is assumed that a code element "1" stored in the read-only memory 8 ultimately implies a transition-less element in the medium; a code element "0", however, ultimately implies an element with a transition-less element in the medium;. A transistion of this kind then occurs, for example, at the beginning of such an element, the element itself implying one of the said two values of the state. On the other hand, the code words may also be composed so that never more than two code elements "0" can directly succeed each other; in that case the complementer 12 can be dispensed with. The output signals of the complementer 12 are then applied to the flip flip 13 for further processing. The elements stored in the read-only memory 8 obviously maintain a stationary value which can be detected, for example, as a voltage level on the output thereof.

The code words thus formed, including the addition a l " separation bits, are passed through the precoder 14 which applies the code elements to the output terminal 15 in accordance with a bit-wise code. without return to a zero level. There are two possibilities in this respect: a) The NRZ-code. where the first value of the state of the medium implies a "0" and the second value implies a "1". A transition in the state of the medium thus is a 0-1 or a 1-0 change over the information.

b) The NRZ- l code. where a transition between the two values of the state of the medium implies a logic " 1". and the absence of such a transition implies a logic "0". The precoder may comprise a feedback loop which corresponds to the elements 19, 20 of Figure 3 to be described hereinafter. If the delay time amounts to one bit period an NRZ-1 code occurs. If the delay time (element 19) amounts to two bit periods. an NRZ code arises. On the output side of the precoder 14 there may be provided a transmission amplifier or, in the case of a magnetisable medium. a write coil/write amplifier. but these elements are not separately shown.

FThe formation of code words of other lengths can be realised in the same manner as described above. Instead of the formation by means of a read-only memory. two other possibilities exist. First of all. the code bits can be formed exclusively by means of combinatory logic. On the one hand. this is very fast. because the logic depth of a relevant network may remain limited to. for example. 3. to 5 gate delay times. On the other hand, a very large number of gates is then required. with a very irrcgular structure, so that the design (for example. by a computer) of a suitable integrated circuit involves serious problems and the testing for possible errors is also difficult. Furthermore. the code words (see hereinafter) can also be arithmetically formed by a number of sequential subtraction operations. This results on the one hand in realisation by means of a simple circuit. On the other hand, the sequential generating of the code bits results in slow operation. The latter will generally involve insurmountable problems.

Figure 2 shows a survey of the possible code words of nine elements, at the most two code elements having a value "0" occurring in direct succession within a code word. Most elements "1" have been omitted for the sake of simplicity. The first 127 of the code words shown are non-symmetrical, whilst the codewords corresponding thereto as a mirror image are not included. The last 20 code words are symmetrical, so that there are 2 x 127 + 20 = 274 possibilities. This number is larger than 256 (28), so that any information word of eight bits can be correctly translated to such a 9-bit code word. An algorithm for the code conversion (i.e. the choice of the combination code word / information word) can be found by assigning the weights 1, 2, 4, 7, 13, 24, 44, 81 and 149 to the successive code element positions. These numbers, forming part of an infinite series [bj]. have the property that bi + b(i + 1) + b (i + 2) = b(i + 3). The representation of the binary number 201(11001001) is calculated as follows; 201 - 149 = 52; 52 - 44 = 8; 8 - 7 = 1, the representation as code word then being: 101001001. It can be demonstrated that more than two code elements "1" can never directly succeed each other. This because, if this were so, bi = b (i + 1) = b (i + 2) = 1,so that the value of b (i + 3) in accordance with the given algorithm would automatically have been 1.

The code thus enables representation of the "values" O to (149 + 81 +24 + 13 + 4 + 2) = 273 before more than two successive "1" appear. These codes are shown indeed in Figure 2.

In principle a very large number of translations of eight-bit information words to nine-bit code words are possible.

As has already been stated, the code words are complemented to ten-bit code by means of an additional code element. The additional code element always implies a state transition and hence the variation in the distance between successive transition instants is limited. Notably the bandwidth of the signal does not extend to zero frequency, so that inter alia systematic level shifts (bias distortions) have little or no effect.

Thus, always eight information bits are translated to one nine-bit code word, complemented to ten code elements by one element. An efficiency of 80% is thus obtained. This has been found to be an attractive percentage in practice. On the other hand, the lengths of the information words and code words are limited, so that, for example, the capacity of the read-only memory 8 of Figure 1 need not be very high. The code words are each time separated from each other by an additional code element. so that the risk of propagation of errors between the various information words is low. It is alternatively possible to insert two or more additional code elements between each pair of code words, for example, by doubling the flipflop 13. It is furthermore possible to use other translations. for example, 7 information bits to 8 code bits. The efficiency is then limited to 7 : (8 + 1) = approximately 78%. On the other hand. the translation of. for example. 10 information bits to 11 code bits is not possible.

because in that case there are only 927 code words. The translation 10/12 offers a lower efficiency of 10 (12 + 1) 77%,. In this respect. Figure 4 illustrates the relationship between n : the number of code bits. p : the number of different code words which can be formed therefrom with at the most two directly successive code elements "0", q: the highest power of 2 which is at the most equal top, m = In q. andes = rn : (n + 1); these factors are shown for some advantageous combinations. It has been found that tlie translation for m = 8 has a favourable yield which is slighly surpassed only for long code words; for n = 17. for example. a read-only memory of 6 x 10-bits is required for an efficiency improvement of 4 %.

ln some cases this will be justified. On the other hand, a 2/2 translation may in some cases be very attractive. because then only a very simple arrangement is required. Notably the read-only memory 8 of Figure 1 can be dispensed with, whilst the terminal 2 is connected directly to the shift register 10. In this case an efficiency of 2/3 is still achieved. whilst the other attractive properties of the invention are maintained : limited bandwidth and prevention of error propagation.

Figure 3 shows an arrangement for reading or receiving information bits in accordance with the invention. The arrangement comprises an input terminal 16. a duo-binary filter 17, a modulo-2 device 18. a delay element 19, a modulo-2 adding element 20, a clock pulse extractor 21. a clock pulse generator 22. a clock pulse line arrangemcnt 23, 23A. an address register 24. a decoder 25, an information register 28 and an information output terminal 29.

Between the terminals 15 (Figure 1) and 16 the actual information carrying medium is situated. for example. embodied in a magnetic layer, on one side of which a write head and associated write amplifier are arranged. whilst on the read side or rcceive side a read head with read amplifier is arranged. A read head of this kind oftcn has a differentiating operation, so that a transition between the two values of the state of the medium results in a response which can be represented for example, approximately as f(t) = fo: (1 + t2/to2), in which + is the time. to is a characteristic time length which is determined by the cooperating effects of the propcrties of the medium. the transport speed of the information relative to the read/receive point. and the read means such as the said head and the amplifier ; fo is proportionality constant. This wavcform arrives on the input terminal 16. If the magnetic transitions (can) occur at a rate: l /T = I / k.to (wherein T is their minimum separation in the time), the total signal received on the terminal 16 can be written as a sum of a number of terms: +N s(t) = s an.f(t-nT).

n=-N Therein an = + 1 or = 0, depending on the occurrence of a state transition in one or the other direction at the relevant point, or on the absence thereof, respectively. The transitions can occur at integer multiples of the time interval T, as from the point t = 0. Summing need be effected only over a limited number of transition pulses, on account of the disguising effect of the noise always present. The said quantity k provides the spacing of the individual transitions in the relation to their effect which is widened in the time. For transport or storage at low density, the value k is high, for example, larger than 3. In the case of high density, the value of k is lower, for example, approximately equal to 1, so that between successive transitions interference phenomena arise. Symbol interference may then also become detrimental. It has been found that the effect of such interference can be limited by using a filter 17. An attractive choice is formed by a filter having a overall response to a said transition in the state as follows: 4 cos (7r t/T) x(t) = 7r 1-4t'/T Thus, this represents the time-dependent signal on the output of the filter. The function is normalised by a preliminary factor 4/"'. Figure 8 shows the response curve when such a filter is used. t/T is horizontally plotted, whilst the value of x(t) is vertically plotted. For t/T = 0, x(t) = 4/ir; fort/T = 1/2, x(t) = l;fort/T = 1 :x(t) = 4/3ir, fort/T = 3/2,5/2 always x(t) = 0 etc., while the amplitude of x(t) at t/T = 2,3 . . . rapidly decrease. The response curve shown is given by way of example. but other responses may also be advantageous. The filter may be embodied in a transversal filter. Generally, transversal filters are well-known.

An advantageous embodiment is formed by a bucket brigade shift register as described, for example, in the article by F.L.J. Sangster. "The bucket-brigade delay line", Philips Technical Review 31 (1970), No. 4, p. 51 ff. In this respect. Figure 5 shows an embodiment of such a bucket brigade as a transversal filter. The circuit comprises five transistors 30-34 and five capacitors 35-39. each of which comprises one first capacitor plate and one or two second capacitor plates. The control lines 45 and 47 are alternately activated, so that the transistors connected thereto become conductive and, moreover, the potential of the capacitor plates connected thereto is changed. The charges of the capacitors of odd and even sequence number are then shifted by one position. The elements 30 and 35 form an input buffer stage.

The elements 31, 32, 36, 37 form the first shift register stage. The capacitors 36 and 37 each comprise. besides the second capacitor plates connected to the control lines 45, 47, a further second capacitor plate 41 and 42. respectively. which are connected to the first and the second summing line (48, 46). respectively. The relative surface area of the plate 41 is smaller than that of the plate 42, so that a negative weighting coefficient (defined as such) arises in view of the connection to the summing lines. The elements 33, 34, 38, 39 form the second shift register stage. The relative surface of the plate 43 is larger than that of the plate 44, so that a positive weighting coefficient arises in view of the identical connection pattern of the two stages shown, Further stages are not shown for the sake of simplicity.

Figure 6 is a general survey of a transversal filter. This filter comprises a signal input 49, seven shift register stages 50-56, a signal output 57, seven weighting elements 58-64, an adding amplifier 65, and a signal output 66. The time-dependent signals to be transformed are received on the input. arc samplcd and are shifted. under the control of a clock pulse system not shown. until they appear for further use, if desired. on the output 57 after, in this case seven. periods of the double clock pulse. Each stage comprises a symbolically denoted weighting element 58-64. an embodiment of which is shown in Figure 5 (capacitor pairs 36i 37. 38/ 39). The output signals of the weighting elements are summed instantaneously or in a clocked manner in the adding amplifier 65. the positive/ negative weighting factors being maintained. The filtered signal thus formed appears on the output 66 for further use. In the case of an odd number of filter stages, the weighting factors are symmetrical relative to the central stage of the shift register. Figure 7 shows a number of weighting factors for a shift register comprising 19 stages. Proceeding from the centre. weighting factors gradually become smaller. be it that periodically changes of sign occur. The number of stages is determined by considerations as regards accuracy of the transformation on the one hand and simplicity of construction and the impossibility of improving the accuracy beyond the level of the interference always present on the other hand. The shape of the signal originating from the receive head is improved by the duo-binary or Nyquist ll filter thus described. The invention can in principle also be used with other types of filter. other types of response curves or other numbers of shift register stages. The element 17 of Figure 3 is thus further elaborated.

For further clarification, Figure 9 shows a number of time-dependent signals occurring when use is made of a filter as described. The second line shows the variation of the values of the state, by way of example. The first line shows the associated meaning of the code elements in the case of an NRZ-1 code. The arrangement of the logic symbols is chosen for optimum clarity: "ones" are always shown directly above the associated state transition. The third line shows the meaning of the code elements assigned to the change of state in the case of an NRZ-code. The fourth line shows the signal obtained on the output of the transversal filter shown in Figure 5, the curves representing the response to the individual transitions. At the area of the vertical broken lines, the response (being the algebraic sum of the total response) is sampled. This response may have the three values + 1,0, -1 shown on the fifth line. Each time only two feasible transistions need be observed, i.e. those which are situated directly before (t/2T) and directly behind the instant of interrogation, because the response at the instants 3/2T, 5/2T etc., was always identically equal to zero. Small, incidental time-shifts have been ignored in the foregoing; the same is applicable to a fixed time-shift. The latter means only a shift of the time axis. The modulo-2 device 18 of Figure 3 now operates as a full-wave rectifier whereby the signal values stated on the sixth line in Figure 9 are produced.

Full-wave rectifiers are known per se.

The output signal of the unit 18 is applied to a modulo-2- adding element 20, which further receives the output signal of the same element 20 after delay over an interval of one channel symbol. The delay time is introduced by the delay element 19. The element 20 then supplies the signal shown on the seventh line of Figure 9: each arriving "1" produces a trans

Claims (13)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   curves or other numbers of shift register stages. The element 17 of Figure 3 is thus further elaborated.

   For further clarification, Figure 9 shows a number of time-dependent signals occurring when use is made of a filter as described. The second line shows the variation of the values of the state, by way of example. The first line shows the associated meaning of the code elements in the case of an NRZ-1 code. The arrangement of the logic symbols is chosen for optimum clarity: "ones" are always shown directly above the associated state transition. The third line shows the meaning of the code elements assigned to the change of state in the case of an NRZ-code. The fourth line shows the signal obtained on the output of the transversal filter shown in Figure 5, the curves representing the response to the individual transitions. At the area of the vertical broken lines, the response (being the algebraic sum of the total response) is sampled. This response may have the three values + 1,0, -1 shown on the fifth line. Each time only two feasible transistions need be observed, i.e. those which are situated directly before (t/2T) and directly behind the instant of interrogation, because the response at the instants 3/2T, 5/2T etc., was always identically equal to zero. Small, incidental time-shifts have been ignored in the foregoing; the same is applicable to a fixed time-shift. The latter means only a shift of the time axis. The modulo-2 device 18 of Figure 3 now operates as a full-wave rectifier whereby the signal values stated on the sixth line in Figure 9 are produced.

   Full-wave rectifiers are known per se.

   The output signal of the unit 18 is applied to a modulo-2- adding element 20, which further receives the output signal of the same element 20 after delay over an interval of one channel symbol. The delay time is introduced by the delay element 19. The element 20 then supplies the signal shown on the seventh line of Figure 9: each arriving "1" produces a transition in the output signal. Comparison reveals that the first line of Figure 9 has thus been reconstituted.

   The following is a further possibility. The information of the first line of Figure 9 is applied to a modulo-2- adding element, which also receives its own output signal after delay over one channel symbol. This results in the third line of Figure 9; this signal is transmitted or stored in coded form as an NRZ-code. In this case the information of the first line of Figure 9 is directly recovered on the output of the unit 18 and the units 19/20 can be dispensed with.

   The output signal of the unit 20 is applied to a clock extractor 21 which may comprise, for example. a resonant circuit which can be adjusted to the repetition frequency of the channel symbols by the series of signal pulses received by the circuit itself. During an operation cycle of the device shown in Figure 3. each time ten channel intervals occur. An equal number of clock pulses are than applied by the clock pulse generator 22, via the line 23A, to the address register 24 (where the first separation bit appearing on the output of this address register.

   constructed as a shift register. is lost). After the arrival of the tenth clock pulse, a complete address is present and a signal on the line 23 activates the decoder, with the result that the latter converts the nine address bits into a l-out-of-256 code. The nine address bits thus contain a redundance. It is possible to introduce this redundance in order to form a 1out-of-512 code. whilst an error signal is then stored in the "invalid" word positions (for example. a word comprising exclusively zeroes or a "1" in a reserved additional bit position per word). The word thus addressed is read and stored, the read amplifier 27 also being activated. in the information register 28 via the line 23. An error detection device is not shown. but in the case of detection of the said error signal. an activation signal can be applied to the clock pulse generator 22. with the result that this generator delays the separation between two successive operation cycles by one channel symbol. After a brief period of time.

   a correct word position of the read-only memory 26 is thus addressed. The clock pulse generator then continuously supplies eight uniformly spaced clock pulses per operation cycle.

   with the result that the information originally applied to the input 2 of Figure 1 is sequentially recovered on the output terminal 29. The terminal 29 may be connected to a user device not shown. for example. a computer. The register 28 may also be constructed to output the information in parallel form, and it may also have a buffer function for storing a number of information words.

   It is to be noted that the medium may be, for example. a disk memory. In that case it is also possible for the source device l of Figure l and the user device described in this context to be the same. A number of elements of the Figurcs 1 and 3 may then be used in common. The clock extractor 21. the clock 22 and the user device may also be interconnected by a synchronisation connection not shown.

   WHAT WE CLAIM IS: 1. An arrangement for introducing the information of binary information bits into a medium through a bivalent state of this medium, comprising a coding device having input means for receiving said information bits in a non-restricted succession of bit periods said coding device having means for forming as information words successive groups of m information bits from the information bits received. and for forming from each group. as a code word. a group of n code elements corresponding to an information word, in a succession

   of channel intervals for subsequent transfer to the output of the coding device, the value of n being larger than the value of m, and the number of successive code elements which do not imply a state transition within a code word always being smaller than an upper limit below the value of n, said arrangement being characterised by comprising a keying device having an input connected to the output of the coding device and being adapted for separating successive code words each time by a number ofj code elements, at least one of the saidj code elements implying a transition in the said state, an output of the said keying device being connected, via a modulator, to an input of the medium, said modulator controlling a non-return-to-zero modulation of said state.
2. 2. An arrangement as claimed in claim 1, characterized in that the modulator is an NRZ-modulator.
3. 3. An arrangement as claimed in Claim 1, characterized in that the modulator is an NRZ-1 modulator.
4. 4. An arrangement as claimed in Claim 1, Claim 2 or Claim 3, characterized in that the value ofj = 1. 1.
5. 5. An arrangement as claimed in any one of Claims 1 to 4, characterized in that m = 8 and n = 9, the largest number of code elements successively appearing within a code word without at least one of these elements implying a transition in the said state being equal to two.
6. 6. An arrangement as claimed in Claim 5, characterized in that the weights of the successive element positions of a code word relate as the numbers 1, 2, 4, 7, 13, 24, 44, 81, 149.
7. 7. An arrangement for receiving or reading information bits from a medium in an arrangement as claimed in any one of Claims 1 to 6, comprising an input for accessing the medium and an output for generating thereon the restored information bits for further use, said input being connected to an input of a demodulator which comprises filtering means and which is associated with the said modulator, an unkeying device being connected to said demodulator for extracting saidj additional code elements per code word, a decoding device being connected to said output.
8. 8. An arrangement as claimed in Claim 7, characterized in that in the case of reception of an NRZ-modulated signal, the said filtering means comprise a duo-binary filter.
9. 9. An arrangement as claimed in Claim 7, characterized in that in the case of reception of an NRZ-1 modulated signal. said filtering means comprises a series connection of a duobinary filter and a precoder which is couplcd end-around and which introduces a delay of one channel interval.
10. 10. An arrangement as claimed in Claim 8 or Claim 9. characterized in that an output of said duo-binary filter comprises a full-wave rectificr element.
11. l l. An arrangement as claimed in any one of Claims 7 to 10. characterized in that said decoding device contains an alphabet of information words which is stored in a read-only memory and which can be addressed by code words.
12. 12. An arrangement as claimed in any one of Claims l to Il.characterized in that said coding device contains a code word alphabet which is stored in a read-only memory and which can be addressed by information words.
13. 13. An arrangement for introducing information into a medium and an arrangement for extracting information from said medium. substantially as hereinbefore described with reference to the accompanying drawings.