JPH08221904A - Encoding method of binary data and sampling device for multivalued data - Google Patents

Abstract

PURPOSE: To provide an encoding method of original binary data for facilitating the sampling of multi-valued data and a multi-valued data sampling device capable of stably sampling them. CONSTITUTION: Output data are selected so that at least one set of a combination '11' or '00' is included in '8-10' conversion and by equalizing a number of sets '11' to a number of sets '00' for every prescribed amount, a signal is made to become DC-free when data are transferred through a transfer system corresponding to a PR(1, 1) system. On the assumption of the encoding, a multi- valued data sampling device is provided with automatic setting means 251-256 for automatically setting the slice levels SL1, SL2 of plural level comparators 241, 242 and automatic compensating means 261-264 for automatically compensating the slice levels of the respective level comparators when asymmetry arises in the input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary data encoding method and a multivalued data extracting device suitable for, for example, a pit edge recording system.

[0002]

2. Description of the Related Art Conventionally, in a high density and large capacity medium such as a write once type or a rewritable magneto-optical type optical disc, for example, a digital video signal, A large amount of data is recorded and reproduced in real time.

In this case, the partial response system, which positively utilizes intersymbol interference, is effective for high-speed transmission of digital information. Particularly, in the PR (1,1) format of the partial response class 1 (so-called duobinary code), the power spectrum is 1 / x on the frequency axis as compared with the unipolar code.
Compressed to 2.

First, referring to FIG. 4 to FIG.
A data transmission system based on the (1,1) method will be described.

In FIG. 4, reference numeral 10 denotes a data transmission system. For example, 8-bit input data is supplied to the block coding circuit 11 to generate data conforming to a predetermined format.

The output data of the coding circuit 11 is supplied to the precoding circuit 12 and is subjected to predetermined partial response precoding according to the conversion rule based on the inverse characteristic of the transmission line 13. In the PR (1,1) method, the data at the present time has a response in which only the data one clock before interferes, and the precoding circuit 12 includes an adder 12a and a 1-bit delay feedback element 12d. .

From the coding circuit 11, for example, "1"
Binary original data such as "00111" is delayed by 1 bit and fed back to the adder 12a.
Three-valued intermediate data such as "2" is generated.

As can be easily understood from the above, PR
In the (1,1) method, binary original data “00”
From the three-valued intermediate data "0" is generated
Original value data “11” to ternary intermediate data “2”
Is generated.

The ternary data output from the precoding circuit 12 is supplied to the transmission line 13. In this case, the transmission line 13 is composed of an optical disk and an optical head for recording and reproduction (neither of which is shown), and its spatial frequency characteristic (Modu
relation transfer function) is a PR with a cosine characteristic
It is compatible with the (1,1) method. The reproduction RF signal from which the intersymbol interference is allowed from the transmission line 13 is commonly supplied to the non-inverting input terminal of one level comparator 14a of the extraction circuit 14 and the inverting input terminal of the other level comparator 14b. To be done.

The inverting input terminal of one level comparator 14a and the non-inverting input terminal of the other level comparator 14b are
Predetermined reference voltage (slice level) SL1, S respectively
L2 is supplied to the slice levels SL1, S
The output of the transmission line 13 is compared with L2, and the level is judged as a ternary signal.

The outputs of both level comparators 14a and 14b are
The binary original data supplied to the decoding circuit 15 through the OR circuit 14c is reproduced by the Viterbi decoding method or the like, for example, according to a predetermined format.

[0012]

When recording on an optical disk, data is recorded by heating the recording medium using the energy of a laser light beam to change its optical or magneto-optical properties. I am trying.

The intensity (power level) of the laser light is controlled to a constant value by so-called APC and is intermittently controlled according to the data to be recorded.

In the pit edge recording system in which the inversion interval of the recording signal and the edge of the pit are made to correspond to each other, ideally,
As shown in FIG. 5B, the pits are formed in the track direction of the optical disc so that the leading edge and the trailing edge of the pits are at predetermined positions.

Then, in this state, as shown in FIG. 6B, a reproduction RF signal having a vertically symmetrical eye pattern is supplied from the transmission line 13 to the extraction circuit 14, and 3 based on the predetermined slice levels SL1 and SL2. Extraction of intermediate value data is performed normally.

However, in reality, as shown in FIGS. 5A and 5C, the front and rear edges of the pit are affected by the ambient temperature, variations in the sensitivity of the recording layer, variations in the power level of the laser beam, and the like. The edges shift from the predetermined positions to the front and the rear, respectively, and pits are formed in a so-called asymmetry state.

When such asymmetry occurs, the eye pattern of the reproduction RF signal supplied to the extracting circuit 14 becomes vertically asymmetric as shown in FIGS. 6A and 6C. Along with this, the optimum values of the slice levels SL1 and SL2, which are the reference for extracting the intermediate data, fluctuate, and there arises a problem that it becomes difficult to extract the ternary intermediate data.

Further, even when the level of the reproduced signal fluctuates due to variations in reflectance of individual optical disks,
There was a problem that the optimum values of the slice levels SL1 and SL2 fluctuate and the extraction stability is impaired.

In view of the above point, an object of the present invention is to provide a transmission line corresponding to a predetermined partial response system,
An object of the present invention is to provide a binary original data encoding method for facilitating extraction of multi-valued data and a multi-valued data extraction device capable of stable extraction.

[0020]

In order to solve the above-mentioned problems, the binary data encoding method according to the present invention transmits m-bit input data to an n-bit input data in order to transmit the data through a transmission system of the edge recording system. In the binary data encoding method for converting (n> m) bits of output data, the output data is selected so as to include at least one combination in which two consecutive bits have the same value. , The values of two consecutive bits are the same,
In addition, the number of combinations having different values is made equal for each predetermined amount of output data.

Further, the multi-valued data extracting device according to the present invention is input to a plurality of level comparators 241 and 242 in which predetermined reference voltages SL1 and SL2 are set, respectively, in correspondence with the reference numerals of the embodiments described later. In a multi-valued data extraction device to which signals are commonly supplied, automatic setting means 251 to 256 for automatically setting reference voltages corresponding to a plurality of level comparators are provided, and when asymmetry occurs in an input signal. In addition, automatic correction means 261 to 264 for automatically correcting the reference voltage are provided.

[0022]

According to the binary data encoding method of the present invention having such a configuration, the signal becomes DC-free (there is no DC offset component) after passing through the transmission line corresponding to the predetermined partial response system. It becomes easy to judge the level as a multi-valued signal, that is, to extract data.

Further, according to the multi-valued data extracting device of the present invention having the above-described structure, the DC-free data is encoded by the method of the present invention as described above and is transmitted through the transmission line corresponding to the predetermined partial response system. Is supplied, the automatic setting means 251-256 causes
While the reference voltage of the level comparator is automatically set,
When asymmetry occurs in the input signal, the automatic correction means 2
61 to 264, the reference voltage is automatically corrected,
Multivalued data can be extracted easily and stably.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A binary data encoding method according to the present invention and a multivalued data extracting device according to the present invention will be described below with reference to FIGS.
An embodiment applied to a data transmission system based on the PR (1,1) system will be described.

[Arrangement of Apparatus] FIG. 1 shows the structure of the essential part of the first embodiment of the present invention, and FIG. 2 shows the structure of the essential part of the second embodiment of the present invention.

In FIG. 1, reference numeral 210 indicates a block coding circuit as a whole, which corresponds to the block coding circuit 11 shown in FIG. Reference numeral 211 denotes an 8-10 conversion circuit, which includes a ROM table 212 and a DSV (Digita).
l Sum Variation) arithmetic circuit 213 is connected, and 10-bit output data is generated from 8-bit input data according to a predetermined conversion rule (rule A and rule B), which will be described later in detail.

On the other hand, in FIG. 2, reference numeral 240 denotes the extraction circuit as a whole, which corresponds to the extraction circuit 14 shown in FIG. The extraction circuit 240 includes a pair of level comparators 24.
1, 242 and an OR circuit 243 to which the outputs of the comparators 241 and 242 are supplied.

The input signal from the terminal in is added by the adder 244.
Through the non-inverting input terminal of one level comparator 241 and the inverting input terminal of the other level comparator 242 through the low-pass filter 245 and the coefficient unit 246.
And is supplied to the adder 244 through.

The output signal of the OR circuit 243 is led to the terminal out and is supplied to the subtractor 252 through the low pass filter 251. A voltage source 253 having a voltage Vcc / 2 which is half the power supply voltage is connected to the subtractor 252, and the output signal of the subtractor 252 is output as a first reference voltage (slice level) SL1 through a coefficient multiplier 254. ,
It is supplied to the inverting input terminal of one of the level comparators 241 and is also fed through the inverting circuit 255 and the adder 256 to the second
Is supplied to the non-inverting input terminal of the other level comparator 242 as the reference voltage (slice level) SL2.

The output signals of the level comparators 241 and 242 are supplied to the adder 263 through the low pass filters 261 and 262, respectively, and the output signal of the adder 263 is supplied to the adder 256 through the coefficient unit 264. To be done.

[Recording Format] Next, the recording format of the optical disc to which the present invention is applied will be described with reference to FIG.

Although not shown, each sector of the write-once type or rewritable magneto-optical type optical disk comprises a pre-format area and a data area, and the data recording area is, for example, as shown in FIG. 3B. In format,
Data is recorded. As the modulation method of recorded data,
For example, NRZ (Non Return to Zero) is used.

As shown in FIG. 3B, in the data recording area, a VFO (Variable Freqency Oscilator) area for pulling in the PLL in advance at the time of reproduction of the optical disk, and a SYNC area which is a synchronization signal of data for each predetermined length, for example. Is provided. The VFO has a shortest cycle and has no DC component, that is, a so-called DC-free VFO, for example, "010101".
A data pattern such as "010101" is used. A similar data pattern is also used for SYNC.

Following this SYNC area, 10
32 data words D00 to D31 of bits are recorded,
Then, if there is a defect such as dropout in these data words, in order to prevent the propagation of error, for example, 2
A 0-bit resynchronization signal RESYNC is added.
Then, following this RESYNC, the next 32 data words D32 to D63 each having 10 bits are recorded,
The same is repeated thereafter.

The RESYNC is also preferably DC-free, and a fixed pattern of known length is used. Further, the error correction of the data D00 to D31; D32 to D63 ... Is performed in the column direction (vertical direction in the figure).

[Block Coding] Next, the block coding of the embodiment shown in FIG. 1 will be described.

In the embodiment shown in FIG. 1, the 8-10 conversion circuit 21 is used.
1, the 10-bit output data words D00 to D31; D32 to D63, ... Are generated from the 8-bit input data word so as to be DC-free, and the following conversion rule A is used. , B, the output data is selected.

That is, in rule A, when converting an 8-bit input data word into a 10-bit output data word, each 10-bit output data word is converted into the output data word of FIG.
As shown in A, at least one combination of "11" or "00" in which two consecutive bits have the same value is used.
Select to include the group.

However, if this condition is satisfied and D
The number of C-free codes is less than the total number of 8-bit input data (256).
For the bit input data, the code having a DC value of [+2] or [-2] is selected according to the DC value of the previous code, and is DC-free through the two codes.

Further, in the rule B, for example, every 32 output data words D00 to D31; D32 to D63;
The number of combinations in which two consecutive bits have the same value and different values, that is, the number of sets of “11” and the number of sets of “00” are equal.

In this embodiment, as shown in FIG.
One bit Y at the end of RESYNC inserted for every two output data is used as an inversion control bit, and "1" of subsequent data is set.
The number of sets of "1" and the number of sets of "00" are counted in advance, and the control bit Y is set to "1" or "0" according to the counting result.
As a result, the rule B can be executed by controlling whether or not to invert the subsequent 32 output data.

In other words, the control bit Y is NRZI (Non
The processing corresponding to “1” (reverse) or “0” (non-reverse) of Return to Zero Inverse is performed.

When the control bit Y is "1", for example, binary original data such as "100111" described above is 8-
It is inverted in the 10 conversion circuit 211 to generate “01100
When it becomes "0" and is processed by a precoder compatible with the PR (1, 1) system, ternary intermediate data such as "12100" is generated. This data has a form in which “2” and “0” are exchanged, as compared with “10122” described above.

Further, INV in which the control bit Y becomes "0"
1 and INV2 in which the control bit Y is "1" are selected as follows. In this embodiment, "11" in the data area is set to [+1] and "00" is set to [-1].
The sum of these values is "DSVA" (Digital Sum Vari
ation of Analog value). Then, the following formulas P00, P11, P12 are calculated, and the smaller one of the sets of P11, P12 is selected.

P00 = DSVA (VFO) + DSVA (SYNC) + D
SVA (D00 to D31) + DSVA (RS1) P11 = P00 + DSVA (INV1) + DSVA (D32 to
D63) + DSVA (RS2) P12 = P00 + DSVA (INV2) + DSVA (D32 ~
D63) + DSVA (RS2) In the above equation, RS1 and RS2 are R in FIG. 3B.
ESYNC (1) and RESYNC (2) are shown, respectively. Also, DSVA (OO) means calculating the DSVA of OO.

Thereafter, similarly, P21, P22; P31, P
32; ... Is calculated, and the smaller one of the sets is sequentially selected, and INV1 or INV2 is selected so as to minimize the absolute value of the DSVA of one sector.

Thus, the reproduction signal of each sector can be treated as a DC-free signal after passing through the PR (1,1) type transmission path.

[Slice Level Setting and Correction] Next, the slice level setting and correction of the embodiment of FIG. 2 will be described.

Adder 2 connected to input terminal in of FIG.
The first loop composed of 44, the low-pass filter 245 and the coefficient unit 246 is for removing an offset that may occur in the circuit system of the previous stage such as an amplifier. By passing through this first loop, , The DC center value of the input signal is set to zero V. In other words, the input signal from the terminal in is DC free.

The second loop from the output terminal of the OR circuit 243, the low-pass filter 251, the subtractor 252, and the coefficient unit 254 to the inverting input terminal of the one level comparator 241 is the optical disk recording / reproducing system. When there is no asymmetry in the transmission line 13 (see FIG. 4) and the eye pattern of the input signal from the terminal in is vertically symmetrical as shown in FIG. 6B, the slice level SL1, This is for automatically setting SL2.

When no asymmetry occurs in the transmission line 13, the output of the level comparator 241 becomes "1" below the normal slice level SL1 and the output of the level comparator 242 becomes the normal slice level SL2. It becomes “1” on the upper side, and both are output through the OR circuit 243.

According to the conversion rule in block coding as described above, the input signal from the terminal in is D
Since it is C-free, the output level of the OR circuit 243 is
If the power supply voltage is Vcc, it should be half the voltage Vcc / 2.

Therefore, the subtractor 252 obtains the deviation of the output level of the OR circuit 243 with respect to the voltage Vcc / 2 of the voltage source 253. The coefficient multiplier 254 multiplies the deviation by a predetermined constant K2 to make it sufficiently large. Level comparator 24
1 and the non-inverting input terminal of the level comparator 242 through the inverting circuit 255, thereby utilizing the DC free state and slicing the slice level SL.
1, SL2 can be automatically set.

Further, from the output terminals of both level comparators 241, 242, low-pass filters 261, 262 and adder 26.
3, the coefficient loop 264 and the adder 256, and the third loop reaching the non-inverting input terminal of the other level comparator 242 causes asymmetry in the transmission line 13 to generate asymmetry as shown in FIGS. 6A and 6C. If the eye pattern of the input signal from the terminal in is vertically asymmetrical, the slice level S
This is for automatically correcting L1 and SL2.

In this embodiment, as described above, in block coding, for example, for every 32 output data, the number of sets of "11" and the number of sets of "00" are equal.

After passing through the PR (1,1) format transmission path, the binary original data “00” is changed to the ternary intermediate data “0” and the binary original data “0”. “11” changes to three-valued intermediate data “2”.

Therefore, the signal obtained from the output terminal of the one level comparator 241 is "0" of the binary original data.
Which corresponds to the number of sets of "0" and the other level comparator 24
The signals obtained from the two output terminals correspond to the number of sets of “11” of the binary original data.

The output signals of the level comparators 241 and 242 are integrated by the low pass filters 261 and 262 and added by the adder 263. When the input signal from the terminal in is vertically asymmetrical as shown in FIGS. 6A and 6C, the addition result of the adder 263 corresponds to the deviation of the ternary intermediate data from “1”.

Then, this deviation is multiplied by a predetermined constant K3 by the coefficient unit 264 and returned to the non-inverting input terminal of the level comparator 242 through the adder 256, whereby the slice levels SL1 and SL2 are automatically corrected. You can

As a result, in this embodiment, when data that can be handled as a DC-free signal is used after passing through the PR (1,1) format transmission line in accordance with the conversion rules described above, When the asymmetry does not occur in the transmission line, the slice level can be automatically set by feeding back the deviation between the output signals of both level comparators and the predetermined voltage, and the asymmetry in the transmission line 13 Even if it occurs, the slice level can be automatically set by integrating and adding the output signals of both level comparators and feeding back.

[Other Embodiments] The present invention has been described above in the case where the 8-10 conversion is used for the block coding. In the block coding, DC-free processing, the number of sets of "11", and "00" are used. Since the number of sets of 8 is a control target, it is possible to use, for example, 8-9 conversion by applying the conversion rule as described above.

Further, in each of the above-described embodiments, the case where the present invention is applied to the transmission line corresponding to the class 1 of the partial response system has been described, but the conversion rule and the arithmetic expression as described above are appropriately changed. As a result, it is easy to apply it to another class of the partial response method, for example, class 4.

[0063]

As described above, according to the first aspect of the present invention, in the binary data encoding method for converting m-bit input data into n (n> m) -bit output data, The output data is "11" or "0".
It is suitable for the edge recording method because it is selected so as to include at least one set of "0" and the number of sets of "11" is equal to the number of sets of "00" for each predetermined amount of output data. When transmitting data via a transmission system compatible with a predetermined partial response method, the signal is D
C-free, which facilitates level determination as a multi-valued signal, that is, extraction of data.

According to the second aspect of the present invention, in the multi-valued data extracting device, the automatic setting means for automatically setting the slice levels of the plurality of level comparators to which the input signals are commonly supplied are provided. Since the automatic correction means for automatically correcting the slice level of each level comparator when the asymmetry is generated in the input signal is provided, it is encoded by the method of the first invention as described above and a predetermined value is obtained. When a DC-free input signal is supplied through a transmission system supporting the partial response method, each slice level is automatically set by the automatic setting means, and asymmetry occurs in the input signal. In this case, the slice level is automatically corrected by the automatic correction means, and the multi-valued data is extracted easily and stably.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment according to a binary data encoding method according to the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of an embodiment of a multi-valued data extraction device according to the present invention.

FIG. 3 is a conceptual diagram for explaining the operation of one embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of a conventional multi-valued data extraction device.

FIG. 5 is a conceptual diagram for explaining the operation of a conventional example.

FIG. 6 is a conceptual diagram for explaining an operation of a conventional example.

[Explanation of symbols]

 11,210 Block coding circuit 12 Precoding circuit 13 Transmission path 14,240 Extraction circuit 241,242 Level comparator 251-256 Automatic setting means 261-264 Automatic correction means SL1, SL2 Slice level

Claims (9)

[Claims] 1. An m-bit input data is converted into an n (where n> m) -bit output data in order to transmit the data through a transmission system based on an edge recording method.
In the value data encoding method, the output data is selected so as to include at least one combination in which two consecutive bits have the same value, and two consecutive bits have the same value, and A method for encoding binary data, wherein the number of combinations having different values is made equal for each predetermined amount of the output data. 2. The binary data encoding method according to claim 1, wherein an inversion control bit is added for each predetermined amount of the output data. 3. The method of encoding binary data according to claim 1, wherein the transmission system has a class 1 characteristic of a partial response system. 4. The transmission system is an optical recording / reproducing system.
The method of encoding binary data described in. 5. A multi-valued data extracting device in which an input signal is commonly supplied to a plurality of level comparators to which respective predetermined reference voltages are set, wherein the reference voltages corresponding to the plurality of level comparators are automatically set. A device for extracting multi-valued data, characterized in that automatic setting means for automatically setting the input voltage is provided, and automatic correction means for automatically correcting the reference voltage when asymmetry occurs in the input signal. 6. The multilevel data extracting apparatus according to claim 5, wherein the input signal is supplied through a transmission system having a class 1 characteristic of the partial response system. 7. The multi-valued data extracting device according to claim 5, wherein the input signal is a reproduction signal corresponding to data having no DC component. 8. A multi-valued data extracting device according to claim 5, wherein said automatic setting means includes means for obtaining a deviation between output signals of said plurality of level comparators and a predetermined voltage to form a feedback loop. 9. A feedback loop including a plurality of integrators to which the output signals of the plurality of level comparators are respectively supplied, and an adder for adding the output signals of the plurality of integrators, wherein the automatic correction means includes a feedback loop. The extraction device for multivalued data according to claim 5, which is formed.