JP2934441B2 - Data recording method - Google Patents

Description

The present invention relates to a data recording method applied to a data storage such as a CD-WO or a CD-RAM according to a data format of a so-called compact disk (CD).

[Conventional technology]

2. Description of the Related Art Conventionally, a reproduction-only disk player device such as a CD player for reproducing a so-called compact disk (CD) in which an audio signal such as voice or music is digitized and recorded on an optical disk has been generally provided.

In the above compact disc (CD), EFM (Eight to Fourteen Modulation) in which a signal of 8 bits per symbol is converted into data of 14 bits (1 channel bit).
24-bit synchronization signal given as data, 14-bit (1 symbol) subcode, 14 × 32-bit (32 symbol) performance information data and parity, and 3-bit margin provided between each symbol As shown in FIG. 6, a data format in which 588 bits made up of 588 bits constitute one frame and 98 frames constitute one subcode block has been standardized, and the absolute address of the one subcode block is one of the subcodes. , And data processing is performed on data such as performance information in units of one subcode block.

In EFM on the compact disc (CD), 14
Modulation is performed so that the number of consecutive “0” bits in the sequence of bit (1 symbol) data and 3 merging bits is 2 or more and 10 or less. Unbalanced value (DSV: Digital Su
m Value) is continuously counted, and the above-mentioned DSV is controlled by giving a merging bit having a bit pattern corresponding to the value of the DSV.

Also, the digital audio signals of the left and right channels recorded on the compact disc (CD) are alternately successively arranged for each word (2 symbols = 16 bits), and are treated as a serial data signal of one channel.
-In a ROM or the like, a header section and a synchronization signal are added before one subcode block in the data format of the CD, that is, data for 98 frames, thereby achieving the seventh data.
One sector (or one block) is composed of 2 Kbytes of data having a data format as shown in the figure.

Furthermore, since conventional CD players are exclusively for reproduction, recording and reproduction can be performed using, for example, a magneto-optical disk formed of a magneto-optical recording medium on which information can be rewritten, and compatibility with the above-mentioned CDs can be achieved. Keep CD-WO and CD-RA
The development of data storage such as M has been advanced.

[Problems to be solved by the invention]

By the way, in the CD data format, the DSV is controlled by continuously counting the DSV from the start position of the recording data and giving a merging bit of a bit pattern according to the value of the DSV as described above. Therefore, data cannot be written or rewritten from the middle. In data storage such as CD-WO and CD-RAM, it is necessary to efficiently manage data in block units.

In view of the above situation, the present invention converts m-bit data into n-bit data larger than the m-bit data, inserts p-bit merging bits between the n-bit data, Is modulated so that the number of consecutive "0" bits in the alternate sequence of n-bit data and p-bit merging bits is equal to or greater than a predetermined d and equal to or less than k and greater than d. In a data recording method for recording and a data recording medium such as CD-WO or CD-RAM in which the data is recorded, data can be written or rewritten in block units, thereby enabling data management in block units. It is intended to be.

[Means for solving the problem]

In order to achieve the above object, the present invention converts m-bit data into n-bit data larger than the m-bit data, inserts p-bit margin bits between the n-bit data, Is modulated so that the number of consecutive "0" bits is d or more and k or more and greater than d and k or less in an alternate sequence of n bits of data and p bits of merging bits. In the data recording method, a merging bit of a bit pattern corresponding to a DC unbalance value (DSV: Digital Sum Value) of recording data is added after the n-bit data to form a data block, and the recording data is recorded. The DC unbalance value is reset for each block.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the block diagram of FIG. 1 showing a modulation circuit used to carry out the method of the present invention, (1) indicates a CI (not shown).
This is a data input terminal to which an 8-bit parallel data signal (Sd) is supplied from the RC encoder.
This is a clock input terminal to which a MHz system clock signal (Sc) is supplied. (3) and (4) are 7.35.
kHz frame sync signal (Sf) and a block sync signal (S
b) is each sink input terminal to be supplied.

Here, between the frame sync signals (Sf), as shown in FIG. 2, 32 8-bit parallel data signals (Sd) based on CIRC-encoded audio signals are formed, and 8-bit parallel data signals (Sd) are formed. Is formed, and the data signal (Sd) and the subcode signal (SC) are formed.
Are selected at a predetermined timing by a selector (not shown) or the like and supplied to the data input terminal (1).

The data signal (Sd) is connected to the data input terminal (1)
Is supplied to a read-only memory (11), where the data is converted from 8-bit data to 14-bit data in accordance with a predetermined conversion table. 14 converted by the above read-only memory (11)
The data signal converted to bit data is stored in the register (1
2), (13), and (14).

The system clock signal (Sc), frame sync signal (Sf) and block sync signal (Sb) are sent to the system control circuit (15) via the input terminals (2), (3) and (4). Supplied. The system control circuit (15) controls the operation of each circuit block in units of 98 frames, that is, one subcode block, based on the system clock signal (Sc), the frame sync signal (Sf), and the block sync signal (Sb). Do.

Here, in the CD data format, the sync pattern in the data signal is [1000000000000100000000001
0]. In this embodiment, since the registers (12), (13), and (14) handle 14-bit data in this embodiment, [1000000000010
0] in the output stage.
It restores to a 4-bit sync pattern.
The 14-bit pattern data is stored in the read-only memory (16) by a signal from the system control circuit (15) corresponding to the frame sync signal (Sf), and the registers (12), (13), ( Supplied to 14). Also, in the above-described sub-code signals, specific pattern data of S ₀ = [00100000000001] S ₁ = [00000000010010] is inserted every one sub-code block, ie, every 98 frames, so these signals (S ₀ ) , (S ₁ ) are formed in the read-only memory (16) by a signal from the system control circuit (15) according to the block sync signal (Sb), and are stored in the registers (12), (13), (14).

These signals correspond to the above registers (12), (13), (14)
, The previous data is held in the register (13), and the data immediately before the data held in the register (12) is stored in the register (14). Will be retained.

Further, the number of leading "0" s and the terminating "0" of the 14-bit data formed in the read-only memories (11) and (16) are uniquely determined by the data signal (Sd). Are formed simultaneously with the data signal. Here, the number of leading and trailing “0” s of the 14-bit data is determined to be 9 or less in the above conversion table, and is represented by 4 bits. In the sync pattern, the number of “0” at the end of the 14-bit replacement data is 2
However, since there is one in a 24-bit pattern, the number of “0” at the end in this case is set to [0001]. These four
Bit-by-bit signals are also stored in registers (12), (13), (1
Transferred in the same way as the data signal in 4).

The numerical value (F ₁ ) indicating the number of “0” at the end of the register (12) and the numerical value (B ₂ ) indicating the number of “0” at the end of the register (13) are 3 bits of merging bits. It is supplied to the addresses of the read-only memories (17) and (18) to be formed.

Here, the merging bit is such that the number of consecutive “0” of [000], [001], [010], [100] in the read only memory (17), (18) is 2 or more. Are selected. Also, the merging bit needs to satisfy the rule that the number of consecutive “0” s inserted between the preceding and succeeding data signals is 2 or more and 10 or less. A number that indicates (F ₁₎
A bit pattern excluding a combination that does not satisfy the above rule is selected using a numerical value (B ₂ ) indicating the number of terminal “0” s as an address. Further, the merging bit is inserted between the preceding and succeeding data signals,
In order not to match the 24-bit sync pattern, when the pattern of the preceding and succeeding data signals is any of the following 11 patterns, the combination of each merging bit with an x mark is removed. The merging bits indicate all cases selected by the above numerical values (F ₁ ) and (B ₂ ).

The above 11 bit patterns can be distinguished by the current data, the previous data, the previous data, and the previous merging bit. In this example,
From the above read-only memory (17), the above numerical value (F ₁ ),
All merging bits are output for (B ₂ ), and the above numerical values (F ₁ ) and (B ₂ ) in the above 11 cases from the read-only memory (18) are marked with a cross. Output the merging bits excluding the combination. Further, the data signal held in the registers (12), (13) and (14) and the immediately preceding merging bit held in a register (42) described later are supplied to a detection circuit (19). The detection circuit (19) detects the above 11 cases. Normally, the read-only memory (17) according to the detection signal from the detection circuit (19)
Is selected, and in the above-mentioned 11 cases, the read-only memory (18) is selected.

In this embodiment, the read only memory (1
The merging bits output from (7) and (18) are supplied to the selector (20). The numerical values of 0 to 3 are sequentially supplied from the system control circuit (15) to the selector (21). The selector (21) initially selects the system control circuit (15) side, and supplies the selector (20) with numerical values of 0 to 3 from the system control circuit (15). Thus, the selector (20) selects an input, that is, a merging bit, according to the numerical value [0-3] from the system control circuit (15).

The merging bit selected by the selector (20) is supplied to the address of the read only memory (22), and the DSV and the polarity signal of the digital signal constituting the merging bit are read by the read only memory (22). Is formed. The data signal of the register (12) is supplied to the address of the read-only memory (23), and the DSV of the digital signal constituting the data signal and the polarity signal are formed in the read-only memory (23). Is done. The data signal and the signal indicating the DSV and the polarity of the merging bit are supplied to the DSV registers (24) and (25) and the polarity registers (26) and (27), respectively.

The signals from the DSV registers (24) and (25) are supplied to one input (A) of an addition / subtraction circuit (28). The other input (B) of the addition / subtraction circuit (28) has a cumulative DSV
The signal from the register (29) is supplied. further,
The signals from the polarity registers (26) and (27) and the signal from the cumulative polarity register (30) are combined with a logic circuit (3
The output of the logic circuit (31) controls the addition / subtraction of the addition / subtraction circuit (28).

The output signal of the addition / subtraction circuit (28) is
2), (33) and the absolute value circuit (34)
Are supplied to the registers (35) and (36) via the. The output signal of the register (36) is supplied to one input (A) of the addition / subtraction circuit (28). further,
The output signals of the registers (32), (33) and (35) are supplied to the other input (B) of the addition / subtraction circuit (28) and to the accumulation DSV register (29). .

The signal from the logic circuit (31) is supplied to the selector (3
7) are supplied. Further, a signal from the polarity register (38) is supplied to the selector (37), and the selector (37) is controlled by a signal from the addition / subtraction circuit (28), and a signal from the selector (37) is It is supplied to the polarity register (38). Then, the signal from the polarity register (38) is output from the cumulative polarity register (3
0).

Further, the numerical value supplied from the system control circuit (15) to the selector (21) is also supplied to the selector (39). The selector (39) is an indicator (40)
The selector (39) is controlled by a signal from the addition / subtraction circuit (28), and a signal from the selector (39) is supplied to the indicator (40). Further, a signal from the indicator (40) is supplied to the selector (21).

And these circuits are the system control circuit (15)
, And the merging bits in a combination state that is optimal for suppressing the DC component are selected while eliminating combinations that are problematic in the rules of the CD data format.

Here, to output a set of 14-bit data signal and 3-bit merging bit signal in series, 14 + 3 =
In the case where 17 clock periods of 17 are required and all the above data are processed in parallel, as shown in FIG.
Processing is performed at timings 0 to 16 using 17 time slots, and a new 14-bit pattern is input at the next timing 0.

That is, first, at timing 0, the register (12)
Is set to any 14-bit data. Then, during the period (A), each of the above read-only memories (17), (18),
(20) and (23) are accessed, and the read only memory (22) is accessed by the first merging bit selected by the selector (20).

Next, at timing 1, the read-only memory (2
The data signals from (2) and (23) and the DSV and polarity of the first merging bit are stored in the registers (24) and (2).
Set to 7). In the period (B), the outputs of the registers (25) and (29) are selected and supplied to the addition / subtraction circuit (28), and the polarity of the register (30) is selected by the logic circuit (31). Is taken out and supplied to the addition / subtraction circuit (28). When the polarity is negative ("0"), the addition (A + B) is performed. When the polarity is positive ("1"), the subtraction (AB) is performed.

The result of the operation by the addition / subtraction circuit (28) is calculated at timing 2
And the absolute value of this value is set in the register (35). During the period (C), the outputs of the registers (32) and (24) are selected and supplied to the addition / subtraction circuit (28), and the registers (30) and (30) are selected by the logic circuit (31). The exclusive OR of the output of 27) is taken out, and the above-mentioned addition / subtraction circuit (28) is controlled with this polarity.

The operation result and the absolute value of the addition / subtraction circuit (28) are set in the registers (32) and (35) at timing 3, and the exclusive OR output by the logic circuit (31) and the register (26) The exclusive OR with the contents of the above is taken out and cassetted in the register (38), and 0 is set in the indicator (40).

During this period (C), the selector (20) selects the second merging bit, and sets the output of the read-only memory (22) in the registers (25) and (26) at timing 3. I do. In the period (D), the outputs of the registers (25) and (29) are set in the addition / subtraction circuit (28), and the operation according to the polarity of the register (30) is performed in the addition / subtraction circuit (28). Perform at

The operation result and the absolute value of the addition / subtraction circuit (28) are set in the registers (33) and (36) at timing 4. Then, in the period (E), the registers (33),
The output of (24) is set in the addition / subtraction circuit (28), and an operation according to the polarity of the exclusive OR of the registers (30) and (26) is performed in the addition / subtraction circuit (28).

The operation result and the absolute value of the addition / subtraction circuit (28) are set in the registers (33) and (36) at timing 5. In the period (F), the registers (35),
The output of (36) is set in the addition / subtraction circuit (28) and (B
The calculation of -A) is performed by the addition / subtraction circuit (28).

At timing 6, when the operation result by the addition / subtraction circuit (28) is positive, the absolute value of the content of the register (32) is larger than the absolute value of the content of the register (33). The contents of register (33) are transferred to register (32), and
0), the exclusive OR of the contents of (26) and the contents of the register (27) are taken out and set in the register (38), and 1 is set in the indicator (40). set.

Also, during this period (F), the third merging bit is selected by the selector (20), and the output of the read-only memory (22) is set in the registers (25) and (26) at timing 6. I do.

Similarly, the arithmetic processing for the third merging bit is performed in the periods (G) to (I), and the arithmetic result is set in the indicator (40) at timing 9.

Further, the fourth merging bit is set at timing 9, and the arithmetic processing for this is performed during period (J) to
At (L), the calculation result is set in the indicator (40) at timing 12.

During the period (M), the selector (21) is switched to the indicator (40) side, and the selector (20) is switched according to the content of the indicator (40).
The optimum merging bit selected at the timing 13 is supplied to the register (41). At this time, since the contents of the registers (32) and (38) are the accumulated DSV and the polarity corresponding to the above-mentioned optimum merging bits, these values are stored in the registers (29) and (30). Set to.

Further, the contents of the register (41) are transferred to the register (42) at the next timing 0, and the three merging bits of the register (42) and the 14 bits of the register (13) are transferred.
The 17-bit signal is supplied to a shift register (43) for parallel / serial conversion by combining the bit data signals. The contents of the shift register (43) are read out according to the system clock signal (Sc), and the exclusive OR circuit (44) restores the sync pattern to obtain the flip-flop (45).
Is output from the output terminal (46) via the.

In this embodiment, the registers (29) and (30) for holding the accumulated DSV and the polarity are reset every 98 frames, that is, for each subcode block, so that the DSVs independent for each subcode block are set. Control is performed to form recording data in which merging bits of a bit pattern corresponding to the DSV value are inserted between the n (n = 14) bits of data. Since the recording data is controlled independently of DSV in units of one subcode block, the unit of one subcode block is one unit.
It can be individually managed as block data as a sector and recorded and reproduced.

The data block of one subcode block (one sector) thus obtained is recorded on, for example, an optical disk (101) as shown in FIG.

FIG. 4 schematically shows the whole and a part of the data recording medium according to the present invention in an enlarged scale.
1) As a recording medium, for example, a magneto-optical disk in which a perpendicular magnetization film having a magneto-optical effect is formed on a transparent substrate is used, and a pregroove (102) formed in a spiral shape is used.
The land between the recording tracks (103) is, for example, the CD-ROM described above obtained by the modulation circuit shown in FIG.
2K-byte block data according to the above data format is magneto-optically recorded on the recording track (103).

In the recording track (103), an address whose track width is changed in a burst shape at an equal interval position corresponding to a synchronization signal (SYNC) portion or an error correction signal (ECC) portion in the data format of the CD-ROM. An area (4) is provided, and for example, 19-bit address information is stored in each address area (10
Recorded in 4) in advance. The signal spectrum of the address information due to the change in the track width is a component above the servo band.

The optical disc (101) has a lead-in area (107) on the inner peripheral side of a data area (6) where data is recorded.
Is provided, and lead-in information indicating the recording status of the data area (106) is recorded in the lead-in area (107).

As described above, in a disk device using an optical disk (101) having a recording track (103) in which address information of a predetermined bit is recorded in advance in each address area (104) due to a change in track width as a data storage, data is read. As an optical pickup to be performed, for example,
Each detector (A), (B), (C),
By using the four-divided detector (110) constituted by (D), each of the above detectors (A), (B),
(C) and (D) outputs (S _A ), (S _B ), (S _C ),
(S _D) addition was added output signal by the adder (111) (S _A
+ S _B + S _C + S _D ), and the detectors (A), (A), which are arranged in the longitudinal direction (XX ′ direction) of the recording track (103). The adder (11) of each output (S _A ) and (S _B ) of ( _B )
2) Addition output (S _AB ) and the above detectors (C),
A subtraction output signal (S _AB −S _CD ) obtained by subtracting the output (S _C ) of ( _D ) and the addition output (S _CD ) of the (S _D ) by the adder (113) by the subtractor (114), The above recording track (103)
The detectors (A) and (B) and the detectors (C), which are arranged in the width direction (YY 'direction) of
Address information (ADR) can be detected as push-pull outputs of each output (S _A ), (S _B ), (S _C ), and (S _D ) of ( _D ).

In this optical disc (101), the recording data is 1
It is possible to record and reproduce recorded data on which DSV control independent for each sub-code block is performed by individually managing the above-mentioned one sub-code block unit as block data of one sector.

〔The invention's effect〕

In the method of the present invention, the DC unbalance value (DSV: Di
Since the merging bit of the bit pattern corresponding to the “gital sum value” is added to the n-bit data to form a data block, and the DC unbalance value is reset in units of blocks for recording the recording data, the recording is performed. The DC unbalance value of data can be controlled independently in data block units, and writing or rewriting in data block units does not affect the contents of recorded data in other data blocks. Therefore,
According to the present invention, data can be written or rewritten in block units on a data recording medium such as CD-WO or CD-RAM, and data management in block units can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a modulation circuit used to carry out the method of the present invention, FIG. 2 is a schematic diagram showing the relationship between signals in the modulation circuit, and FIG. FIG. 4 is a time chart for explaining, FIG. 4 is a schematic plan view of an optical disc to which the data recording medium according to the present invention is applied, and FIG. 5 is a schematic view showing a configuration of an optical pickup for reading data from the optical disc. It is. FIG. 6 is a schematic diagram showing a data format of a compact disk (CD), and FIG. 7 is a schematic diagram showing a data format of a CD-ROM. 101 optical disk 103 recording track

Claims (1)

(57) [Claims] 1. Converting m-bit data into n-bit data larger than the m-bit data, inserting p-bit merging bits between the n-bit data,
Data is recorded by modulating such that the number of consecutive "0" bits is d or more and k or more and greater than d and k or less in the alternating sequence of these n-bit data and p-bit merging bits. In the data recording method, the DC unbalance value (DSV: Digital Sum Value) of the recorded data
A data pattern formed by adding a merging bit of a bit pattern according to the following to the n-bit data to form a data block, and resetting the DC unbalance value for each block in which the recording data is recorded. Method.