JPH0389627A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To obtain an analog signal with less distortion by subtracting a compensating signal which includes the component cut off by a limiter, from a shift signal. CONSTITUTION:A limiter output D is subtracted from an addition output C by a compensating signal generating circuit 7 to obtain a compensating signal E. This signal E corresponds to the component cut off by a limiter 6. A signal F=B-E obtained by subtracting the compensating signal E from a shift signal B is obtained in a subtractor 8. The limiter output is converted to an analog signal by first digital.analog converter(DAC) 5, and the signal F is converted to an analog signal by a second DAC 9, and a waveform approximately coinciding with the original waveform is obtained by analog-subtracting in a subtracting circuit 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention improves zero-cross distortion and quantization/distortion that occur when digital-to-analog (D/A) converts a digital signal corresponding to an audio signal or the like. The present invention relates to a digital-to-analog converter equipped with a circuit.

[Prior Art] In a digital/analog converter (D/A converter), for example, offset binary [1000] to [
It is well known that the greatest distortion occurs when the most significant bit (MSB) in one word of a digital signal changes, such as when the most significant bit (MSB) in one word of a digital signal changes. When the MSB change point is at the zero volt point (zero cross) of the input signal,
Since the distortion rate of low-level signals worsens, adding some kind of voltage shift signal to the input signal
Techniques for avoiding this are known. The shift signal is generally a signal that provides a DC offset, a dither, or the like. However, when a shift signal is added, there is a possibility that the input of the D/A converter may exceed this dynamic range, and if this occurs, large waveform distortion will occur. To solve this problem, there is already a D/A converter that is provided with a level detection circuit and a circuit that interrupts the addition of shift signals during a period in which the dynamic range is exceeded.

[Problems to be Solved by the Invention] However, if the addition of shift signals is interrupted, a discontinuous point as shown in FIG. 5 (A>) occurs in the analog signal after D/A conversion.This discontinuous point can be resolved. In order to do this, it is conceivable to add a compensation signal corresponding to the shift signal shown in FIG. 5(B) to the analog signal.

However, if the shift signal added to FIG. 5(A) is not completely subtracted when returning to the original signal, distortion due to discontinuous points as shown in FIG. 5(C) will still occur.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital-to-analog converter capable of improving waveform discontinuity when preventing overflow of a D/A converter.

[Means for Solving the Problems] The invention according to claim 1 to achieve the above object provides a digital signal generation circuit that generates a digital signal, and a shift signal generation circuit that generates a shift signal for distortion improvement in a digital format. an adder for adding the shift signal to the digital signal; a level detection circuit for determining whether the output of the adder exceeds a certain digital value; When an output indicating that the output of the adder is less than the predetermined digital value is generated, a value substantially the same as the output of the adder is output, and the output of the adder is output from the level detection circuit. a digital limiter that outputs the predetermined digital value when an output indicating that the predetermined digital value is greater than or equal to the predetermined digital value; and an output of the adder from the level detection circuit that is greater than or equal to the predetermined digital value. a compensation signal forming circuit for forming a compensation signal corresponding to a value obtained by subtracting the certain digital value from the output of the adder in response to an output indicating the shift signal; a first digital-to-analog converter for converting the output of the limiter into an analog signal; and a second digital-to-analog converter for converting the output of the subtracter into an analog signal.・
The present invention relates to a digital-to-analog conversion device including an analog converter and an analog subtraction circuit for subtracting the output of the second digital-to-analog converter from the output of the first digital-to-analog converter. .

The invention according to claim 2 also provides a digital signal generation circuit that generates a digital signal, a shift signal generation circuit that generates a shift signal for distortion improvement in a digital format, and an inversion circuit that forms an inversion signal of the digital signal. , a first for adding the shift signal to the digital signal.
an adder, a first level detection circuit for determining whether the output of the first adder exceeds a certain digital value, and a first addition from the first level detection circuit. When an output indicating that the output of the adder is less than the predetermined digital value is generated, the adder outputs substantially the same value as the output of the first adder, and the first level detecting circuit outputs the value substantially the same as the output of the first adder. a first digital limiter that outputs the predetermined digital value when an output indicating that the output of the first adder is equal to or greater than the predetermined digital value; Corresponds to a value obtained by subtracting the certain digital value from the output of the first adder in response to an output indicating that the output of the first adder is greater than or equal to the certain digital value. a first compensating signal forming circuit for forming a first compensating signal, a second adder for adding the shift signal to an inverted digital signal obtained from the inverting circuit; a second level detection circuit for determining whether the output of the adder exceeds a certain digital value; When an output indicating that the value is less than the predetermined value is generated, a value substantially the same as the output of the second adder is outputted, and the output of the adder is output from the second level detection circuit to the predetermined digital value. a second digital limiter that outputs the constant digital value when an output indicating that the digital value is greater than or equal to the value is generated;
When the level detection circuit generates an output indicating that the output of the second adder is greater than or equal to the predetermined digital value, the output of the second adder determines the predetermined digital value. a second compensation signal forming circuit for forming a second compensation signal corresponding to the value obtained by subtracting the second compensation signal; and a first compensation signal forming circuit for subtracting the second compensation signal from the output of the first digital limiter. a subtracter, a second subtracter for subtracting the first compensation signal from the output of the second digital limiter, and a first subtracter for converting the output of the first subtracter into an analog signal. a second digital-to-analog converter for converting the output of the second subtracter into an analog signal;
The present invention relates to a digital-to-analog conversion device comprising an analog subtraction circuit for subtracting the output of the second digital-to-analog converter from the output of the first digital-to-analog converter.

Note that the adder, subtracter, and subtraction circuit in Claims 1 and 2 can be configured so that the adder can be converted into a subtracter by reversing the phase or polarity of one of these inputs, and the subtracter or subtraction circuit can be configured as an adder. It can be changed. Therefore, addition and subtraction in the present invention are terms used for convenience and are interchangeable.

[Function] The compensating signal forming circuit of the invention of claim 1 obtains a component that has been truncated by the limiter. The compensation signal containing this component and the shift signal (DC offset signal or dither signal) are subjected to subtraction processing.

For example, the polarity (phase) of the compensation signal is inverted and added to the shift signal. The second digital-to-analog signal converts both the shift signal to be subtracted and the compensation signal into analog signals. In the subtraction circuit, the shift signal is subtracted, and as a result, a compensation signal is added to obtain an analog signal with less distortion.

A similar effect can also be obtained in the invention of claim 2.

[First Embodiment] Next, a digital-to-analog converter according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

A digital signal generating circuit 1 shown in FIG. 1 is a playback circuit in, for example, a CD player, and sequentially outputs, at a fixed sampling period, a digital signal A in, for example, a 16-bit offset binary format corresponding to an analog signal such as audio. .

In this embodiment, the shift signal generating circuit 2 generates a shift signal B in an offset binary format corresponding to a DC offset in an analog signal corresponding to a digital signal. Note that the shift signal B is sent out at the same sampling period as the digital signal. Further, this shift signal B is a signal whose level is sufficiently lower than the maximum level of the digital signal A.

The digital adder 3 has one input terminal connected to the digital signal generation circuit 1 and the other input terminal connected to the shift signal generation circuit 2, and outputs the sum of the digital signal A and the shift signal B = C= Generates A+-B.

Based on the digital signal A generated from the digital signal generation circuit 1 and the output C of the adder 3, the level detection circuit 4 detects that the addition output C is output from the first digital-to-analog converter (
It is determined whether the overflow level of 5 (hereinafter simply referred to as DAC) or a certain level set lower than this has been reached.

A digital limiter 6 connected to the adder 3 and the level detection circuit 4 outputs the addition output C as it is in response to a level detection signal indicating that the addition output C has not reached a certain level, and It continuously outputs a digital value at a constant level in response to a level detection signal indicating that the output C is above a certain level. The compensation signal forming circuit 7 is composed of a digital subtraction circuit, and one input terminal is connected to the adder 3 and the other input terminal is connected to the limiter 6. Therefore, from this compensation signal forming circuit 7, a compensation signal E consisting of a value obtained by subtracting the limiter output from the addition output C is obtained.The compensation signal E is as follows.
This corresponds to the component cut off by limiter 6.

The digital subtracter 8 is connected to the shift signal generating circuit 2 and the compensation signal forming circuit 7, and outputs a signal F=B−E obtained by subtracting the compensation signal E from the shift signal B.

The first DAC 5 connected to the limiter circuit 6 converts the output of the limiter 6 into an analog signal, and has the same dynamic range as the adder 3 in this embodiment. The second DAC 9 converts the output F of the subtracter 8 into an analog signal.

The analog subtraction circuit 10 converts the output of the first DAC 5 to the second DAC 5.
A waveform obtained by multiplying the output of the DAC 9 by $4 is output.

[Operation] FIGS. 2A to 2F are explanatory diagrams showing the states of points A to F in FIG. 1 using analog analogy. In addition, Fig. 2 (A
) shows a sine wave analog signal corresponding to the digital signal A having the largest dynamic range of the adder 3 and the first DAC 5. When the digital shift signal B shown in FIG. 2(B) is added to the digital signal A shown in FIG. 2(A), an overflow 3 of the adder 3 occurs near the maximum value of the digital signal A as a natural result.

As shown in FIG. 2(C), the output of A+B is obtained in the positive region in the period tO to t1 and the period t2 to t3 where no overflow occurs, but the output from t1 to t1 where overflow occurs.
In the t2 period, overflow occurs, the sign is reversed, and an output is obtained in the negative region.

The limiter 6 outputs the addition output C as is during non-overflow periods such as tO to t1 and t2 to t3, and continuously outputs a constant value (maximum I) during overflow periods such as t1 to t2. Output to. As a result, the output shown in FIG. 2(D) is obtained from the limiter 6.

In the compensation signal forming circuit 7, the compensation signal E shown in FIG. 2(E) is obtained by subtracting the limiter output from the addition output C. This compensation signal E corresponds to the component cut off by the limiter 6. In the subtracter 8, the signal F=B−E obtained by subtracting the compensation signal E in FIG. 2(E) from the shift signal B in FIG. 2(B) is obtained as FIG. 2(F).
obtained as shown in .

The first DAC 5 converts the limiter output in Figure 2 <D) to an analog signal, the second DAC 9 converts the signal in Figure 2 (F) to an analog signal, and the subtraction circuit 10 converts the limiter output in Figure 2 (D) )
When the waveform of Fig. 2 (F) is analog subtracted from the waveform of
A waveform substantially matching the original waveform shown in FIG. 2 (A>) is obtained.

In FIG. 2, the signal in FIG. 2 (F) changes slowly at time tl and 52, so even if the shift signal remains in the subtraction circuit 10, the output waveform of the subtraction circuit 10 changes at tl and 52. Therefore, an analog signal with little distortion can be obtained.

Note that when the level of the digital signal A is low, the output of the limiter 6 matches the addition output C, and the output of the compensation signal forming circuit 7 becomes zero.

[Second Embodiment] Next, a D/A converter according to a second embodiment of the present invention will be described with reference to FIGS. 3 and 4.

However, the items indicated by reference numerals 1.2.5.9.10 in FIG. 3 are substantially the same as those indicated by the same reference numerals in FIG. , 6b, 7
The items indicated by a, 7b, 8a, and 8b are 3.4.6 in Figure 1.
．． Since it is substantially the same as that shown in 7.8, detailed explanation thereof will be omitted.

In this second embodiment, a phase inversion circuit 11 is connected to a digital signal generation circuit. The digital signal shown in FIG. 4(A) and the shift signal from the shift signal generation circuit 2 are input to the first adder 3a, and these are added. The inverted digital signal and shift signal shown in FIG. 4(B) are input to the second adder 3b, and these are added. The first and second level detection circuits 4a and 4b are substantially the same and detect overflows of the first and second adders 3a and 3b. 1st and 2nd rimino taro a, 6b
operates in the same manner as the limiter 6 in FIG. 1, and generates the output shown in FIG. 4(C) (D>) at the time of overflow.

The first and second compensation signal forming ports R7a, 7b are
and a fourth limiter by subtracting the outputs of the first and second limiters 6a, 6b from the outputs of the second adders 3a, 3b.
The first and second compensation signals shown in FIGS. (E) and (F) are formed.

The first subtracter 8a subtracts the second subtracter from the output of the first limiter 6a.
Figure 4 (G) is obtained by subtracting the output of the compensation signal forming circuit 7b
) forms a signal. The second subtracter 8b subtracts the output of the first compensation signal forming circuit 7a from the output of the second limiter 6b to form the signal shown in FIG. 4 (G I).

The first and second DACs 5 and 9 convert the signals shown in FIGS. 4(G) and 4(H) into analog signals. The subtraction circuit 10 subtracts the output of the second DAC 9 from the output of the first DAC 5, and outputs the waveform shown in FIG. 4(I).

This embodiment has the same effects as the first embodiment, and also has the advantage that a waveform with a larger dynamic range than the DAC 5 can be obtained from the subtraction circuit 10.

[Modifications] The present invention is not limited to the above-described embodiments, and, for example, the following modifications are possible.

(1) A digital dither can be added as a shift signal instead of a DC offset signal.

(2) Limiter 6.6 to form a compensation signal
An independent limiter can be provided separately from a and 6b.

(3) In order to detect a predetermined level with the level detection circuits 4.4a and 4b, a reference level is set, and this reference level is combined with the output of the adders 3.3a and 3b or the output of the digital signal forming circuit and the inversion circuit 11. An excessive level may be detected by comparing the output of the

[Effects of the Invention] According to the inventions of claims 1 and 2, waveform discontinuity can be easily improved. According to the invention of claim 2, it is possible to further expand the dynamic range.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a D/A converter according to the first embodiment of the present invention, FIG. 2 is a waveform diagram showing the state of each part in FIG. 1 by analog analogy, and FIG. A block diagram showing the D/A converter of the second embodiment, and FIGS. 4(A) to (I) show the states of each part in FIG. 3, among which (A) to (H) are analog Waveform diagrams shown by analogy, (I) are output voltage waveform diagrams, and FIG. 5 is a diagram showing conventional waveforms at the time of overflow. DESCRIPTION OF SYMBOLS 1... Digital signal generation circuit, 2... Shift signal generation circuit, 3... Adder, 4... Level detection circuit,
5... DAC16... Limiter, 7... Compensation signal forming circuit, 8... Subtractor, 9... DAC510.
...Subtraction circuit.

Claims (1)

[Scope of Claims] [1] A digital signal generation circuit that generates a digital signal, a shift signal generation circuit that generates a shift signal for distortion improvement in a digital format, and a circuit for adding the shift signal to the digital signal. an adder; a level detection circuit for determining whether the output of the adder has exceeded a certain digital value; and an output of the adder from the level detection circuit that is less than the certain digital value. When an output indicating that is generated, a value substantially the same as the output of the adder is output, and an output indicating that the output of the adder is greater than or equal to the predetermined digital value is generated from the level detection circuit. a digital limiter that outputs the predetermined digital value when the level detection circuit is generating an output indicating that the output of the adder is greater than or equal to the predetermined digital value; a compensation signal forming circuit for forming a compensation signal corresponding to a value obtained by subtracting the certain digital value from the output of the limiter; a subtracter for subtracting the compensation signal from the shift signal; a first digital-to-analog converter for converting the output of the subtracter into an analog signal; a second digital-to-analog converter for converting the output of the subtracter into an analog signal; and an analog subtraction circuit for subtracting the output of the second digital to analog converter from the output. [2] A digital signal generation circuit that generates a digital signal; a shift signal generation circuit that generates a shift signal for distortion improvement in a digital format; an inversion circuit that generates an inverted signal of the digital signal; a first adder for adding shift signals; a first level detection circuit for determining whether the output of the first adder has exceeded a certain digital value; When the level detection circuit generates an output indicating that the output of the first adder is less than the certain digital value, outputs a value substantially the same as the output of the first adder; a first digital limiter that outputs the certain digital value when the first level detection circuit generates an output indicating that the output of the first adder is greater than or equal to the certain digital value; Corresponding to when the first level detection circuit generates an output indicating that the output of the first adder is greater than or equal to the predetermined digital value, a first compensating signal forming circuit for forming a first compensating signal corresponding to a value obtained by subtracting the digital value of , and a second compensating signal forming circuit for adding the shift signal to the inverted digital signal obtained from the inverting circuit. an adder; a second level detection circuit for determining whether the output of the second adder exceeds a certain digital value; and a signal from the second level detection circuit to the second adder. When an output indicating that the output of the adder is less than the predetermined digital value is generated, substantially the same value as the output of the second adder is output, and the second level detecting circuit outputs the adder. a second digital limiter that outputs the certain digital value when an output indicating that the output of the device is greater than or equal to the certain digital value; and a second digital limiter that outputs the certain digital value from the second level detection circuit; A second adder corresponding to a value obtained by subtracting the certain digital value from the output of the second adder in response to an output indicating that the output of the adder is greater than or equal to the certain digital value. a second compensation signal forming circuit for forming a compensation signal; a first subtracter for subtracting the second compensation signal from the output of the first digital limiter; and the second digital limiter. a second subtracter for subtracting the first compensation signal from the output of the subtractor; a first digital-to-analog converter for converting the output of the first subtracter into an analog signal; a second digital-to-analog converter for converting the output of the second subtractor into an analog signal; and subtracting the output of the second digital-to-analog converter from the output of the first digital-to-analog converter. A digital-to-analog conversion device consisting of an analog subtraction circuit for