JPH0644711B2 - Analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention involves adding and subtracting an analog signal such as an audio signal to a dither signal in a DAT (digital audio tape recorder) or the like. The present invention relates to an analog-digital conversion device for converting a digital signal into a digital signal.

[Prior Art] Quantization noise (difference between quantized output and input sample value) becomes a problem in PCM recording / reproduction of an audio signal. Especially, when the input signal level is low and the number of quantization steps is small, the quantization noise has a strong correlation with the input, and becomes a kind of distortion (higher harmonic) of the input signal rather than noise. Also,
Even if the input signal level is high, an unpleasant noise is generated every time the quantization step changes for a signal that changes very slowly. In addition, there are variations in the quantization step of the analog-digital (A / D) converter itself, and the A / D
Non-linear distortion occurs during conversion. In order to solve the above problems, it is known to add white noise called dither to an input signal for A / D conversion, and then subtract the dither.

[Problems to be Solved by the Invention] When an analog dither is added to the analog information signal, this added value may be larger than the maximum allowable input level of the A / D converter. If an adder and an A / D converter that match the maximum value of the dither addition information signal are prepared, no problem will occur, but the cost of the adder and the A / D converter will increase. On the other hand, if the output of the adder and the input of the A / D converter are limited to constant values, the dynamic range of the analog information signal is narrowed by the amount of dither.

In order to solve the above problems, there is a method of stopping the addition of dither when the input analog information level is high.
No. 2-13142. Further, Japanese Patent Application No. 61-176980 proposes to control the level of an analog dither. According to these methods, the added value of the information signal and the dither is prevented from exceeding a predetermined value. However, the configuration becomes relatively complicated.

Therefore, an object of the present invention is to provide an analog-digital conversion device that can relatively easily solve the problem of large amplitude input.

[Means for Solving the Problems] To achieve the above object, the present invention provides an input circuit for supplying an analog information signal with a variable resistor for adjusting the level of the analog information signal, and an analog dither. A signal generating means, an adding means for adding an analog dither signal generated by the analog dither signal generating means to the analog information signal supplied from the input circuit; and an analog dither addition information signal obtained by the adding means. A digital dither addition information signal corresponding to this is converted, which has an allowable maximum input level larger than the maximum level of the analog dither signal and is supplied with an input equal to or higher than the allowable maximum input level. An analog-to-digital circuit, sometimes configured to produce an output corresponding to a signal truncated above the maximum allowable input level. Digital converter, a subtraction circuit for subtracting the digital dither signal corresponding to the analog dither signal from the digital dither addition information signal, and the analog above the allowable maximum input level (+ L) of the analog-digital converter. The detection level (L1) on the plus side corresponding to the analog level lower by the same or almost the same level as the dither signal level and the allowable small input level of the analog-digital converter (the maximum allowable input level on the negative side). The negative detection level (L) corresponding to an analog level that is higher than or equal to the level of the analog dither signal.
2) and a level detection circuit for detecting whether or not the output of the subtraction circuit reaches at least one of the above, and the detection level of the output of the subtraction circuit on the plus side and / or the minus side by the level detection circuit. A limiter for limiting the output to the positive side and / or the negative side detection level in response to being detected to have reached
And a display connected to the level detection circuit and providing a display corresponding to the output of the level detection circuit indicating that the output of the subtraction circuit has reached the detection level on the plus side and / or the minus side. The present invention relates to an analog-digital conversion device.

[Operations and Effects of Invention] The present invention has the following operations and effects.

(B) When the analog-digital converter overflows, an output clipped to a constant value is generated. The clipped output is input to the subtraction circuit, and when the digital dither is subtracted from this, a signal including a variation due to the digital dither is generated. If this signal is output as it is, the dither component remains as noise. However, according to the present invention, a limiter circuit is provided at the output stage of the subtraction circuit, and when the overflow occurs, the output of the subtraction circuit is not sent as it is, but the signal limited by the limiter is sent out. It is possible to prevent generation of noise due to operation.

(B) Since the display device is provided, the operation of the limiter circuit can be monitored and appropriate analog-digital conversion can be performed.

[Embodiment] Next, a DAT A / D converter according to an embodiment of the present invention will be described with reference to FIGS. An A / D converter for converting an analog information signal composed of an audio signal shown in FIG. 1 into a digital signal (PCM signal),
Input terminal 1, first amplifier 2, level adjustment variable resistor 3,
Low-pass filter 4, second amplifier 5, sample and hold (SH) circuit 6, dither adder 7, buffer amplifier 8, A / D converter 9, dither subtraction circuit 10, limiter 11, multiplexer 12, and digital Filter 1
3 includes a circuit in which 3 is connected in this order.

The variable resistor 3 provided before the adder 7 adjusts the level of the analog information signal A1 given from the sample hold circuit 6 to the adder 7.

The low pass filter 4 is configured to pass an audio signal of 0 to 20 kHz.

The sample hold circuit 6 samples the information signal A1 at a constant frequency (for example, 88.2 kHz), holds the sample obtained by this, and outputs the sample. This output terminal is one input of the analog adder 7. It is connected to the terminal.

Reference numeral 14 is a dither generation circuit, which includes a 16-bit digital dither generator 15 and a 16-bit D / A converter 16
The digital dither generator 15 including the variable resistors 17 and 18 for adjusting the dither level and the digital level reducing circuit 19 outputs a 16-bit digital signal substantially randomly at the sampling frequency of the sample and hold circuit 6 (for example, 88.2 kHz] and M sequences (Maximal-length Pulse Sequences) generated at the same sampling frequency.
) It consists of a pseudo-random pulse generator and outputs substantially the same as the analog white noise converted into a digital signal. The D / A converter 16 connected to the digital dither generator 15 converts the 16-bit digital dither into an analog dither signal corresponding thereto.
Despite the fact that the subtraction circuit 10 substantially requests a dither signal of a 10-bit level, both the dither generator 15 and the D / A converter 16 have a 16-bit configuration, so that a highly accurate analog dither is provided. Can be obtained. D
The dither level adjusting resistor 17 connected between the A / A converter 16 and the input terminal of the adder 7 adjusts the level of the analog dither signal B1 so as to correspond to the digital dither signal of 10-bit level. Is given to the adder 7.

The digital level reduction circuit 19 connected to the digital dither generator 15 converts the 16-bit digital dither signal into a digital dither signal B2 having a change range of 10 bits.
And is composed of a D-type flip-flop. For example, if the positive-polarity 16-bit digital dither signal is [0101101100101110], 10 bits from MSB to 10SB are shifted from 7SB to LSB, and a digital dither with 6 0s added to the upper bits. The signal [0000000101101100] is formed and output. If the negative 16-bit digital dither signal is [10111100111001001], the 10 bits from MSB to 10SB are shifted from 7SB to LSB, and the 6 higher 1s are shifted.
A digital dither signal [1111111011100111] with is added is formed and output.

The adder 7 is preferably an analog information signal A1 having a plus peak and a minus peak of about 3V or less, respectively, which is supplied from the sample and hold circuit 6, and 0V to -9.
An analog dither addition information signal (A1 + B1) is formed by adding the analog dither signal B1 adjusted so that one peak and the other peak are located in the range of 3.6 mV. FIG. 3 shows the analog information signal A1, the analog dither signal B1, and the analog dither addition information signal A1 + B1.
And is shown in principle. Each signal is shown with a large amplitude, but of course the amplitude will vary.

The A / D converter 9 is made of PCM-779, for example, and has an allowable input range of + 3V to -3V. From the A / D converter 9, an analog input, that is, a 16-bit digital output corresponding to the analog dither addition information signal A1 + B1, that is, a digital dither addition information signal A2 + B2 is obtained. Even if the A / D converter 9 has variations in quantization step and generates non-linear distortion at the time of A / D conversion, the non-linear distortion is added by adding dither to perform A / D conversion. It can be reduced.

The digital subtraction circuit 10, one input terminal of which is connected to the A / D converter 9 and the other input terminal of which is connected to the digital level reduction circuit 19, substantially outputs from the 16-bit digital dither addition information signal A2 + B2. The 10-bit level digital dither signal B2 is subtracted, and ideally only the digital information signal A2 is output. Since the digital dither signal B2 input to the subtraction circuit 10 is in the same sampling period as the added analog dither signal B1, ideally, the digital component corresponding to the added analog dither signal B1 is completely removed. To be done. If the dither level is extremely low, there may be no problem even if the dither is not subtracted.However, if the dither level is high as in this embodiment, the dither will be noisy unless it is subtracted. become.

By the way, the level of the analog dither addition information signal A1 + B1 is the allowable input level of the A / D converter 9 + 3V to -3V.
Within the range, the effect of dither addition and subtraction can be satisfactorily obtained. However, the level of the input signal of the A / D converter 9 may exceed the allowable maximum input level ± 3V. FIG. 2 shows the analog input and output of the A / D converter 9 and the output of the subtractor 10.
FIG. 2A shows the maximum allowable input level L of the A / D converter 9.
The analog information signal A1 having a peak corresponding to Thus, the analog information signal A1 having a high peak level
When the analog dither signal B1 is added to
The analog dither addition information signal A1 + B1 has a portion exceeding the maximum allowable input level L as shown in FIG. A / D
Since the converter 9 cannot perform A / D conversion on a portion having a maximum allowable input level L or higher, an output in a state in which the level L or higher is truncated is generated. That is, the analog dither signal B1
An A / D conversion output that does not include the digital dither component corresponding to is obtained. When the dither signal B2 is subtracted from the portion not including the dither in the subtraction circuit 10, FIG.
A subtraction output including a dither is obtained as shown in analog form in FIG. If it is output as it is, the dither component becomes noise and an unpleasant sound is generated.
As shown in FIG. 3D, the limiter 11 removes the dither component to obtain an output. Further, the display 20 indicates that the level at which the distortion is generated is reached, and the user is informed that the input level is excessive.

A level detection circuit 21 is provided to operate the limiter 11 and the display 20. The level detection circuit 21 has a plus-side overflow level detection circuit 22 and a minus-side overflow level detection circuit 23 connected to the output of the subtraction circuit 10, and these outputs are displayed as a limiter 11 via an OR gate 24. Connected to the container 20. In this embodiment, the analog dither signal B1 is set in the range of 0 to -93.6 mV as described with reference to FIG. Therefore, when the analog dither signal B1 is added to the analog information signal A1 in FIG. 3, one envelope of the analog dither addition information signal A1 + B1 coincides with the analog information signal A1 and the other envelope is at the position shown by the dotted line. . Therefore, the amplitude of A1 + B1 changes between the solid line and the dotted line. As a result, on the plus side, A / D
The signal A1 + B1 obtained by adding the dither signal B1 to the analog information signal A1 having a level matching the plus maximum input level + L of the converter 9 does not exceed the plus maximum input level + L of A / D conversion. Therefore, this signal A1 + B1
There is no problem even if the digital dither signal B2 is subtracted after the / D conversion. Therefore, the detection level L1 of the plus side overflow level detection circuit 22 in FIG.
It is set to the plus allowable maximum input level + L of the D converter 9. Since the A / D converter 9 outputs a digital signal in the form of 2's complement, the maximum positive output is [0111111111111111]. Therefore, the plus-side overflow level detection circuit 22 is configured to invert the MSB of the input digital signal and input it to the AND gate without inverting the other. As a result, when a signal of level L1 is input to the plus side overflow detection circuit 22, a high level output is generated and given to the limiter 11 and the display 20. Since the analog input of the detection level L1 or more causes the output to be distorted, when the display 20 indicates the overflow, the variable resistor 3 lowers the input level.

On the other hand, the minus side overflow level detection circuit 23
Has a negative side overflow detection level L2 having an absolute value lower by a dither level (93.6 mV) than the negative side allowable maximum input level -L (allowable minimum level) of the A / D converter 9 shown in FIG. Is set. The maximum allowable input level L1 for negative output is 1
It is a 6-bit two's complement number [1000000000000000], and the minus side overflow detection level L2 is lower than this, that is, the dither signal level, that is, 93.6 mV (about 0.1
4 dB) and is set high (low in the absolute value on the negative side). The digital value of the minus side overflow detection level L2 can be represented by, for example, [100000XXX ......... XX]. However, x is 1 or 0 here. The minus side overflow detection circuit 23 is also composed of a logic circuit. When the input digital signal matches the digital value of the minus side overflow detection level L2, a high level output is generated, and the limiter 1 is supplied via the OR gate 24.
1 and display 20.

The limiter 11 is configured to continuously output the value of the overflow level L1 or L2 corresponding to the output (high level) indicating the overflow generated from the level detection circuit 21 only during the overflow period. As a result, the variation (noise) due to the dither is not output, the data as shown in principle in FIG. 2 (D) is output, and unpleasant noise is reduced. Since waveform distortion occurs when the limiter 11 works, the input level is adjusted by the variable resistor 3 as much as possible to prevent overflow.

The display 20 is connected to the level detection circuit 21 and indicates that the signal has reached the overflow detection levels L1 and L2. This indicator 20 is A for the signal on the minus side.
Since it does not respond to the maximum value (absolute value) of the allowable input on the minus side of the / D converter 9 and overflow is displayed in response to a signal exceeding the detection level L2 lower by the dither level than this to the minus side, The signal level can be adjusted accurately.

Since DAT has a left channel and a right channel,
Left channel input terminal 1 as well as right channel input terminal 2
5 and the right channel A / D converter 26, and the output lines of both channels are connected to the multiplexer 12. The output of the multiplexer 12 is the digital filter 1
3 to a recording circuit (not shown).

In the example of FIG. 3, the analog dither signal B1 is 0 to -9.
Although it is generated on the minus side of 3.6 mV, it may be generated on the plus side of 0 to +93.6 mV as shown in FIG. In this case, the level of A1 + B1 is A
Since it becomes higher than 1, the overflow detection level L1 on the plus side is set to the maximum allowable input level of the A / D converter 9
93.6 mV, or about 0.14 dB lower,
On the other hand, the minus side overflow detection level L2 is −
Match L.

Further, as shown in FIG. 5, the dither signal is changed from -46.8 mV to
It can also be generated in the range of +46.8 mV. In this case, the plus side overflow detection level L1 is set smaller than the plus allowable maximum input level + L, and the minus side overflow detection level L2 is set smaller than the minus side allowable maximum input level.

By the way, as shown in FIG. 3 or FIG.
Is biased, distortion when the amplitude of the analog information signal A1 becomes low level can be reduced. That is,
In FIG. 3, 0 to −9 is applied to the analog information signal A1 having a small amplitude.
Even if the dither signal B1 of 3.6 mV is added, the amplitude of the information signal A1 is A during the negative period (half cycle).
1 + B1 never crosses the zero level. On the other hand, A1 + B1 may cross the zero level in the period in which the amplitude of the information signal A1 is positive, the quantization is performed on both the positive side and the negative side, and the error, that is, the distortion may increase. Therefore, if the method of FIG. 3 or FIG. 4 is adopted, the probability of zero crossing is half that of the method of FIG.
Distortion can be reduced.

[Another embodiment] Next, an A / D according to another embodiment of the present invention shown in FIG.
The conversion method will be described. However, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 6, both A1 + B1 and B1 are A / D converted by one A / D converter 9 in order to reduce cost and prevent generation of a subtraction error based on the A / D conversion error. There is. For this purpose, a multiplexing gate circuit 31 is provided between the sample hold circuit 6 and the adder 7. The gate circuit 31 extracts the analog information signal A1 in a part of one sampling period and uses it as one input of the adder 7. Since the analog dither signal B1 is always output to the other input terminal of the adder 7, the output of A1 + B1 is obtained during the period when the analog information signal A1 is input, and the output of B1 is during the other period. Is obtained. The A / D converter 9 time-divisionally A / D-converts A1 + B1 and B1. Branch line memory 32 of output of A / D converter 9
Selectively reads the digital dither signal B2 corresponding to B1 and reads it in synchronization with the output period of A2 + B2.
As a result, the output of A2 + B2-B2 = A2 from the subtraction circuit 1 is obtained. Since the data in the period in which B2 is not output from the memory 32 is unnecessary, only A2 is extracted by the sampling gate 33 connected to the output line of the subtraction circuit 10. The method of time division multiplexing processing in FIG. 5 is substantially the same as the method disclosed in Japanese Patent Laid-Open No. 62-13124.

In the case of FIG. 6, since it is not necessary to directly send the digital dither signal from the dither generation circuit 14 to the subtraction circuit 10,
The digital level reduction circuit 19 of FIG. 1 is unnecessary,
The dither generation circuit 14 is composed of a digital dither generation circuit 15, a D / A converter 16 and each variable resistor 17.

[Brief description of drawings]

FIG. 1 is a block diagram showing a DAT A / D converter according to an embodiment of the present invention, and FIG. 2 shows a problem caused by adding a dither signal to a large-amplitude analog information signal and a method for solving the problem. FIG. 3 is a waveform diagram for explaining, FIG. 3, FIG. 4 and FIG. 5 are waveform diagrams for explaining changes in the overflow detection level when the position of the analog dither signal is changed, and FIG. It is a block diagram which shows the A / D conversion device of another Example. 7 ... Adder, 9 ... A / D converter, 10 ... Subtraction circuit, 11 ... Limiter, 14 ... Dither generation circuit, 15
...... Digital dither generator, 16 …… D / A converter,
20 ... Display unit, 21 ... Level detection circuit.

Claims (1)

[Claims] 1. An input circuit for supplying an analog information signal having a variable resistor for adjusting the level of the analog information signal, an analog dither signal generating means, and an analog information signal supplied from the input circuit. An adder for adding the analog dither signals generated by the analog dither signal generator, and an analog dither addition information signal obtained by the adder for conversion into a corresponding digital dither addition information signal. And has a maximum allowable input level larger than the maximum level of the analog dither signal, and when an input exceeding the maximum allowable input level is supplied, it corresponds to a signal in which the portion exceeding the maximum allowable input level is truncated. An analog-to-digital converter configured to generate an output, the digital dither summing information signal A subtraction circuit for subtracting a digital dither signal corresponding to the analog dither signal, and a level which is the same as or almost the same as the level of the analog dither signal than the maximum allowable input level (+ L) of the analog-digital converter The level of the analog dither signal is the same as or substantially the same as the positive detection level (L1) corresponding to the low analog level and the allowable minimum input level of the analog-digital converter (negative maximum allowable input level). A level detection circuit for detecting whether or not the output of the subtraction circuit reaches at least one of the negative detection level (L2) corresponding to the analog level higher by the level; and the subtraction circuit by the level detection circuit. It is detected that the output of has reached the detection level on the plus side and / or the minus side. And a limiter that limits the output to the plus and / or minus detection levels in response to the output of the subtraction circuit, and the output of the subtraction circuit is connected to the plus and / or minus side. An analog-to-digital conversion device, comprising: a display corresponding to the output of the level detection circuit indicating that the detection level has been reached.