JPH07107979B2 - Digital-to-analog converter - Google Patents

Description

The present invention relates to converting a digital information signal corresponding to an analog signal such as an audio signal into an analog signal with addition and subtraction of dither. Digital-
More specifically, the present invention relates to an analog (D / A) conversion device, and a D / A converter having a level adjustment device for surely performing dither subtraction.
A conversion device.

[Conventional technology]

If the linearity of the relationship between the input and output of the D / A converter is poor, waveform distortion will occur and harmonic noise will occur. In order to reduce the noise due to the non-linearity of the D / A converter, the digital dither is added to the digital information signal (data) input to the D / A converter, D / A conversion is performed, and then analog A method of removing (subtracting) the dither component included in the signal is already known. By adding dithers according to this method, when digital information signals that repeatedly output the same analog waveform are input repeatedly, the same operation is performed even if the same digital information signal is repeatedly D / A converted. However, the averaging of the non-linear distortion occurs, and the generation of jarring noise due to the non-linear distortion is reduced.

[Problems to be solved by the invention]

By the way, when the digital information signal is zero,
In principle, when the digital dither is generated, the output of the subtractor should also become zero. However, the difference between the signal transmission system that D / A converts the digital dither addition information signal and inputs it to the subtractor and the signal transmission system that D / A converts the digital dither and inputs it to the subtractor, and analog subtraction The dither does not become zero at the subtractor output stage due to the subtraction error in the subtractor. Therefore, it is necessary to connect a variable resistor to the input line of the subtractor to adjust the gain so that the dither at the output stage of the subtractor becomes zero. However, this adjustment was very troublesome. Further, even if the dither subtraction error is adjusted to be zero, the problem of temperature drift due to the variable resistor remains.

Therefore, it is an object of the present invention to provide a digital-analog conversion device capable of highly accurate automatic adjustment of a dither level.

[Means for Solving the Problems] To achieve the above object, the present invention provides a digital information signal input circuit, a digital dither generator, the digital information signal supplied from the input circuit, and the digital dither. An adder for adding a digital dither supplied from a generator to obtain a digital dither addition information signal; a multiplier for multiplying the digital dither obtained by the digital dither generator by a coefficient; and an adder obtained by the adder. A digital-analog conversion means for converting the digital dither addition information signal and the digital dither obtained from the multiplier into analog signals individually or by time division multiplexing to obtain an analog dither addition information signal and an analog dither. And the analog dither addition information signal obtained from the digital-analog conversion means. A subtractor for subtracting the analog dither from a signal, a clock signal generator, and a counter having a latch function, the counter for multiplying in the multiplier by counting the clock signal generated from the clock signal generator. A coefficient unit for generating a coefficient and supplying it to the multiplier, and an analog dither level supplied to the subtractor are adjusted so that the output of the subtractor becomes zero when the level of the digital information signal is zero. Occasionally, reset means for resetting the counter to start counting the clock signal by the counter, and a zero-cross point at which the output level of the subtractor becomes zero when adjusting the level of the analog dither are detected. , A zero-cross detection circuit that supplies the detection signal at the time of this zero-cross to the coefficient unit. The coefficient unit latches the output of the counter in response to the detection signal at the time of the zero cross supplied from the zero cross detection circuit, and supplies the latched output to the multiplier as the coefficient. The present invention relates to a digital-analog conversion device characterized in that

[Operation] In the above invention, the level of the dither used for the subtraction is adjusted at the stage of the digital dither. Therefore, highly accurate adjustment can be easily performed. Further, since the level-adjusted digital dither value is substantially unaffected by temperature, the drift due to the variable resistance can be reduced.

〔Example〕

Next, a D / A for converting a digitalized audio signal according to the embodiment of the present invention shown in FIG. 1 into an analog signal.
The conversion device will be described. This D / A converter is 16 words per word.
Bit offset binary code (offset binar
It has an input circuit (1) for inputting a digital information signal (data) having a configuration of y code) in parallel form, which is connected to a digital adder (2). The information signal (X) is input from the input circuit (1) at a sampling repetition frequency of 88.2 kHz, for example.

(3) is a digital dither generator, which produces a 12-bit binary digital signal substantially at the same time as the data.
This circuit is generated at a sampling frequency of 88.2kHz.
This dither generator (3) is an M-sequence (Maximal-length P
ulsc Sequencec) consists of a pseudo-random pulse generator circuit, which is substantially the same as analog white noise converted into a digital signal, and is transmitted in synchronization with data.

The adder (2) connected to the 16-bit data input circuit (1) and the dither generator (3) has a 16-bit information signal (X) input in parallel and a 12-bit dither (Y) input in parallel. ) Is added in bit units to output a 16-bit digital dither addition information signal of X + Y.

The first D / A converter (4) connected to the output of the adder (2) is, for example, PCM53JP- which is an IC manufactured by Burr Brown Co.
It has a 16-bit input terminal and is D / A converted to the digital dither addition information signal (X + Y) and supplies the analog dither addition information signal (X '+ Y') to the subtractor (5). To do.

(6) is a dither level adjusting circuit provided according to the present invention, which is connected to the dither generator (3). This dither level adjusting circuit comprises a multiplier (7), a clock signal generator (8), and a coefficient unit (9), and adjusts the level of the digital dither (Y) to perform the second D / A conversion. It is to be sent to the container (11).

The second D / A converter (11) has the same 16-bit configuration as the first D / A converter (4), and has a multiplier (7) for level adjustment.
Is connected to a dither generator (3) via a digital dither generator (3) to convert the digital dither (Y) into an analog dither (Y ') and output it.

Since one input terminal of the subtractor (5) is connected to the first D / A converter (4) and the other input terminal is connected to the second D / A converter (11), the subtraction The device (5) subtracts the analog dither (Y ') from the analog dither addition information signal (X' + Y ') and outputs the analog information signal (X').

Sampling gate (12) connected to subtractor (5)
Is a deglitch circuit, sampling gate (13)
And a filter (14) to remove glitches. That is, the sampling gate (13) is used to sample a portion not including the glitch from the output of the subtractor (5), and the sampled portion is passed through a filter (14) to obtain a target analog output. There is.

Reference numeral (15) is a zero-cross detection circuit, which comprises a rectifying / smoothing circuit (16) connected to the output of the subtractor (5), a sample hold circuit (17) connected to the rectifying / smoothing circuit (16),
One input terminal is connected to the rectifying / smoothing circuit (16), and the other input terminal is composed of a comparator (18) made into a sample hold circuit (17). The output of the comparator (18) is connected to the control terminal of the coefficient unit (9) via the switch (19).

(Operation) Next, the operation of this D / A converter will be described. At the time of normal D / A conversion, the digital information signal (X) supplied from the input circuit (1) is added with the dither (Y) generated from the dither generator (3) by the adder (2) to obtain the digital dither. An addition information signal (X + Y) is obtained, which is converted by a first D / A converter (4) into an analog dither addition information signal (X '+ Y') and input to a subtractor (5). At the other input terminal of the subtractor (5), the digital dither (Y) obtained from the dither generator (3) is converted into an analog dither (Y ') by the second D / A converter (11). Enter. Now, the level of the digital dither (Y) is not adjusted in the level adjusting circuit (6), the output of the dither generator (3) is directly input to the second D / A converter (11), and Assuming that all circuits are operating in an ideal (zero error) state, the dither component (Y ') in the dither addition information signal at one input terminal of the subtractor (5) and the other input terminal Dither (Y ')
And have the same value, and the dither component is not included in the output of the subtracter (5). Therefore, the problem due to dither addition does not occur at all. If the dither (Y) is added for D / A conversion, harmonic distortion based on the non-linearity error of the D / A converter (4) is averaged and a jarring sound is produced, as described above. It will not occur.

When the level of the output of the subtractor (5) is adjusted to zero by the method shown in FIG. 1, the digital information signal is not output from the input circuit (1), that is, the digital information signal (X) is zero. In the stopped state, the coefficient unit (9) is reset, and the clock signal generator (8) sends a clock signal to the coefficient unit (9). The output of the coefficient unit (9) consisting of a counter is up-operated every time a clock signal is input and becomes large. Since the coefficient unit (9) is connected to the multiplier (7), the coefficient (K) and the dither (Y) are digitally multiplied in the multiplier (7). Immediately after the reset, the coefficient (K) output from the coefficient unit (9) is small, so that the output of the multiplier (7) is small and the output level of the second D / A converter (11) is also low. For this reason,
The dither (Y ') obtained from the first D / A converter (4) and the dither (K') obtained from the second D / A converter (11).
Y ') is large and the dither is output at a high level from the subtractor (5). The output of the subtractor (5) is converted into a direct current by the rectifying and smoothing circuit (16), and a direct current output corresponding to the subtraction error is obtained. The sample hold circuit (17) operates in synchronization with the clock of the clock signal generator (8) and stores the output of the rectifying / smoothing circuit (16). Therefore, the comparator (18)
The output of the rectifying / smoothing circuit (16) before one sampling period (1 clock) is compared with the current output. When the coefficient (K) obtained from the coefficient unit (9) in response to the clock signal increases, the output (KY) of the multiplier (7) also increases, and the output of the second D / A converter (11) ( K'Y ') also becomes large. Since the coefficient unit (9) is up-operating now, the output of the subtractor (5), that is, the subtraction error, gradually decreases. Therefore, the potential of the non-inverting input terminal of the comparator (18) to which the output of the sample hold circuit (17) is input becomes higher than the potential of the inverting input terminal, and the output of the comparator (18) becomes high level. . According to the output of the comparator (18), the coefficient unit (9)
In order to control the switch, the switch (19) is turned on a little later than the time when the coefficient unit (9) is reset.

By gradually increasing the coefficient (K), both inputs of the subtractor (5) substantially match, the output of the subtractor (5) becomes zero, and the coefficient (K) can be further increased. If so, the output of the subtracter (5) again increases. When the output of the subtractor (5) increases across zero, the output of the sample and hold circuit (17) becomes lower than the output of the rectifying and smoothing circuit (16), and the output of the comparator (18) switches to a low level. To do. Coefficient unit (9)
Responds to the low level output of the comparator (18) to stop the up operation and latch the coefficient at that time. Therefore, the multiplier (7) is continuously supplied with a coefficient that makes the subtraction error substantially zero.

The above-mentioned dither level adjustment may be performed every time the power is turned on by forming a reset signal in synchronization with the power-on of the compact disk player including the D / A converter, and before the shipment from the factory. The adjustment step may be performed or may be performed arbitrarily.

When the level adjustment is completed and the coefficient (K) is latched, the switch (19) is turned off to make the zero-cross detection circuit (15) irrelevant to the normal D / A conversion operation.

In the system shown in FIG. 1, since the level is adjusted at the stage of the digital dither, it becomes possible to easily and automatically perform the high precision adjustment. Further, since the adjusted coefficient is a digital value and does not change depending on the temperature, the drift can be reduced.

Next, FIG. 2 showing another embodiment of the present invention will be described. However, in FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. The D / A converter shown in FIG. 2 does not include the second D / A converter (11) shown in FIG. Instead, a time division multiplexing circuit (20) including a multiplexer is provided and the D / A converter (4) is used in time division. The time division multiplexing circuit (20) is connected to the adder (2) and the multiplier (7), and is connected to the digital dither addition information signal (X + Y) output from the adder (2) and the multiplier (7). The time-division multiplexed signal (X + Y) + (KY) with the output digital dither (KY) is formed and sent to the D / A converter (4). From the D / A converter (4), the analog time division multiplexed signal (X '+ Y') + corresponding to this input
(K'Y ') is obtained. The sample hold circuit (21) connected to the D / A converter (4) extracts and holds the analog dither (K'Y ') from the time division multiplexed signal. Since one input terminal of the subtractor (5) is connected to the D / A converter (4) and the other input terminal is connected to the sample hold circuit (21), the analog time division multiplexed signal (X ' The dither (K'Y ') can be subtracted from (X' + Y ') contained in + Y') + (K'Y '). That is, it is possible to generate an output including (X '+ Y')-(K'Y ') in a time division manner. Assuming now that the subtraction error is zero and the multiplier (7) is not provided,
From the subtracter (5), as in FIG. 1, (X '+ Y')-
A signal including (Y ') = X' in time division is obtained. Since the output of the subtractor (5) contains an unnecessary signal, the sampling gate (13) extracts only the necessary signal (X '). Rectifier smoothing circuit (16) of zero-cross detection circuit (15)
Is connected to the output of the sampling gate (13) in this example. If the coefficient (K) is ignored, the sampling gate (13) outputs (X '+ Y')-(Y '). Therefore, if the digital information signal (X) is set to zero, the dither ( Only the subtraction error of Y ') is output, and the dither level can be adjusted as in the case of FIG.

[Modification]

The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(A) In FIG. 2, the multiplexer circuit (20) is not provided on the output side of the adder (2), but a gate circuit is provided on the input side of the adder (2), and an information signal is provided by this gate circuit. (X) is extracted, the information signal (X) is input to the adder (2) with a vacant time, and the dither (Y) is added to the information signal (X) to obtain the (X + Y) signal and the (Y) signal. The time division multiplexed signal of may be formed.

(B) In the system shown in FIG. 2, (X '+ Y') may be sampled and held by the sample and hold circuit (21).

(C) The present invention is also applicable to the case where a stereo signal is input and separated into a left channel and a right channel at the output side of the adder (2).

(D) The dither generator (3) is replaced with an analog dither generator.
It may be configured in combination with a D / A converter.

(E) A latch circuit may be provided independently at the output stage of the coefficient unit (9).

(F) The zero-cross detection circuit (15) and a part of the level adjustment circuit (6) may be detachably connected and may be detached after the adjustment is completed.

(G) The coefficient (K) may be changed from a large value to a small value.

(H) The coefficient of the multiplier (7) and the subtraction ratio of the dither in the subtractor (5) are not about 1, but the coefficient in the case of FIG.
The value may be set to a value slightly smaller than 16 times, and the subtraction ratio may be set so that subtraction can be performed to enable highly accurate subtraction.

〔The invention's effect〕

 As is apparent from the above, the present invention has the following effects.

(B) Since the variable coefficient unit generates a coefficient that gradually changes in response to the clock signal, it is possible to easily give the optimum coefficient value to the multiplier.

(B) Since the detection and control means detects the optimum coefficient time point based on the output of the subtractor and fixes the coefficient value of the variable coefficient device, the setting of the optimum coefficient value can be automatically and easily achieved. .

(C) Since the analog input of the subtractor is adjusted not by using the variable resistor but by the state of the digital signal, the problem of temperature drift of the variable resistor does not occur.

[Brief description of drawings]

FIG. 1 is a block diagram showing a D / A converter of an embodiment of the present invention, and FIG. 2 is a block diagram showing a D / A converter of another embodiment of the present invention. (1) …… Data input circuit, (2) …… Adder, (3)
…… Dither generator, (4) (11) …… D / A converter,
(5) …… Subtractor, (6) …… Level adjustment circuit, (15)
...... Zero cross detection circuit.

Claims (1)

[Claims] 1. A digital dither addition circuit for adding a digital information signal input circuit, a digital dither generator, and the digital information signal supplied from the input circuit and the digital dither supplied from the digital dither generator. An adder for obtaining an information signal, a multiplier for multiplying the digital dither obtained by the digital dither generator by a coefficient, a digital dither addition information signal obtained by the adder, and a digital obtained by the multiplier Digital-analog conversion means for converting the dither and an analog signal individually or by time division multiplexing to obtain an analog dither addition information signal and analog dither; and the analog dither addition obtained from the digital-analog conversion means. A subtractor for subtracting the analog dither from the information signal; A coefficient including a clock signal generator and a counter having a latch function, the coefficient generating the coefficient for multiplication in the multiplier by counting the clock signal generated from the clock signal generator, and supplying the coefficient to the multiplier And adjusting the level of the analog dither supplied to the subtractor so that the output of the subtractor becomes zero when the level of the digital information signal is zero. Reset means for starting the counting of the clock signal, and detects the zero-cross time point when the output level of the subtractor becomes zero when adjusting the level of the analog dither, and the detection signal at this zero-cross time point is sent to the coefficient unit. And a zero cross detection circuit for supplying the zero cross detection circuit, Digital-to-analog conversion, characterized in that the output of the counter is latched in response to the supplied detection signal at the time of the zero crossing, and the latched output is supplied to the multiplier as the coefficient. apparatus.