JPH0738591B2 - Digital-to-analog converter - Google Patents

Description

The present invention relates to converting a digital signal corresponding to an analog signal such as an audio signal into an analog signal by adding and subtracting a dither digital signal. Of the digital-analog (D / A) conversion device.

[Prior Art] Quantization noise (difference between quantized output and input sample value) becomes a problem in PCM recording and reproduction of an audio signal. Especially, when the input signal level is low and the number of quantization steps is small, the quantization noise has a strong correlation with the input, and becomes a kind of distortion (higher harmonic) of the input signal rather than noise. Further, even if the input signal level is high, an unpleasant noise is generated every time the quantization step changes for a signal that changes very slowly. In order to solve the above problems, it is already known to add white noise called dither to an analog input signal and convert it into a digital signal during A / D conversion.

[Problems to be Solved by the Invention] In order to reduce the cost of the D / A converter, this D
It is desirable that the number of input bits of the / A converter be the same as or close to the number of bits (generally 16 bits) of the word of the information digital signal. However, if designed in this way, the value of the information digital signal must be suppressed by the amount of dither so that the value obtained by adding the dither digital signal to the information digital signal does not exceed the number of bits of the adder and D / A converter. did not become. Therefore, the dynamic range was inevitably narrowed. Of course, the dynamic range can be increased by increasing the number of bits of the adder and the D / A converter, but the cost of the device inevitably increases.

Also, if the digital dither addition information signal and the digital dither signal are D / A converted by different D / A converters and the analog dither is subtracted from the analog dither addition information signal, the dither cannot be sufficiently subtracted. was there.

Therefore, an object of the present invention is to provide a D / A conversion device that can obtain a wide dynamic range and can favorably perform dither subtraction.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a dither digital signal generating a dither digital signal composed of an input line of an information digital signal having a predetermined number of bits and a substantially random digital signal. A signal generator, a gate circuit for selectively transmitting the dither digital signal of the dither digital signal generator, and determining whether the information digital signal has a value of a predetermined value or more, A digital value judgment and gate control circuit for controlling the gate circuit so as to stop the transmission of the dither digital signal by a judgment output indicating that it has a value equal to or more than a predetermined value, the input line and the gate circuit Connected to the
A time division multiplex signal forming circuit for forming a time division multiplex signal of the digital dither addition information signal obtained by adding the information digital signal and the dither digital signal and the dither digital signal, and connected to the time division multiplex signal forming circuit. Is converted to an analog signal,
A digital-analog converter for obtaining an analog time division multiplexed signal including analog dither addition information corresponding to the digital dither addition information signal and analog dither for the dither digital signal, and an output of the digital-analog converter A signal including the analog dither addition information and a signal including the analog dither independently based on the analog time division multiplexed signal, and the analog dither addition information and the analog dither are obtained at the same time. And a circuit for subtracting the signal including the analog dither from the signal including the analog dither addition information.

To describe the correspondence between the present invention and the embodiments, the time division multiplex signal forming circuit is a part consisting of the gate circuit 15 and the adder 2, and the subtracting circuit is the subtracter 13, the sample hold circuit 16, and the sampling circuit. This is a part including the gate circuit 17.

[Operations and Effects of the Invention] The present invention has the following operations and effects.

(B) When the information digital signal has a large value of a predetermined value or more, the supply of the dither digital signal is stopped. Therefore, the input of the digital-analog (D / A) converter is prevented from becoming excessive, and the D / A converter does not limit the dynamic range by the dither, and the information digital signal is D / A in a wide dynamic range. Can be converted.

(B) Both the digital dither addition information signal and the dither signal are D / A converted by the same digital-analog converter. Therefore, the D / A conversion errors of both signals become substantially the same, and it becomes possible to favorably subtract the analog dither from the analog dither addition information signal. Further, when the analog dither addition information signal includes the offset voltage, the analog dither signal also includes substantially the same offset voltage. D / A conversion without any influence is possible.

[Examples] Next, examples of the present invention will be described.

A device for converting a digitized audio signal into an analog signal according to the first embodiment shown in FIG. 1 is a line 1 for inputting an information digital signal (digitized audio signal) of 1-word 16-bit structure in a parallel format. Which is connected to the digital adder 2 via the gate circuit 15. From this line 1, for example, 88.2kH
An information digital signal is input at the sampling repetition frequency of z.

A dither digital signal generator 3 is a circuit for generating a 12-bit digital signal substantially randomly. This dither digital signal generator 3 includes a 16-bit shift register 4 and three exclusive ORs as shown in FIG.
It is composed of gates 5, 6 and 7 and a NOT circuit 8. That is, the 11th stage output terminal and the 13th stage output terminal selected from the 1st to 16th stage output terminals of the shift register 4 are connected to the two input terminals of the first exclusive OR gate 5. , The output terminal of the 14th stage and the output terminal of the 16th stage are connected to the two input terminals of the second exclusive OR gate 6, and the first and second exclusive OR gates are connected.
The output terminals of the gates 5 and 6 are connected to the second exclusive OR gate 7 2
It is connected to one input terminal, and the output terminal of the third exclusive OR gate 7 is connected to the data input terminal of the shift register via the NOT circuit 8. When a clock signal of 88.2 kHz is input to the clock input terminal of this shift register, different data for each clock, that is, random pulses, are obtained at the output terminals of the 1st to 16th stages. Assuming that the number of bits of this shift register 4 is n, when 2n-1 clock pulses are input, the original state is restored. That is, the repetition period of the digital signal generated from the output terminals of the 1st to 16th stages is
A 2n-1 times the clock period is 2 ¹⁶ -1 times in this example. Since this cycle is significantly longer than the cycle of the analog signal corresponding to the information digital signal, it can be considered that the cycle has substantially no periodicity with respect to the information analog signal. The circuit of FIG. 2 has the M series (Maxima
l-lenght Pulse Sequences) A known circuit called a pseudo-random pulse generation circuit. In this embodiment, a 12-bit substantially random digital signal obtained from the output terminals of the first to twelfth stages of the shift register 4 is used as a dither digital signal. The dither digital signal is substantially the same as the analog white noise converted into the digital signal, and is transmitted in synchronization with the information digital signal.

Referring again to FIG. 1, a gate circuit 9 is provided at the output stage of the dither digital signal generator 3. The gate circuit 9 selectively passes a 12-bit dither digital signal sent in parallel form.
As shown in the figure, it is configured by connecting electronic switches S _{1 to} S ₁₂ to 12-bit dither digital signal transmission lines L _{1 to} L ₁₂ .

The digital value judgment circuit 10 of FIG. 1 is as shown in FIG.
A four-input AND gate connected to the 16-bit information signal transmission line A ₁ upper four bits of the line A ₁₃ to A ₁₆ of the to A _12. Therefore, the output of the AND gate becomes the high level only when all of the upper 4 bits are at the high level, that is, "1", which indicates that the information digital signal is the predetermined value [111100 ... 0] or more. Become. The output terminal of the AND gate is connected to the control terminals of the switches S _{1 to} S ₁₂ of the gate circuit 9, and the switches S _{1 to} S ₁₂ are turned off when the value is equal to or more than a predetermined value, and the other terminals are turned on.

The output of gate circuit 9 is coupled to the input of digital adder 2. Therefore, the adder 2 digitally adds the 16-bit information digital signal and the 12-bit dither digital signal, and outputs a 16-bit addition output. Since the gate circuit 15 transmits the information digital signal by time division, the adder 2 outputs the digital dither addition information signal and the dither signal by time division multiplexing.

The first D / A converter 11 is composed of PCM53JP-V which is an IC manufactured by Burr Brown Co. This D / A converter 11 has a 16-bit digital input terminal, is connected to the output of the adder 2, and outputs the 16-bit digital time-division multiplexed signal obtained from the adder 2 to the built-in ladder resistor. Converted to analog time-division multiplexed signals by a circuit network.

As a circuit for subtracting the dither analog signal from the dither addition information analog signal included in the analog time division multiplexed signal, an analog subtractor 13, a sample hold circuit 16, a sampling gate circuit 17, and a filter 19 are provided. There is. One input terminal of the subtractor 13 is a D / A converter 11
The other input terminal is connected to the sample and hold circuit 16
Is connected to the D / A converter 11 via. The sampling gate circuit 17, the filter 19 and the output stage of the subtracter 13 are sequentially connected. The control circuit 18 is connected to the dither digital signal generator 3, the gate circuit 15, the sample hold circuit 16, and the sampling gate circuit 17, and controls each part as shown in FIG.

[Operation] Next, the operation of the circuit shown in FIG. 1 will be described.

A 16-bit information digital signal is input from line 1 at a constant sampling period, and a 12-bit dither digital signal is output from dither digital signal generator 3 at the same sampling period as the information digital signal.
If all the upper 4 bits of the 16-bit information digital signal on the input line 1 are not "1", even if the 12-bit dither digital signal has the maximum value, these added values do not exceed 16 bits. Therefore, the addition by the adder 2 is normally performed, the 16-bit addition output is input to the 16-bit D / A converter 11, and the normal D / A conversion operation is performed.

On the other hand, when all the high-order bits of the 16-bit information digital signal become "1", the added value of the information digital signal and the dither digital signal may exceed 16 bits. If the adder 2 and the D / A converter 11 have a capacity of 17 bits or more, it is possible to process even if it exceeds 16 bits.
However, in this embodiment, the adder 2 and the D / A converter 11 have only 16-bit processing capability for cost reduction. Therefore, when the digital value judgment circuit 10 detects that all of the upper 4 bits of the information digital signal are "1", the gate circuit 9 is in the signal transmission cutoff state, and the adder 2 of the dither digital signal and the second D signal. The supply to the / A converter 12 is stopped. Therefore, all the inputs of the dither digital signal in the adder 2 become "0", and the information digital signal becomes the output of the adder 2 as it is.

The D / A converter 11 converts the information digital signal to which the dither digital signal has not been added into an analog signal. However, when the digital value is large, the unpleasant noise due to the quantization is extremely small. Also, the gate circuit 9
The dither digital signal supply stop time due to is relatively short, so even if dither addition and subtraction are not performed, D / A
The conversion characteristics are not significantly deteriorated.

When the dither digital signal is cut off by the gate circuit 9, neither addition nor subtraction is performed, so that only the information digital signal is D / A converted and output as it is. Blocking the dither with the gate circuit 9 means D /
This means that all 16 bits of the A converter 11 can be used in the information digital signal, and the dynamic range is widened. According to this D / A conversion method, an audio signal of DC to about 20 kHz can be satisfactorily obtained.

Next, the dither addition and subtraction will be described in detail with reference to FIG. An information digital signal (digitized audio signal) is input to the input line 1 at every sampling period (T) as shown in FIG. 4 (A), and the dither digital signal generator 3 is shown in FIG. 4 (B). As described above, the dither digital signal (pseudo random pulse) is generated every sampling period (T). If the value of the information digital signal is now small, the gate circuit 9 is kept in the ON state, and the dither digital signal is input to the adder 2 without restriction.
On the other hand, the sampling gate circuit 15 connected to the input line 1 is controlled by the control circuit 18, and as shown in FIG. 4 (C), the output time of one sample of the original information digital signal (in FIG. For ease of illustration, the sampling period and the one-sample output time are shown to be the same) are turned on at time T ₁ , which is a time division, and the information digital signal is generated at the timing shown in FIG. 4 (C). To the digital adder 2. In the adder 2, the dither digital signal of FIG. 4 (B) and the information digital signal of FIG. 4 (C) are added in parallel, and the addition output of FIG. 4 (D) is obtained. As is clear from FIG. 4 (D), the original 1
The sample output time is time-shared, and in the latter half,
An output (A + B) obtained by adding the dither digital signal B to the information digital signal A is obtained, and the dither digital signal B is obtained in the first half. That is, the A + B signal and the B signal are time-divided and alternately obtained.

Since the adder output of FIG. 4D is input to the D / A converter 11 as it is, an analog signal corresponding to FIG. 4D is obtained at this output terminal. The output terminal of the D / A converter 11 is connected to one input terminal of the subtractor 13 and is also connected to the sample hold circuit 16, and the output terminal of the sample hold circuit 16 is the other input terminal of the subtractor 13. 4D, the analog signal corresponding to the output of the adder in FIG. 4D is directly input to the subtractor 13, and the dither analog signal extracted and held by the sample hold circuit 16 is input. The sampling timing of the sample hold circuit 16 is as shown in FIG. 4 (E), the extraction gate is opened corresponding to the dither output period in FIG. 4 (D), and the sample (dither analog signal) is taken in. . Then, the extracted dither analog signal is held until the next sampling is performed and becomes the input of the subtractor 13. Therefore, the other input terminal (-) of the subtractor 13
A dither analog signal is always input to. Therefore, consist t ₅ ~t ₇ analog signals sent the incoming information + dither period to allow subtraction of the dither analog signal. Since the time division processing is performed, the information + dither analog signal is not always input to the subtractor 13. For this reason, the dither analog signal comrades are also subtracted during the period of t ₁ to t ₄ . Therefore, an analog signal including an unnecessary signal is obtained from the output terminal of the subtractor 13. Therefore, the sampling gate circuit 17
To extract only the required signals. FIG. 4F shows the timing of sampling in the sampling gate circuit 17. When information + dither analog signal is a gate to the ON state in the period of t ₅ ~t ₆ which is set within the period of t ₄ ~t ₇ are input to the subtractor 13, (information) + (dither) - ( The dither) or information signal is extracted. Since the information analog signal is intermittently output from the sampling gate circuit 17, the intermittent portion is interpolated through the low-pass filter 19,
Get full information analog output. Since the sampling gate circuit 17 extracts the information analog signal except for the portion including the glitch in the analog signal sequence, the analog signal with less noise is finally obtained.

In this time division method, both the information + dither digital signal and the dither digital signal are converted by the same D / A converter 11. Therefore, the D / A conversion error is also the same, and there is no problem that the dither subtraction cannot be sufficiently performed due to the difference in the D / A conversion error. Therefore, there is less noise
D / A conversion becomes possible. Also, in this method, the D / A converter
11 offset voltages can be removed. That is, D /
Even if the information + dither analog signal as the output of the A converter 11 includes the offset voltage V ₀ , the dither analog signal also includes the offset voltage V ₀ . Therefore, the subtractor 13
When the difference between the two is calculated with, the offset voltage V ₀ is canceled and removed.

Incidentally, there is no problem even if only the transmission time of the information signal A in the input line 1 shown in FIG. 4 (A) to t ₄ ~t ₇ period of one sampling period T. Therefore, another channel (for example, left or right data of a stereo signal) may be transmitted during the period of t ₁ to t ₄ .

[Modification] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(A) The dither digital signal generator 3 may be composed of an analog dither generator and an A / D converter connected to this output, instead of being composed of the M-sequence pseudo random pulse generation circuit.

(B) In the circuit of FIG. 1, a digital value judgment circuit
A circuit corresponding to the delays of 10 and the gate circuit 9 may be provided in the circuit which gives the dither digital signal.

(C) The sampling gate circuit 17 is moved to the input side of the subtractor 13, and the information + dither analog signal is extracted to obtain the subtractor 13
May be input to subtract the dither.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a D / A conversion device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the dither digital signal generator of FIG. 1, and FIG. FIG. 1 is a circuit diagram showing the digital value judging circuit and the gate circuit of FIG. 1, and FIG. 4 is a diagram showing the time relation of each part of FIG. 1 ... Input line, 2 ... Adder, 3 ... Dither digital signal generator, 9 ... Gate circuit, 10 ... Digital value judgment circuit, 11 ... D / A converter, 13 ... Subtractor.

Claims (1)

[Claims] 1. An input line of an information digital signal having a predetermined number of bits, a dither digital signal generator for generating a dither digital signal consisting of substantially random digital signals, and the dither digital signal of the dither digital signal generator. A gate circuit for selectively sending the information digital signal, and a determination output indicating whether or not the information digital signal has a value greater than or equal to a predetermined value, and a determination output indicating that the information digital signal has a value greater than or equal to the predetermined value. A digital value determination and gate control circuit for controlling the gate circuit so as to stop the transmission of the dither digital signal, and the input digital line and the gate circuit are connected to add the information digital signal and the dither digital signal. The time-division multiplexed signal of the digital dither addition information signal and the dither digital signal A time division multiplex signal forming circuit for forming, and an analog dither addition information corresponding to the digital dither addition information signal, which is connected to the time division multiplex signal forming circuit, converts the time division multiplex signal into an analog signal, and Digital for obtaining analog time division multiplexed signal including analog dither to dither digital signal −
An analog converter, connected to an output terminal of the digital-analog converter, independently obtains a signal including the analog dither addition information and a signal including the analog dither based on the analog time division multiplex signal, and A circuit for arranging analog dither addition information and the analog dither at the same time, and subtracting the signal including the analog dither from the signal including the analog dither addition information.