JPH0810828B2 - Digital-analog converter - Google Patents

Description

The present invention relates to a digital information signal corresponding to an analog signal such as an audio signal, which is analogized by addition of dither or addition and operation of dither. The present invention relates to a digital-analog (D / A) conversion device for converting a signal.

[Conventional technology]

Quantization noise (difference between quantized output and input sample value) becomes a problem in PCM recording and reproduction of audio signals.
Especially, when the input signal level is low and the number of quantization steps is small, the quantization noise has a strong correlation with the input, and becomes a kind of distortion (higher harmonic) of the input signal rather than noise. Further, even if the input signal level is high, an unpleasant noise is generated every time the quantization step changes for a signal that changes extremely slowly. In order to solve the above problems, at the time of A / D conversion, white noise called dither is added to an analog input signal and converted into a digital signal,
Alternatively, add the dither to the analog input signal, convert it to a digital signal, and then subtract the digital dither signal corresponding to this dither, or add the digital dither signal to the digital signal during D / A conversion. hand
It is already known to perform D / A conversion or to subtract an analog dither signal corresponding to a digital dither signal from the D / A conversion output after this D / A conversion.

[Problems to be solved by the invention]

By the way, when a digital dither is added to the digital information signal (data), this added value may be larger than the maximum allowable input level of the D / A converter. If an adder and a D / A converter suitable for the maximum digit of the data + dither signal are prepared, no problem will occur, but the cost of the adder and the A / D converter will increase. On the other hand, if the number of input bits (maximum input digit) of the adder and D / A converter is limited to a fixed value (for example, 16 bits), the data level must be limited to the range where the adder does not overflow during dither addition. Inevitably, the dynamic range of D / A conversion becomes narrower.

In order to solve the above problems, the applicant of the present application has proposed a method of stopping the addition of dither when the level of input data is high in Japanese Patent Application No. 60-150566. According to this method, it is possible to prevent the added value of the data and the dither from exceeding a predetermined number of bits. However, the effect of dither addition and subtraction cannot be obtained during the blocking period.

Therefore, it is an object of the present invention to provide a digital-analog converter which can obtain the effect of dither addition and subtraction even when the level of a digital information signal is high.

[Means for solving problems]

The present invention for achieving the above object has an input circuit for inputting a digital information signal of a two's complement code having N bits (where N is an integer of 3 or more) and N bits. Lower M bits (where M is N>M>
A digital dither generating means for generating a digital dither whose upper NM bits are a logical range "0", and the digital dither generating means are connected to the digital dither generating means. A two's complement circuit for generating the two's complement of a digital dither and a signal line of the most significant bit of N digital information signal lines corresponding to N bits derived from the input circuit are connected. A NOT circuit, an output terminal of the NOT circuit, and a predetermined number of high-order bit signal lines other than the most significant bit signal line of the N-bit digital information signal lines are connected to the input circuit of the input circuit. A logical product circuit for generating an output indicating whether or not the digital information signal is above a predetermined level, the digital dither generating means, the two's complement circuit, and the logical product. And a digital AND circuit for selecting and outputting the digital dither of the dither generating means in response to an output obtained from the AND circuit indicating that the level is not higher than the predetermined level. Connected to the dither switching circuit for selecting and outputting the 2's complement of the 2's complement circuit in response to the output indicating that the level is equal to or higher than the predetermined level, and the input circuit and the dither switching circuit. Is connected to the adder for adding the output of the dither switching circuit to the digital information signal of the input circuit, the adder and the dither switching circuit, and the output of the adder and the dither switching. Digital-analog conversion means for converting the output of the circuit into an analog signal, and dither addition information corresponding to the output of the adder, which is connected to the digital-analog conversion means. The present invention relates to a digital-analog conversion device comprising subtraction means for subtracting the dither analog signal corresponding to the output of the dither switching circuit from the analog signal.

In the present invention, the offset binary code and the two's complement code (2's co) are used.
The relation between the mplement code) and the signal level in decimal system is shown in 4 bits data as follows.

The 16-bit two's complement code in the embodiment is also the above-mentioned four.
It is determined in the same way as the bit code. Further, the 2's complement of the digital dither is a number obtained by inverting each hit of the digital dither and adding 1 thereto.

[Work]

In the above invention, when the level of the digital information signal is high, the 2's complement of the digital dither is added. As a result, an addition signal equivalent to that obtained by subtracting the digital dither from the digital information signal can be obtained, and the analog signal corresponding to the digital information signal can be restored. In addition, the effects of dither addition and subtraction can be obtained up to a high level range of the input digital information signal.

[First Embodiment] Next, a first embodiment of the present invention will be described.

[Explanation of the entire D / A converter]

The apparatus for converting a digitalized audio signal into an analog signal according to the first embodiment shown in FIG.
It has an input circuit (1) for inputting a digital information signal (hereinafter referred to as data) of a 2's complement code of word 16 bits in parallel form, which is connected to the digital adder (2). From this input circuit (1), for example,
Input the sampling repetition frequency data of 88.2kHz.

(3) is a digital dither generator, which is a circuit for generating a 12-bit offset binary code digital signal substantially randomly at the same sampling frequency of 88.2 kHz as the data. This dither generator (3)
Is composed of an M-sequence (Maximal-length Pules Sequences) pseudo-random pulse generating circuit, which is substantially the same as the analog white noise converted into a digital signal and is transmitted in synchronization with data.

The 4-bit additional circuit (3a) connected to the dither generator (3) is the MSB (the Mos) of a 12-bit digital dither.
t Significant Bit), 4 bits with the content of logic "0" are added, and a 16 bit dither is output. This digital dither corresponds to positive level data in 2's complement code.

The 2's complement circuit (3b) connected to the 4 bit addition circuit (3a) outputs the 2's complement of the 16 bit dither. Since this input is 2's complement code positive level data, this output corresponds to 2's complement code negative level data.

The dither switching circuit (4) connected to the 4-bit addition circuit (3a) and the negative number circuit (3b) of 2 is a multiplexer (mu).
ltiplexer) and selects either dither or its two's complement.

The data level judgment circuit (5) connected to the 16-bit data input circuit (1) judges whether the added value of the 16-bit data and the 12-bit dither may be incorrect, and When there is no possibility, a 4-bit additional circuit (3
The output dither of a) is selected, and the switching circuit (4) is controlled to select the output of the two's complement circuit (3b) when there is a possibility of improperness.

The adder (2) connected to the 16-bit data input circuit (1) and the dither switching circuit (4) is input in parallel.
16-bit data X and 12-bit dither Y (or its two's complement) input in parallel are added in bit units, and X +
It outputs a 16-bit Y addition signal.

The multiplexing circuit (6) connected to the adder (2) and the dither switching circuit (4) is composed of a multiplexer, and the data + dither signal (X +) obtained from the 16-bit adder (2) is obtained.
Y) and the dither (Y) obtained from the dither switching circuit (4)
And are time-division multiplexed. The multiplexing circuit (6) also separates the right and left channels.

The D / A converter (7) connected to the output of the multiplexing circuit (6) has a 16-bit input terminal and D / A converts data + dither signal (X + Y) and dither (Y) respectively. Then, the analog data + dither signal (X ′ × Y ′), the analog dither (Y ′) and the time division multiplexed signal are output. The D / A converter (7) is a circuit for converting 2's complement code data output from the multiplexing circuit (6) into an offset binary code (NOT circuit for inverting the MSB) and an offset binary code. It consists of PCM53JP-V, a Burr Brown IC configured to convert binary coded data to analog and produces positive and negative level outputs.

The sample hold circuit (8) connected to the output terminal of the D / A converter (7) outputs the data + the dither signal (X ′ + Y ′) and the dither (Y ′) output from the D / A converter (7). ) And the analog dither (Y ') is sampled from the multiplexed signal and held.

One input terminal of the subtraction circuit (9) is a D / A converter (7)
Since the other input terminal is connected to the output of the sample hold circuit (8), this subtraction circuit (9) is output from the D / A converter (7) in time division multiplex format. The output analog dither (Y ') of the sample hold circuit (8) is analog-subtracted from the analog data + dither signal (X' + Y ') and the analog dither (Y').

The sampling gate circuit (10) connected to the output of the subtraction circuit (9) extracts analog data (X ′) from the output of the subtraction circuit (9).

The low pass filter (19) connected to the output of the sampling gate circuit (10) is connected to the sampling gate circuit (1
The intermittent part of the intermittent analog information signal obtained from 0) is interpolated, and complete analog data is sent to the output terminal (12).

[Explanation of FIG. 2] FIG. 2 shows in detail the 2's complement circuit (3b), the data level determination circuit (5) and the dither switching circuit (4) of FIG. Lines a ₁ to a derived from the data input circuit (1)
₁₆ is 16 bits from MSB to LSB of 16-bit two's complement code.
It corresponds to the bit and is connected to the adder (2) and the lines a _{1 to} a ₄ of the upper 4 bits are connected to the data level judgment circuit (5). Data level determination circuit (5) is, NOT circuits (1 connected to the MSB line a ₁
3), and an AND gate (14) connected to this output and 2SB line a ₂ and to 3SB line a ₃ and 4SB line a ₄
AND gate (15) and the previous two AND gates (14) (1
It consists of an AND gate (16) connected to 5). by the way,
Since the 2's complement code is the inverted MSB of the offset binary code data as described above, the upper 4 bits (MSB, 2SB, 3SB, 4SB) of the offset binary code data are [1111]. When, the two's complement code is [0111]. In this embodiment, if the 12-bit dither is added when the upper 4 bits of the data of the 2's complement code is [0111], the added value may be incorrect. Therefore, the data level determination circuit (5) generates a high level output only when the upper 4 bits are [0111], and generates a low level output in other cases.

16-bit output line b ₁ ~ of 4-bit additional circuit (3a)
The b ₁₆ is connected to one contact a of the dither switching circuit (4) and is also connected to the other contact b via the two's complement circuit (3b). 2's complement circuit (3b) includes a NOT circuit N ₁ to N ₁₆ which is connected to the line b ₁ ~b _16, become from the + 1 adder circuit (17), the 2's complement output line C ₁ -C ₁₆ Output.

The dither switching circuit (4) is a data level determination circuit (5)
The contact a is turned on when the output of is low level and the dither of the 4-bit addition circuit (3a) is selected, and the contact b is turned on when the output of the data level determination circuit (5) is low level. Complement is selected. Therefore, this output line d ₁ ~
The dither and its two's complement are selectively obtained at d ₁₆ .
The switching circuit (4) is shown by the contacts a and b,
Actually, it is composed of an electronic switch.

〔motion〕

Next, in the system of FIGS. 1 and 2, when the upper 4 bits of the data of the 2's complement code are other than [0111], addition and subtraction are properly performed even if the dither level is the maximum. Explain that. The 16-bit two's complement code data indicating the analog (decimal) positive maximum level is [0111111111111111], and the two's complement code data indicating the analog zero level is [0000000000000000]. The data of the two's complement code indicating the negative maximum level of [1000000000000000] is [1000000000000000], and there are many data corresponding to many analog levels in the meantime. Now, as an example, when the highest dither [0000111111111111] of all 12 bits is 1 is added to the data [1000000000000001] of 2's complement code corresponding to +1 of the analog level, the following equation is obtained.

Therefore, the adder (2) sends the addition output without overflow.

On the other hand, when the data corresponding to the analog positive maximum level of the upper 4 bits [0111], for example, is added with the dither corresponding to the analog level + 1, the result is as follows.

In the two's complement code, this added value corresponds to the negative maximum analog level. Therefore, it can be seen that the two's complement code has an incorrect addition value. Therefore, according to the present invention, a two's complement is used as a dither and is added to the data to obtain the following added value.

This added value has 17 digits, but since the adder (2) has only an output line of 16 bits, it outputs only 16 bits up to 16 digits. When the number exceeds 16 digits (in the case of overflow) like the above-mentioned added value, a signal (carry flag) indicating overflow is generated from the adder (2). The data consisting of up to 16 digits of the added value corresponds to an analog level which is one stage lower than the maximum positive analog level in the 2's complement code.
When 16-bit data [0111111111111110] of the added value is converted into an analog signal, analog data of (+ MAX) -1 level is obtained, and when the two's complement [1111111111111111] is converted into an analog signal, An analog dither signal with a level of -1 is obtained, and when these are analog-subtracted by the arithmetic circuit (9), (+ MAX) -1-(-1) = + MAX, and the original analog signal is restored.

Another example is shown below. Now, if the dither of the two's complement code corresponding to the analog +2 level is added to the data of the two's complement code corresponding to the maximum analog positive level + MAX, the following value is obtained.

This added value is one less than the maximum negative analog value −MAX.
It shows a higher level -MAX + 1, which is significantly different from the original data, and even if the analog dither is subtracted on the analog side, the original analog signal cannot be restored. However, adding two's complement dithers in accordance with the present invention results in the following:

The 2's complement dither added in the above equation corresponds to the -2 level of the analog signal, so that the lower 16 bits (adder output) of the added value are two levels below the maximum positive analog level + MAX. + MAX-2), which corresponds to the original data. If the analog dither (-2) corresponding to [1111111111111110] is subtracted from the analog addition signal (+ MAX-2) corresponding to [0111111111111101] obtained from the D / A converter (7), (+ MAX-2)-( -2) = + MAX, and the original analog signal is restored.

To summarize this method, in the case where N bit (16 bits) 2's complement code data is added and operated with the M bit (12 bits) 2's complement code dither, the upper N-th data If the M bit (4 bits) has the maximum digit (MSB) of 0 and all the remaining bits (3 bits) are 1, then proper dither addition and subtraction may be impossible. Therefore, the two's complement of the dither (reverse polarity dither) is added, and the analog dither corresponding to the two's complement is subtracted on the analog side.

[Time division operation]

FIG. 3 shows the state of each part of FIG. 1 in principle. From the input circuit (1) of FIG. 1, as shown in FIG.
The data X is output in parallel at the sampling period T. This data X is the data of the right channel of the stereo signal, and the sampling period T is the first period T ₁ of the first half and the second period T of the latter half. It is disposed in the period T ₂ of the half after dividing into ₂ and. The first period T ₁ of the first half is used for the left channel data of the stereo signal.

The dither switching circuit (4) outputs a digital dither Y corresponding to a pseudo random pulse as shown in FIG. 3 (B) at the same sampling period as the data.

In the adder (2), the data X of FIG. 3 (A) and the dither Y of FIG. 3 (B) are digitally added to obtain the addition output X + Y of FIG. 3 (C).

Multiplexing circuit (6), t ₀ ~t ₃ as shown in FIG. 3 (D)
The dither Y is arranged in the first period T ₁ until the second period from t ₃ to t ₆ .
The data + dither signal (X + Y) is arranged in the period. At the same time, the left and right channel data are separated.

The D / A converter (7) converts the digital multiplexed signal Y + (X + Y) of FIG. 3 (D) into an analog multiplexed signal Y '+ (X'.
+ Y ').

The sample hold circuit (8) extracts the output of the D / A converter (7) at the timing of t ₁ to t _{2 in} FIG. 3 (E). Since the period from t _{1 to} t ₂ is during the period T ₁ (t _{0 to} t ₃ ) in which the D / A converter (7) outputs the analog dither signal Y ′, the sample hold circuit (8) , An analog dither Y ′ is extracted, and as shown in FIG. 3 (F), this is held for one sampling period (t _{1 to} t ₇ ) and output, and at t ₇ , a new analog dither Y ′ is sampled and held. .

In the arithmetic circuit (9), the third input which is one of the inputs
Analog data + dither signal (X '+) shown in FIG.
The analog dither Y ', which is the other input, is subtracted from the time division multiplexed signal of Y') and the dither signal (Y '). Therefore, during the period from t ₃ to t _{6 in} FIG. ₃ , (X ′ + Y ′) − Y ′ =
The output of X'is obtained. Even if the D / A converter (7) has an offset voltage V ₀ , (X ′ + Y ′ + V ₀ ) −
Since the _{(Y '+ V 0) =} X', in the arithmetic circuit (9) analog data X of the output stage of 'does not include offset voltage.

The output of the arithmetic circuit (9) includes unnecessary signals other than the necessary analog data X '. Therefore, Yotsute the sampling gate circuit (10), extraction of FIG. 3 (G) to t ₄ analog data at the timing of ~t ₅ X as shown 'is performed. By setting this extraction to t ₄ to t ₅ within t ₃ to t ₆ , the glitch (glitc) included near both ends of t ₃ to t ₆
You can get the output except h).

The intermittent signal in FIG. 3 (G) is a low pass filter (11).
The signal is interpolated by passing through, and a complete analog information signal is output from the output terminal (12).

In the system shown in FIG. 3, both the digital data + dither signal (X + Y) and the digital days (Y) are converted into analog signals by the same D / A converter (7). Since the A conversion error becomes the same, the subtraction of (X '+ Y')-(Y ') = X' in the arithmetic circuit (9) can be performed well.

[Second Embodiment] Next, a digital-analog converter according to a second embodiment of the present invention shown in FIG. 4 will be described. The input circuit (1), dither generator (3), 4 bit addition and 2 in FIG.
Complement code conversion circuit (3a), 2's complement circuit (3b), dither switching circuit (4), level determination circuit (5), adder (2), D / A converter (7), subtraction circuit (9) ), The sampling gate circuit (10), and the filter (11) are constructed in the same manner as shown by the same reference numerals in FIG. In this example, since the multiplication circuit (6) shown in FIG. 1 is not provided, the first D / A converter (7) converts only the digital data + the dither signal (X + Y) into an analog signal for calculation. Send to circuit (9). The digital dither Y is converted into an analog dither (Y ') by the second D / A converter (7a) connected to the output of the dither limiting gate circuit (4) and sent to the arithmetic circuit (9). The arithmetic circuit (9) outputs (X '+ Y')-Y '= X' obtained by subtracting the analog dither Y'from the analog data + dither signal (X '+ Y'). In this example, in order to input a stereo signal, a third signal is input.
As in the case of FIG. 3A, the right channel digital data X is arranged in the rear half of one sampling period T, and the left channel data is arranged in the front half thereof.
The channel separation circuit (6a) connected to the D / A converter (7) separates the left and right channel data.

(Modification)

The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(A) In FIG. 1, the multiplication circuit (6) is not provided on the output side of the adder (2), but a gate circuit is provided on the input side of the adder (2). Alternatively, the data X may be input to the adder (2) with a vacant time, and the dither Y may be added to the data X to form a time division multiplex signal of the X + Y signal and Y.

(B) In the system shown in FIG. 1, the sample hold circuit (8) allows analog data + dither signal (X '
+ Y ') may be sample-held.

(C) Period T _{1 in} FIG. 3 without inputting a stereo signal
Input signal to period T ₂ or to the first period T ₁
May be free time.

(D) The dither generator (3) is replaced with an analog dither generator.
It may be configured in combination with an A / D converter.

(E) Data may be input as an offset binary code, converted into a two's complement code, and input to the adder (2). In this case, the level determination circuit (5) may be a circuit for determining whether or not the upper 4 bits in the offset binary code are all "1".

〔The invention's effect〕

As is apparent from the above, according to the present invention, even when a D / A converter with a small number of bits is used, it is possible to obtain the effect of adding and subtracting the dither up to the high level range of the data. .

[Brief description of drawings]

FIG. 1 is a block diagram showing the D / A converter of the first embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of FIG. 1 in detail, and FIG. FIG. 4 is a block diagram showing the D / A conversion device of the second embodiment of the present invention. (1) …… Data input circuit, (2) …… Adder, (3)
...... Dither generator, (3b) ...... 2's complement circuit, (4) ...
… Dither switching circuit, (5) …… Level judgment circuit, (9)
…… Subtraction circuit.

Claims (1)

[Claims] 1. An input circuit for inputting a digital information signal of a two's complement code having N bits (where N is an integer of 3 or more), and N bits, the lower M bits of which (M Is N>
Is connected to the digital dither generating means for generating a digital dither which has a dynamic range (an integer satisfying M> 2) and whose upper NM bits are logic "0". , A 2's complement circuit for generating the 2's complement of the digital dither, and N corresponding to N bits derived from the input circuit.
NOT circuit connected to the signal line of the most significant bit of the digital information signal lines of the book, the output terminal of the NOT circuit and the signal line of the most significant bit of the N bit digital information signal lines Connected to a predetermined number of high-order bit signal lines except
The AND circuit is connected to the AND circuit for generating an output indicating whether or not the digital information signal of the input circuit is above a predetermined level, the digital dither generating means, the two's complement circuit and the AND circuit. The digital dither of the dither generating means is selected and output in response to an output obtained from the AND circuit indicating that the level is not equal to or higher than the predetermined level, and the digital level is equal to or higher than the predetermined level obtained from the AND circuit. Is connected to the input circuit and the dither switching circuit for selecting and outputting the 2's complement of the 2's complement circuit in response to an output indicating that An adder for adding the output of the dither switching circuit to the digital information signal, and the adder and the dither switching circuit are connected,
Digital-analog conversion means for converting the output of the adder and the output of the dither switching circuit into an analog signal, and connected to the digital-analog conversion means,
A digital-analog conversion device comprising: subtractor means for subtracting the dither analog signal corresponding to the output of the dither switching circuit from the dither addition information analog signal corresponding to the output of the adder.