JPH0810827B2 - Digital-analog converter - Google Patents

Description

The present invention relates to a digital information signal corresponding to an analog signal such as an audio signal, which is analogized by addition of dither or addition and subtraction of dither. The present invention relates to a digital-analog (D / A) conversion device for converting a signal.

[Conventional technology]

Quantization noise (difference between quantized output and input sample value) becomes a problem in PCM recording and reproduction of audio signals.
Especially, when the input signal level is low and the number of quantization steps is small, the quantization noise has a strong correlation with the input, and becomes a kind of distortion (higher harmonic) of the input signal rather than noise. Further, even if the input signal level is high, an unpleasant noise is generated every time the quantization step changes for a signal that changes extremely slowly. In order to solve the above problems, at the time of A / D conversion, white noise called dither is added to an analog input signal and converted into a digital signal,
Alternatively, add the dither to the analog input signal, convert it to a digital signal, and then subtract the digital dither signal corresponding to this dither, or add the digital dither signal to the digital signal during D / A conversion. hand
It is already known to perform D / A conversion or to subtract an analog dither signal corresponding to a digital dither signal from the D / A conversion output after this D / A conversion.

[Problems to be solved by the invention]

By the way, when a digital dither is added to the digital information signal (data), this added value may be larger than the maximum allowable input level of the D / A converter. If an adder and a D / A converter suitable for the maximum digit of the data + dither signal are prepared, no problem will occur, but the cost of the adder and the A / D converter will increase. On the other hand, if the number of input bits (maximum input digit) of the adder and D / A converter is limited to a fixed value (for example, 16 bits), the data level must be limited to the range where the adder does not overflow during dither addition. Inevitably, the dynamic range of D / A conversion becomes narrower.

In order to solve the above problems, the applicant of the present application has proposed a method of stopping the addition of dither when the level of input data is high in Japanese Patent Application No. 60-150566. According to this method, it is possible to prevent the added value of the data and the dither from exceeding a predetermined number of bits. However, the effect of dither addition and subtraction cannot be obtained during the blocking period.

Therefore, it is an object of the present invention to provide a digital-analog converter which can obtain the effect of dither addition and subtraction even when the level of a digital information signal is high.

[Means for solving problems]

The present invention for achieving the above object comprises an input circuit, a digital dither generator, a dither level limiting gate circuit, an overflow level judgment circuit, an adder, a digital / analog conversion means and a subtraction means, and the input circuit is an offset circuit. .N in binary code or 2's complement code
It has N signal lines for supplying digital information signals of bits (where N is an integer of 4 or more) in parallel, and the digital dither generator has M bits of an offset binary code (where M is N). > M ≧ 3), and the dither level limiting gate circuit comprises M number of dither level limiting gates. Of the dither level limiting gates have first and second input terminals, respectively, and the first input terminals of the M dither level limiting gates transmit M-bit dithers generated in parallel from the digital dither generator. And the second input terminals of the M dither level limiting gates are connected to the M lines for Is connected to an upper overflow level determination logic circuit and a lower overflow level determination logic circuit, and the upper overflow level determination logic circuit is the uppermost one of the N signal lines. Bit line to N
The N-bit digital information, which is connected between the upper bit signal line up to the Mth bit line and the second input terminal of the uppermost dither level limiting gate among the M dither level limiting gates. When the most significant bits from the most significant bit to the NMth bit of the signal are offset binary codes, they all show a logical 1, and when they are two's complement codes, the most significant bit is a logical 0.
, And the lower overflow level decision logic circuit is configured to place the uppermost dither level limiting gate in a blocking state when the other bits up to the NMth bit indicate a logic one. Of the signal lines of the remaining bits excluding the upper N-M bits and the lowermost bits of the signal and the remaining M-1 of the M dither level limiting gates excluding the uppermost dither level limiting gate.
M-1 overflow level decision gates respectively connected to the second input terminals of the dither level limit gates, each overflow level decision gate being a respective one upper overflow level decision gate. Alternatively, the upper overflow level judgment logic circuit controls the corresponding dither level limiting gates to the blocking state and the corresponding dither level limiting gates are blocked only when the corresponding signal line is logic 1. To each one of the upper overflow level judgment gates or the upper overflow level judgment logic circuit so that the adder is connected to the input circuit and the dither level limiting gate circuit and the N inputs. The digital information of the line No. and the digital dither obtained through the M dither level limiting gates are added, and the digital-to-analog converting means includes the dither addition data signal obtained from the adder and the dither level limiting gates. The dither obtained from the circuit is formed to be converted into an analog signal, and the subtracting means is formed to subtract the analog dither from the analog dither-added data signal obtained from the digital-analog converting means. The present invention relates to a digital-analog conversion device characterized by the above.

[Work]

In the above invention, when the level of the digital information signal is high, the level-limited dither is added. Therefore, even if the dither is added, the added value does not exceed the predetermined number of bits (N bits), that is, the predetermined digit. Since the level of the digital information signal is not limited, the dynamic range of D / A conversion can be kept large. In addition, the effects of dither addition and subtraction can be obtained in a wide level range of the input digital information signal.

[First Embodiment] Next, a first embodiment of the present invention will be described.

[Explanation of the entire D / A converter]

The apparatus for converting a digitalized audio signal into an analog signal according to the first embodiment shown in FIG.
Word 16-bit offset binary code (offs
It has an input circuit (1) for inputting a digital information signal (hereinafter simply referred to as data) having a configuration of et binary code) in parallel form, which is connected to a digital adder (2). From this input circuit (1), for example, 88.2
Data is input at the sampling repetition frequency of kHz.

(3) is a digital dither generator, which is a circuit for generating a 12-bit binary digital signal substantially randomly at the same sampling frequency of 88.2 kHz as the data. This dither generator (3) is an M-sequence (Maximal-len
gth Pulsc Sequences) consists of a pseudo-random pulse generator circuit, which is virtually the same as analog white noise converted into a digital signal, and is transmitted in synchronization with data.

The dither level limiting gate circuit (4) connected to the output stage of the dither generator (3) limits the dither level when the data level is high according to the present invention.

The overflow level judgment circuit (5) connected to the 16-bit data input circuit (1)
It is judged whether or not the added value with the 12-bit dither may exceed N bits (16 bits), that is, N digits. Further, it is determined how much the dither level should be lowered so that the added value will not exceed N bits. It is a circuit that controls the dither level limiting gate circuit (4) according to the determination result.

An adder (2) connected to a 16-bit data input circuit (1) and a dither level limiting gate circuit (4) outputs 16-bit data X input in parallel and a 12-bit dither Y input in parallel. It adds in units and outputs a 16-bit addition signal of X + Y.

The multiplexer circuit (6) connected to the adder (2) and the dither level limiting gate circuit (4) is a multiplexer (mult).
iplexer), data + dither signal (X + Y) obtained from a 16-bit adder (2) and gate circuit (4)
And the dither (Y) obtained from (1) are time-division multiplexed. The multiplexing circuit (6) also separates the right and left channels.

The D / A converter (7) connected to the output of the multiplexing circuit (6) is composed of PCM53JP-V which is an IC of Burr Brown Co., has a 16-bit input terminal, and has a data + dither signal (X + Y). ) And dither (Y) are respectively D / A converted to output a time division multiplexed signal of analog data + dither signal (X '+ Y') and analog dither (Y ').

The sample hold circuit (8) connected to the output terminal of the D / A converter (7) outputs the data + the dither signal (X ′ + Y ′) and the dither (Y ′) output from the D / A converter (7). ) And the analog dither (Y ') is sampled from the multiplexed signal and held.

One input terminal of the subtraction circuit (9) is a D / A converter (7)
Since the other input terminal is connected to the output of the sample hold circuit (8), this subtraction circuit (9) is output from the D / A converter (7) in time division multiplex format. The output analog dither (Y ') of the sample hold circuit (8) is analog-subtracted from the analog data + dither signal (X' + Y ') and the analog dither (Y').

The sampling gate circuit (10) connected to the output of the subtraction circuit (9) extracts analog data (X ′) from the output of the subtraction circuit (9).

The low pass filter (19) connected to the output of the sampling gate circuit (10) is connected to the sampling gate circuit (1
The intermittent part of the intermittent analog information signal obtained from 0) is interpolated, and complete analog data is sent to the output terminal (12).

[Explanation of FIG. 2] FIG. 2 shows the overflow level determination circuit (5) and the dither level limiting gate circuit (4) of FIG. 1 in detail. The dither level limiting gate circuit (4) is shown in FIG.
Has a dither input lines b ₁ ~b ₁₂ of 12 which is connected to bit digital dither generator (3), one input of AND gate D ₁ to D ₁₂ of the dither input lines b ₁ ~b ₁₂ 12 It is connected to each terminal. Accordance connexion, dither the AND gate D ₁ ~D
Is limited by by connexion bit units ₁₂ are sent to the output terminal C ₁ -C ₁₂ of AND gate D ₁ to D ₁₂ in.

The overflow determination circuit (5) is the second digit in the 16-bit data lines a _{1 to} a ₁₆ , that is, 15SB (15th Significant).
16th digit from the line a _{2 of} Bit) or MSB (the Most Signifi
cant bit) is connected to 15 lines up to line a ₁₆ . The 2nd to 12th digit lines a _{2 to} a ₁₂ are AND gates E ₁
~ E ₁₁ and NOT circuits F _{1 to} F ₁₁ are connected to the other input terminals of the AND gates D _{1 to} D _{11 in} the dither level control gate circuit (4). 13th digit line a ₁₃ and 14th digit line a ₁₄
And are connected to the AND gate E ₁₃ and connect the 15th digit line a ₁₅ and the 16th digit line a ₁₅ .
Digit (MSB) line a ₁₆ is connected to AND gate E ₁₄
The output terminals of the AND gates E ₁₃ and E ₁₄ are connected to the AND gate E ₁₂ in the next stage of these. The output terminal of AND gate E ₁₂ is NOT
It is connected to the other input terminal of the AND gate D ₁₂ of the maximum digit in the dither level control gate circuit (4) via the circuit F ₁₂ . The output terminal of the AND gate E ₁₂ is the AND gate E ₁₁
Is connected to the input terminal of Also, AND gates E _{1 to} E ₁₀
One of the two input terminals are respectively connected to the output terminal of the one AND on the digit gate E ₃ to E _11.

Now, _{one of the} upper 4 bits (bits a _{13 to} a ₁₆ ) of 16 bits of binary data (X) MSB, 2SB, 3SB, 4SB in the data lines a _{1 to} a ₁₆ is a logic "0". If so, the 12-bit dither Y is at the maximum level (b ₁ (LSB) ~ b
_Even if all ₁₂ (MSB) are logical "1", X + Y does not exceed 16 digits. Therefore, the output of the AND gate E ₁₂ is low level, the output of the NOT circuit F ₁₂ is high level, and the remaining NO
The outputs of the T circuits F _{1 to} F ₁₁ also become high level, and AND gates D _{1 to} D
₁₂ does not at all limit the dither, dither line b ₁ ~b ₁₂ is directly output to the line c ₁ to c _12. In short, when the data level is low, the dither is added as it is.

When all the upper 4 bits (bits a _{13 to} a ₁₆ ) of the data X are high level (logic “1”) and the fifth bit (a ₁₂ ) from the top is low level, that is, the upper 5 bits are 〔1111
In the case of [0], the outputs of the AND gates E ₁₃ , E ₁₄ , and E ₁₂ become high level, the output of the NOT circuit F ₁₂ becomes low level, and the highest digit bit of the dither Y passes through the AND gate D _12. Can not.
However, since the line a ₁₂ of the 5SB is low level, the output of the AND gate E ₁₁ is low level, the output of the NOT circuit F ₁₁ is high level, and the dither can pass through the AND gate D ₁₁ . At this time, the AND gate D ₁ to D ₁₁ output from also all the high level 11 of the lower of the NOT circuit F ₁ to F ₁₀ are dither passes than NOT circuit F _11. That is, when the upper 5 bits of the 16-bit data X is [11110], the 12-bit dither Y is the lower 11 bits.
The output is bit-controlled. Therefore, even if all 11 bits of the dither Y are logical "1", the added value X + Y of the data and the dither does not exceed 16 bits.

When the upper 6 bits of the 16-bit data X are [111110], the outputs of the NOT circuits F ₁₁ and F ₁₂ become low level, and the upper 2 bits of the AND gates D ₁₂ and D ₁₁ pass the dither. Block. Since the output of the AND gate E ₁₀ of the judgment circuit (5) is at a low level, the NOT circuit F ₁₀ and the lower NO
The outputs of the T circuits F _{1 to} F ₉ become high level, and the lower 1 of dither X
Bit 0 passes through AND gates D ₁ -D ₁₀ .

As described above, as the level of the data X becomes higher, the level of the dither Y becomes smaller, and if the upper 15 bits of the data X (bits a _{2 to} a ₁₆ ) are all logic “1”, then 12 bits are obtained. The outputs of the NOT circuits F _{1 to} F ₁₂ of the above all become low level, and the passage of all bits of the dither Y is blocked.

After all, in this manner, 16 as long as the bit all the top 15 bits of the data X (bit of a ₂ ~a ₁₆₎ does not turn the logic "1" at the same time, is carried out the addition to the data of the dither.
That is, all of the top N _S bits are high level “1”,
When the N _S + 1st bit from the high order is low level “0”,
Dither Y is limited to (15-N _S ) bits.

As described above, according to this method, the dither addition and subtraction effects can be obtained even in the area where the level of the data X is high. In short, the 16-bit data X gives 2 ¹⁶
= Among the 65536 levels, it is possible to add limited or unrestricted dither to levels up to 65534.

[Explanation of operation]

FIG. 3 shows the states of the first parts in principle. As shown in FIG. 3A, the input circuit (1) of FIG. 1 outputs data X in parallel at one sampling period T. The data X is data of the right channel of the stereo signal, placed in the period T ₂ halves after splitting the sampling period T before the first period T ₁ of the half rear half second and period T ₂ of Has been done. The first period T ₁ of the first half is used for the left channel data of the stereo signal.

The dither generator (3) outputs a digital dither Y composed of pseudo-random pulses as shown in FIG. 3 (B) at the same sampling cycle as the data. In FIG. 3, a dither level limiting gate circuit (4) is shown for ease of explanation.
Is also shown as Y.

In the adder (2), the data X of FIG. 3 (A) and the dither Y of FIG. 3 (B) are digitally added to obtain the addition output X + Y of FIG. 3 (C). Since the dither Y is limited by the dither level limiting gate (4) when the level of the data X is high, the adder (2) does not overflow.

Multiplexing circuit (6), t ₀ ~t ₃ as shown in FIG. 3 (D)
The dither Y is arranged in the first period T ₁ until the second period from t ₃ to t ₆ .
Data + dither signal (X + Y) in the period of are arranged. At the same time, the left and right channel data are separated.

The D / A converter (7) converts the digital multiplexed signal Y + (X + Y) of FIG. 3 (D) into an analog multiplexed signal Y '+ (X'.
+ Y ').

The sample hold circuit (8) extracts the output of the D / A converter (7) at the timing of t ₁ to t _{2 in} FIG. 3 (E). Since the period from t _{1 to} t ₂ is during the time T ₁ (t _{0 to} t ₃ ) when the D / A converter (7) outputs the analog dither signal Y ′, the sample hold circuit (8) , Analog dither Y ′ is extracted, and as shown in FIG. 3 (F), this is held for one sampling period (t _{1 to} t ₇ ) and output, and at t ₇ , a new analog dither Y ′ is sampled and held. To do.

In the subtracting circuit (9), the analog data + dither signal (X ') shown in FIG.
+ Y ') and dither signal (Y')
The other input, the analog dither Y ', is subtracted. Therefore, during the period from t ₃ to t _{6 in} FIG. ₃ , (X ′ + Y ′) − Y ′
= X 'output is obtained. Even if the D / A converter (7) has an offset voltage V ₀ , (X ′ + Y ′ + V ₀ ) −
Since the (Y '+ V ₀₎ = X', in the subtraction circuit (9) analog data X of the output stage of 'does not include offset voltage.

The output of the subtraction circuit (9) includes unnecessary signals other than the necessary analog data X '. Therefore, Yotsute the sampling gate circuit (10), extraction of FIG. 3 (G) to t ₄ analog data at the timing of ~t ₅ X as shown 'is performed. By setting this extraction to t ₄ to t ₅ within t ₃ to t ₆ , the glitch (glitc) included near both ends of t ₃ to t ₆
You can get the output except h).

The intermittent signal in FIG. 3 (G) is a low pass filter (11).
The signal is interpolated by passing through, and a complete analog information signal is output from the output terminal (12).

In the method of FIG. 3, both the digital data + dither signal (X + Y) and the digital dither (Y) are converted into analog signals by the same D / A converter (7), so both D Since the / A conversion errors are the same, the subtraction of (X '+ Y')-(Y ') = X' in the arithmetic circuit (9) can be favorably performed.

[Second Embodiment] Next, a digital-analog converter according to a second embodiment of the present invention shown in FIG. 4 will be described. Input circuit (1), dither generator (3), dither level limiting gate circuit (4), overflow level judgment circuit (5), adder (2), D / A converter (7), subtraction circuit in FIG. (9), sampling gate circuit (10), filter (1
1) has the same structure as that shown in FIG. In this example, the multiplexing circuit (6) in FIG.
Is not provided, the first D / A converter (7) converts only the digital data + the dither signal (X + Y) to analog and sends it to the subtraction circuit (9). The digital dither Y is converted into an analog dither (Y) by the second D / A converter (7a) connected to the output of the dither limiting gate circuit (4) and sent to the subtracting circuit (9). The subtraction circuit (9) subtracts the analog dither Y'from the analog data + dither signal (X '+ Y') (X '+ Y')-Y '=
Output X '. In this example, in order to input a stereo signal, one sampling cycle T is used as in FIG. 3 (A).
Since the right channel digital data X is arranged in the rear half and the left channel data is arranged in the front half,
The channel separation circuit (6a) connected between the adder (2) and the D / A converter (7) separates the left and right channel data.

(Modification)

The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(A) In FIG. 1, the multiplexer circuit (6) is not provided on the output side of the adder (2), but a gate circuit is provided on the input side of the adder (2). Alternatively, the data X may be input to the adder (2) with a vacant time, and the dither Y may be added to the data X to form a time division multiplexed signal of the X + Y signal and Y.

(B) In the system shown in FIG. 1, the sample hold circuit (8) allows analog data + dither signal (X '
+ Y ') may be sampled and held.

(C) Period T _{1 in} FIG. 1 without inputting a stereo signal
Input the same signal as period T ₂ to the first period or
T ₁ may be free time.

(D) The dither generator (3) is replaced with an analog dither generator.
It may be configured in combination with an A / D converter.

(E) The present invention is also applicable to the case where the input data of the adder (2) is input with a 2's complement code. The two's complement code is an offset binary
Since this is a code with the MSB inverted, the NOT circuit (20) is connected to the line a ₁₆ of the MSB in FIG. 2 as shown in FIG.
Apply inverted MSB signal to gate E ₁₄ . Other than this is the second
The configuration is exactly the same as the figure.

〔The invention's effect〕

As is apparent from the above, according to the present invention, the following effects can be obtained.

(A) Since the limiting gates are connected to the M-bit dither transmission lines and the dither level is controlled for each bit based on the upper overflow level determination logic circuit and the lower overflow level determination logic circuit, the dither is configured. The level of can be finely controlled. Therefore, the effect of dither addition can be obtained up to a high level of the digital information signal.

(B) The lower overflow level judgment logic circuit includes M-1 overflow level judgment gates connected to respective input lines, and each overflow level judgment gate has one upper overflow level judgment gate or upper overflow level judgment gate. It is connected to the decision logic circuit. Therefore, a signal for controlling the dither level limiting gate can be easily and surely obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a D / A conversion device of a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a dither level limiting gate circuit and an overflow level judging circuit of FIG. 1, and FIG. FIG. 1 is a waveform diagram showing the states of points A to G in principle, FIG. 4 is a block diagram showing a D / A converter of the second embodiment of the present invention, and FIG. 5 is an overflow level determination of a modified example. It is a circuit diagram which shows a part of circuit. (1) …… Data input circuit, (2) …… Adder, (3)
... dither generator, (4) ... dither level limiting gate circuit, (5) ... overflow level judgment circuit.

Continuation of the front page (56) References JP-A-57-202123 (JP, A) JP-A-60-128719 (JP, A) Actually developed 55-141323 (JP, U)

Claims (1)

[Claims] 1. An input circuit, a digital dither generator, a dither level limiting gate circuit, an overflow level judgment circuit, an adder, a digital / analog conversion means and a subtraction means, wherein the input circuit is an offset binary code or 2 Complementary code of N bits (where N is an integer of 4 or more) for supplying in parallel the digital information signal, the digital dither generator having an offset binary
The dither level limiting gate circuit is configured to generate in parallel digital dithers consisting of substantially random digital signals of M bits of code (where M is an integer satisfying N> M ≧ 3). A dither level limiting gate, each of the M dither level limiting gates has a first and a second input terminal, and the first input terminals of the M dither level limiting gates are parallel to the digital dither generator. Occurred in M
Each of the M number of lines for transmitting a bit dither is connected to the second input terminal of each of the M dither level limiting gates, and the overflow level determination circuit is connected to the upper overflow level. A decision logic circuit and a lower overflow level decision logic circuit, wherein the upper overflow level decision logic circuit is an upper bit signal line from the most significant bit line to the NMth bit line of the N signal lines. Of the M dither level limiting gates and the second input terminal of the most significant dither level limiting gate, and the N-Mth bit from the most significant bit of the N-bit digital information signal. The upper bits up to are offset
When it is a binary code, it always shows logical 1 and 2
Is a complement code, the most significant dither level limiting gate is set to a blocking state when the most significant bit is a logical 0 and the other bits up to NM th are a logical one. The lower overflow level determination logic circuit connects the signal line of the remaining NM bits excluding the upper NM bits and the least significant bit of the N bits and the uppermost dither level limiting gate from the M dither level limiting gates. The remaining M-1 dither level limiting gates include M-1 overflow level judgment gates respectively connected to the second input terminals, and each overflow level judgment gate includes a respective 1 One upper overflow level decision gate or the upper overflow level decision logic circuit corresponds to this. The respective upper level overflows are controlled so that the respective dither level limiting gates are controlled to the blocking state and the corresponding dither level limiting gates are controlled to the blocking state only when the corresponding signal lines are at logic "1". Connected to the level judgment gate or the upper overflow level judgment logic circuit, the adder connected to the input circuit and the dither level limiting gate circuit, and the digital information signals of the N input lines and the M dither levels. It is formed so as to add with the digital dither obtained via the limiting gate, and the digital-analog conversion means obtains the dither addition data signal obtained from the adder and the dither obtained from the dither level limiting gate circuit. Formed to convert to an analog signal, Digital means is characterized in that it is formed to subtract the dither from dither added data signal of an analog of analog obtained from the digital-to-analog converter - analog converter.