JPH0666690B2 - Analog to digital converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital conversion device for converting an analog signal such as an audio signal into a digital signal accompanied by superposition (addition) and subtraction of a dither signal.

[0002]

2. Description of the Related Art Quantization noise (difference between quantized output and input sample value) becomes a problem in PCM recording / reproduction of an audio signal. Especially, when the input signal level is low and the number of quantization steps is small, the quantization noise has a strong correlation with the input, and becomes a kind of distortion (higher harmonic) of the input signal rather than noise. Also, even if the input signal level is high,
For a very slowly changing signal, annoying noise is generated each time the quantization step changes. In addition, there are variations in the quantization step of the A / D converter itself, and nonlinear distortion occurs during A / D conversion. In order to solve the above problems, white noise called dither is added to an input signal for A / D conversion, or dither is added for A / D conversion.
It is already known to convert and then subtract the dither.

[0003]

By the way, if the maximum allowable input level of the A / D converter is made constant and the dither signal is added to the analog signal, the dynamic range becomes narrower by the amount of the dither signal. Of course, if the maximum allowable input level of the A / D converter is increased, the dynamic range can be increased, but the cost of the device will inevitably increase. In order to solve this kind of problem, it is possible to lower the level of the analog dither when the input level becomes high, and to gradually lower this level through an integrating circuit without suddenly lowering it, for example, Japanese Patent Laid-Open No. 57-202123. Known in the gazette. However, it is not known to change the analog dither continuously or in multiple steps. Further, it is difficult to change the analog dither continuously or in multiple steps.

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog / digital conversion device capable of simply and automatically adjusting the level of analog dither continuously or in multiple steps.

[0005]

SUMMARY OF THE INVENTION To achieve the above object, the present invention relates to an analog information signal input line, a digital dither generator for generating digital dither in parallel bit format, and a digital dither generator. A digital-analog converter for converting the digital dither to an analog dither, a plurality of switches connected to a multi-bit dither transmission line between the digital dither generator and the digital-analog converter, and An adder for adding the analog information signal of the input line and the analog dither output from the digital-analog converter, the analog dither addition information signal obtained from the adder, and the digital-analog converter Analog dither and digital dither sum information signal and digit An analog / digital conversion means for converting into a dither, a subtracter for subtracting the digital dither from the digital dither addition information signal obtained from the analog / digital conversion means, and a control terminal of the plurality of switches are connected. The output terminals have a plurality of output terminals, and the plurality of output terminals are associated with the plurality of switches so as to sequentially block transmission from the upper bits of the digital dither generated by the digital dither generator as the shift operation progresses. The shift register, a clock signal supply means for supplying a clock signal for driving the shift register, and the output of the adder are compared with a reference value, and it is confirmed that the output of the adder is higher than the reference value. The comparison output shown cuts off the supply of the clock signal to the shift register. Serial those related to the analog-digital converter comprising a comparator for controlling the clock signal supply means. The analog-digital conversion means is the two A / D converters 11 and 12 shown in FIG. 1 or the one A / D converter 11 shown in FIG. The clock signal supply means is a clock signal line 51 with a switch 52.
Is.

[0006]

According to the present invention, the analog dither is not controlled by a variable resistor or the like, but a switch is provided on a transmission line of a plurality of bits of the digital dither and the switch is controlled by a shift register. It is possible to automatically prevent the output of the above from becoming excessively large with a simple configuration. In addition, the dither level can be corrected in multiple steps in bit units.

[0007]

[First Embodiment] Next, a first embodiment of the present invention will be described. An apparatus for converting an information analog signal corresponding to an audio signal into a digital signal according to the embodiment shown in FIG. 1 has an information analog signal input line 1 composed of an audio signal of about 0 to 20 kHz, which is a sample hold. It is connected to the analog adder 2 via the circuit 1a. The dither generator 3 comprises a digital dither generator 3a, a D / A converter 3b, and a digital dither level control circuit 9 connected between them. The digital dither generator 3a is composed of a known M-sequence pseudo random pulse generation circuit. The 12-bit digital dither obtained here is converted into analog dither by the D / A converter 3b. The level control circuit 9 is composed of twelve switches S1 to S12 connected in series to twelve lines for transmitting tether of 12 bits in parallel, and operates to reduce the level of the dither signal when the level of the analog information signal is high. To do. The control of the switches S1 to S12 will be described later.

The output terminal of dither generator 3 is coupled to the input terminal of analog adder 2. Therefore, the adder 2
Outputs an output obtained by analog-adding the analog information signal and the dither signal having a minute level.

Reference numeral 11 is a first A / D converter, which converts the output of the adder 2 into a 16-bit digital signal. A second A / D converter 12 converts the dither signal obtained from the dither generator 3 into a digital signal and outputs a random digital signal (dither digital signal) corresponding to the dither signal (white noise). To do.

A digital subtractor 13 has one input terminal connected to the output terminal of the first A / D converter 11 and the other input terminal to the output terminal of the second A / D converter 12. The second A / D converter 1 is connected from the digital dither addition information signal obtained from the first A / D converter 11.
The digital dither signal obtained from 2 is subtracted, and the digital information signal corresponding to the analog information signal is sent to the output line 14.

The level judgment control circuit 10 for controlling the level control circuit 9 includes a comparator 49 for comparing the output of the adder 2 and the output of the reference voltage source 48, and a shift register 50.
A switch 52 connected to a line 51 for supplying a clock signal to the shift register 50, and the shift register 5
0 reset signal supply line 53. The voltage VR of the reference voltage source 48 is equal to the maximum allowable input level VM of the A / D converter 11.

The shift register 50 has 12 stages of output terminals, and the outputs of the respective stages are connected to the control terminals of the switches S1 to S12. The switch 52 is for selectively supplying the clock signal to the shift register 50, and is responsive to the high level output of the comparator 49 indicating that the dither addition information signal obtained from the adder 2 has exceeded the predetermined value VM. Then it is configured to turn on. The reset signal on the line 53 resets the shift register in synchronization with the start or end of each sample hold of the sample hold circuit 1a connected to the input line 1. The frequency of the clock signal is sufficiently higher than the sampling frequency of the sample hold circuit 1a.

Next, the operation of the circuit shown in FIG. 1 will be described. An analog information signal is input from the line 1 and a dither signal having a lower level than the analog information signal is output from the dither generator 3. Both the analog information signal and the dither signal are input to the adder 2, and addition outputs of these are obtained, and this is converted into a digital signal by the A / D converter 11. On the other hand, the dither signal is converted into a digital signal by the second A / D converter 12, and becomes a random digital dither signal corresponding to white noise.
Sent to 3. In the subtractor 13, the digital dither signal is subtracted from the digital dither addition information signal,
A digital information signal is output that is substantially free of dither.

In the apparatus of FIG. 1, when the level of the input analog information signal is low, the digital dither generator 3a is used.
Is directly converted into an analog dither signal by the D / A converter 3b. That is, when the level of the input analog information signal is low and the output of the adder 2 is lower than the predetermined value VR = VM given by the reference voltage source 48, the output of the comparator 49 is low and the switch 52 is turned off. The shift register 50 is kept inoperative, all the switches S1 to S12 are kept on, and the 12-bit dither is D / A.
It is given to the converter 3b.

On the other hand, when the level of the input analog information signal becomes high and the output of the adder 2 exceeds the predetermined value VR = VM, and the output of the comparator 49 changes from the low level to the high level, the switch 52 is turned on. Therefore, the shift register 50 receives the clock signal as input data and uses the clock signal as a shift pulse, so that the output terminal of the shift register 50 sequentially becomes high level from the first stage to the twelfth stage. In response to this, the switches S1 to S12 are sequentially turned off. If the level of the input analog information signal is not so high, 12 switches S
Before all of 1 to S12 are turned off, the output of the adder 2 becomes lower than the predetermined value VR = VM and the output of the comparator 49 returns to the low level. Therefore, when the output of the comparator 49 returns to the low level, the switch 52 is turned off, the shift operation of the shift register 50 is stopped, and the state before the stop is maintained. Therefore, the level-limited analog dither signal is automatically supplied to the adder 2 so that the output of the adder 2 does not exceed the maximum allowable input VM. In addition,
Even if the output of the adder 2 becomes higher than VM during a part of one sampling period, it immediately becomes lower than VM, so that an appropriate A / D conversion output can be obtained.

[0016]

[Second Embodiment] A / A of the second embodiment shown in FIG.
The D converter will be described. However, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Also in this device, similarly to the device of FIG. 1, an information analog signal input line 1, a dither generator 3, an adder 2, an analog information signal level determination circuit 10, and a 16-bit A / D converter 1
1, a subtractor 13 is provided. However, the second A / D converter 12 in FIG. 1 is omitted. Instead of this
The A / D converter 11 is used in a time division manner, and both the dither addition information signal and the dither signal are converted into digital signals by the same A / D converter 11. In order to perform the time division control, the device of FIG. 2 has a gate circuit 15, a memory 16 and a sampling gate circuit 17. Although not shown, a sample and hold circuit for the information signal and the dither signal and a control circuit for performing time division multiplexing control are of course provided.

In the system of FIG. 2, only the dither signal is added to the adder 2 when the information signal is blocked by the gate 15.
Is input and is output as is. Meanwhile, gate 15
When is open, both the information signal and the dither signal are input to the adder 2 and an addition output is obtained. As a result, the A / D converter 11 performs A / D conversion on the dither addition information signal and the dither signal in a time division manner.

The memory 16 temporarily stores the digital dither signal, and outputs the dither signal in synchronization with the period in which the digital dither addition information signal is input to the subtractor 13. The sampling gate 17 extracts only the information signal. In addition,
The decision circuit 10 and the dither generator 3 are configured and operate in the same manner as in FIG.

[0019]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) A time division multiplex signal forming circuit may be provided on the output side of the adder 2. (2) The dither addition information signal may be written in the memory 16. (3) A gate circuit for inputting only the necessary dither addition information signal and dither signal to the subtractor 13 may be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an A / D conversion device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an A / D conversion device of a second embodiment.

[Explanation of symbols]

 1 Input Line 2 Adder 3 Dither Generator 9 Level Control Circuit 10 Analog Information Signal Level Judgment Circuit 11 A / D Converter

Claims (1)

[Claims] 1. An input line for an analog information signal, a digital dither generator for generating digital dither in parallel bit format, and a digital-analog conversion for converting the digital dither generated by the digital dither generator into analog dither. A plurality of switches connected to a multi-bit dither transmission line between the digital dither generator and the digital-to-analog converter; an analog information signal on the input line;
An adder for adding the analog dither output from the analog converter, an analog dither addition information signal obtained from the adder, and an analog dither obtained from the digital-analog converter, as a digital dither addition information signal. Connected to the control terminals of the plurality of switches; an analog / digital conversion means for converting into digital dither, a subtracter for subtracting the digital dither from the digital dither addition information signal obtained from the analog / digital conversion means, A plurality of output terminals, the plurality of output terminals being associated with the plurality of switches so as to sequentially block transmission from the upper bits of the digital dither generated by the digital dither generator as the shift operation proceeds. Drive shift register and the shift register A clock signal supply means for supplying a clock signal for operating the output of the adder and a reference value, and a comparison output indicating that the output of the adder is higher than the reference value to the shift register. An analog-digital conversion device comprising: a comparator that controls the clock signal supply means so as to cut off the supply of the clock signal.