JP2828444B2 - Encoding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for encoding an image signal such as a television signal, and more particularly, to encoding an image signal with high efficiency by utilizing characteristics of the image signal. The present invention relates to an encoding device for encoding. 2. Description of the Related Art Conventionally, when encoding an image signal such as a video signal, first, an analog video signal is A / D-converted into, for example, 8-bit digital data per sample to obtain an 8-bit video. For example, there is a method of compressing an image signal by predictively encoding data by applying, for example, a previous value difference encoding method or the like, and nonlinearly quantizing the data into, for example, 4-bit difference data. FIG. 7 shows an example of the nonlinear quantization characteristic. The horizontal axis represents the difference level Δ from −255 to +255, and the vertical axis represents the case where, for example, a mid-tread type nonlinear quantization is employed. The non-linear quantization level Δ 'of 15 representative values from -7 to +7 is shown. Regarding the differential data already obtained by the above-mentioned nonlinear quantization by the applicant of the present application, for example, two consecutive 4-bit differential data are set as one set to be 8-bit data, and the DC and low-frequency components are suppressed. There has been proposed an encoding device that converts data into 8-bit conversion data having a bit pattern as described below. FIG. 8 is a diagram for explaining the concept of the above-mentioned proposal, in which, of the two nonlinear quantized difference data values of 4 bits each, the difference data value Δn _{−1 in time} is taken on the horizontal axis,
Taking the difference data value delta _n temporally subsequent to the vertical axis. Here, only the first quadrant is shown, and the lattice shown by the solid line shows the nonlinear quantization characteristics shown in FIG. 7 independently on the horizontal axis and the vertical axis. Points existing in a region surrounded by the grid, as shown in FIG. 8 _{(Δ n-1, Δ n} ) (- 255 ≦ Δ n-1 ≦ 255, -255
≦ Δ _n ≦ 255) is (i, j) (− 7 ≦
i ≦ 7, −7 ≦ j ≦ 7). Therefore, when represented in two dimensions in this way, all two sets of two difference data of 4 bits each are 15 × 15 = 255.
Assigned to one of the regions. The above proposal makes use of this, and the 8-bit code 256
Among the types, for example, in the case of NRZ (Non Return to Zero) modulation, 255 pieces of conversion data having a bit pattern whose absolute value of a CDS (Cordword Digital Sum) is as small as possible are made to correspond to these (i, j) conversion data. ing. In other words, the remaining 31 converted data can be assigned so as to have a bit pattern with a large absolute value of the CDS. Therefore, these 31 converted data are also used as unused data. Trying to suppress the DC and low frequency components of the data sequence. The CDS represents the sum of each bit in a single code when the level “1” in each bit of the data pattern is “+1” and the level “0” is “−1”. The CDS is zero when the sum of the numbers "" and "0" is equal. Next, how the 225 conversion data selected from the 256 bit patterns correspond to (i, j) will be described. As a basic idea, an 8-bit data pair is formed by combining two consecutive 4-bit quantized difference value data obtained by performing the above non-linear quantization, and an 8-bit data pair (i, j) is formed. Conversion data having a small absolute value of the CDS is assigned preferentially from a place having a high appearance frequency. FIG. 9 shows the appearance frequency of the difference value in the general standard image information signal. The difference value is converted into a distribution of the quantized difference value after nonlinearly quantizing, and the above (i, j) Assign conversion data. When NRZ modulation is considered to be performed, the 8-bit unused data is preferably a bit pattern in which “0” and “1” are continuous, that is, as shown below. 18 conversion data of group A, B, C and D and E
In addition, a total of 31 pieces of conversion data of 13 pieces of conversion data out of the 16 pieces of conversion data of the F group may be adopted. Further, as the bit pattern of the conversion data to be used of 8 bits, there are four bits each of “1” and “0” among all the bits of the conversion data (CDS = 0, ₈ C ₄ = 70).
), "1" is 3 bits, "0" is 5 bits, and "1" is 5 bits
Bit and “0” each with 3 bits (CDS = ± 2, ₈
C ₃ + ₈ C ₅ = 112 pieces), "1" is 2 bits, "0" is 6 bits and "1" is 6 bits, "0" that there are two bits (CD
S = from among _{± 4, 8 C 2 + 8} C 6 = 56 pieces), but excluding the 13 pieces of conversion data extracted from the E and F groups in total
225 codes should be used. [Problems to be Solved by the Invention] However, in the encoding device as described above,
Once the conversion data of the CDS with a relatively high appearance frequency is output immediately after the conversion data of the CDS with a low absolute value and a large absolute value is output, the converted data sequence It takes a relatively long time to settle to the original zero level with the DSV (Digital Sum Value) fluctuating, and if such a state continues for a long time, a DC or low-frequency component is generated. When transmitting a data stream, these direct current or low frequency components are very difficult to transmit on a transmission path such as a magnetic recording / reproducing apparatus, and thus cause a data transmission error or the like. An object of the present invention is to solve the above problems and to provide an encoding device capable of encoding an image signal with high efficiency with a simple configuration. [Means for Solving the Problem] An encoding apparatus according to the present invention encodes a difference value signal between adjacent sample point information in an image signal and outputs an encoded signal. Output means for simultaneously outputting a plurality of encoded signals output as the plurality of encoded signals, and the same number of encoded signals simultaneously outputted from the output means as the plurality of encoded signals corresponding to the combination of the plurality of encoded signals. A conversion unit that converts and outputs a converted signal having less DC and low-frequency components of bits, and a bit corresponding to a combination of some of the plurality of encoded signals and having the same number of bits as the plurality of encoded signals and different from the converted signal. A correction signal generating means for outputting a correction signal having a pattern, and detecting a digital sum value (DSV) variation of the converted signal output from the converting means, and outputting the correction signal from the correction signal generating means in accordance with the DSV variation. Is obtained by a that the correction signal output control means. [Operation] With the above configuration, a plurality of continuous encoded signals can be reduced in DC and low frequency components without adding redundant bits according to a combination of differential value encoded signals between a plurality of consecutive adjacent sample point information. It can be converted to a converted signal, and can further suppress DSV fluctuation in the converted signal sequence. EXAMPLES Hereinafter, the present invention will be described using one example of the present invention. FIG. 1 shows an embodiment of an encoding apparatus to which the present invention is applied. An analog image signal such as a video signal input to the terminal 1 is converted into 8-bit digital video data by the A / D converter 2 and then input to the positive input terminal of the subtractor 3. To the negative input terminal of the subtractor 3, 8-bit prediction data from the predictor 7 is input, and the subtracter 3 outputs 8-bit prediction error data. The 8-bit prediction error data of the subtracter 3 is nonlinearly quantized by the nonlinear quantizer 4 into 4-bit quantized difference value data according to the above-described characteristics. The quantized difference value data output from the non-linear quantizer 4 together with the quantized difference value data delayed by the one-data period delay unit 8 is converted into an 8-bit parallel quantized difference value data sequence by the data converter 9. Is converted into converted data having a bit pattern in which DC and low frequency components of the same number of bits (8 bits) are suppressed in accordance with the above-described concept. On the other hand, the quantized difference value data output from the non-linear quantizer 4 is transmitted to a representative value setter 5 having characteristics opposite to those of the non-linear inverse quantizer 4 for non-linearly quantizing a 4-bit signal into an 8-bit signal. Is also entered. This representative value setting device 5 is an adder
6, a well-known local decoder is constructed together with the predictor 7, and the accumulation of quantization errors of the prediction error signal is prevented by inputting the 8-bit prediction error data of the predictor 7 to the negative input terminal of the subtractor 3. . The 225 types of conversion data obtained by the data converter 9 are as follows:
Switch A terminal A, DSV calculator 10 and pattern discriminator 1
Entered into 1 respectively. The DSV calculator 10 calculates the fluctuation of the DC component by accumulating the number of “1” and “0” of the converted data signal input up to the present, and inputs the signal DSV0 indicating the result to the calculation control circuit 12 I do. The arithmetic control circuit 12 performs control according to a control procedure as shown in FIG. In the pattern discriminator 11, for example, as shown in FIG.
The 8-bit conversion data output from the data converter 9 is the unused 3 bits among the 8-bit conversion data (256 types).
It is determined whether or not the converted data corresponds to one piece of converted data (the absolute value of the CDS has a large bit pattern as described above). Here, as the conversion data to which the unused conversion data is assigned, for example, the above-described area (i, j) = (− 2 to +
2, -2 to +2), (± 3,0), (0, ± 3), (3,3),
31 points (-3, -3) are selected. Bit patterns of 31 unused conversion codes may be assigned to the extraction points in FIG. 2 so that CDS values having different polarities alternately exist as much as possible. Further, not only one piece of unused conversion data is assigned to one piece of conversion data but also a plurality of pieces of unused conversion data given to each piece of conversion data to be compared in the pattern discriminator 11. Good. That is, by assigning two types of unused conversion data, positive and negative, having the same absolute value of the CDS to the target conversion data, the unused conversion data having a DSV of zero or the closest to zero is obtained. Can be appropriately selected. FIG. 3 shows conversion data extraction points to which two pieces of unused conversion data are assigned, respectively. The conversion data to be converted is a pair of quantized difference value data (i , j) = (− 2 to + 2, −2 to
+2), (± 2,0), (0, ± 2), (2,2), (−2, −
2) The 15 pieces of converted data, of which 30 pieces of unused converted data are to be applied, and the remaining one piece of unused converted data is also targeted.
It may be assigned to another conversion data located near 15 conversion data. The pattern discriminator 11 shown in FIG. 1 will be described in detail below as assigning a plurality of unused conversion data to one conversion data. When it is determined that the conversion data input to the pattern determiner 11 is conversion data to which a plurality of unused conversion data are assigned, a determination signal A indicating the determination result and a DSV control signal corresponding to the input conversion data are provided. The pattern signals 1 and 2 of the two unused conversion data are supplied to the arithmetic and control circuit 12. The arithmetic control circuit 12 sends the DSV correction output signal B, the pattern signal of the unused conversion data for the selected DSV control, and the latch control pulse signal to the DSV arithmetic unit 10 according to a flowchart described later, The signals are input to the input terminal B of the circuit 13 and the latch circuits 14 and 15, respectively. Next, the control operation of the arithmetic and control circuit 12 will be described with reference to the flowchart shown in FIG. First, the switch 13 is connected to the A side (step 1), a latch operation pulse signal is supplied to the latch 14 at the timing shown in FIG. 5A, and the output conversion data of the data converter 9 is latched (step 2). Next, a signal DSV0, which indicates the DSV value in the conversion data string output from the data converter 9 at this time, is
Obtained from the DSV operation circuit 10 (step 3), the signal DSV0 indicates
It is determined whether the DSV value is “0” or any other value (step 4). DS
If the V value is "0", the process proceeds to step 11, where the latch circuit generates a pulse signal having the timing shown in FIG.
15 is operated, and the converted data output from the latch circuit 14 is latched as it is. On the other hand, if the DSV value is not “0” at step 4, the conversion data latched by the latch circuit 14 is converted from the discrimination signal (signal A indicating) obtained by the pattern discriminator 11 to DSV at step 5.
It is determined whether or not the unused conversion data for control is the conversion data to be allocated. If the conversion data is not the conversion data to be allocated, the process proceeds to step 11, where the latch circuit 15 is switched to the control circuit in FIG.
Is operated at the timing of
Each unused conversion data is generated by adding the unused conversion data selected by the corresponding pattern signals 1 and 2 in step 6 to the DSV value obtained from the signal DSV0 one data period before from the DSV calculator 10. The DSV value (DSV1, DSV2) is calculated. Next, the DSV value of the current signal DSV0 and D
Compare the SV values DSV1 and DSV2,
It is determined whether V2 has a DSV suppression effect of bringing the DSV value closer to zero as compared with the current DSV value (step 7). Both (D
SV1 and DSV2), if there is no effect, proceed to step 11, and if there is an effect, switch switch 13 to B side in step 8,
Then, unused conversion data corresponding to the effective pattern signal 1 or 2 is supplied to the B-side input terminal of the switch 13 (step 9). Next, a latch pulse signal is given to the latch circuit 14 at the timing shown in FIG. 5C to latch unused conversion data corresponding to the code pattern signal 1 or 2 from the switch 13. Next, in step 11, the latch circuit 15 is operated at the timing shown in FIG. 5d to latch unused conversion data output from the latch circuit 14. Note that, as shown in FIG. 5B, the period in which the waveform is at the high level corresponds to the period during which the arithmetic and control operations from step 3 to step 9 in the arithmetic control circuit 12 are performed. Further, in the present embodiment, the case where two consecutive 4-bit quantized difference value signals are converted into an 8-bit coded signal has been described as an example. However, by providing a plurality of delay circuits, m consecutive n-bit The present invention can also be applied to a case where a coded difference value signal is converted to an m × n-bit coded signal, in which case the DC and low-frequency component suppression effect is further improved. In the above embodiment, one or two unused conversion data are assigned to one target conversion data for DSV control. However, the present invention is not limited to this, and three or more types may be assigned. In this case, the DSV suppression effect is further improved. In FIGS. 2 and 3, unused conversion data for DSV control is assigned to conversion data having a relatively high frequency of occurrence, and the control for lowering the once generated high DSV value fluctuation is actively performed.
Conversely, the same effect can be obtained by assigning these unused conversion data for DSV control to conversion data having a slightly lower frequency for the purpose of preventing the DSV value from fluctuating in advance. Furthermore, in the above embodiment, NRZ modulation is premised, but the same can be said for NRZI modulation. Further, as shown in FIG. 6, a conversion code assigned to a portion (hatched portion in the drawing) which never occurs in the area (i, j) is also used as unused conversion data for DSV control. The effect of DSV suppression can be further improved. According to this figure, a total of six pieces of conversion data including the third quadrant can be obtained as unused conversion data.
Further, according to this concept, instead of mid-tread type nonlinear quantization, (i, j), (i = −8, −7,... −1,1,.
= −8, −7,…, −1,1,…, 8) Even in the mid-riser type nonlinear quantization using a total of 256 transformed data, non-occurring transformed data of the 256 transformed data is DSV The present invention can be applied by using it as unused conversion data for control. [Effects of the Invention] As described above, according to the present invention, an image signal can be encoded so that DSV can be suppressed very effectively, and data can be reliably reproduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an encoding apparatus to which the present invention is applied, and FIGS. 2 and 3 are two successive quantized difference value data after nonlinear quantization. FIG. 4 is a flowchart showing an operation of the present embodiment, FIG. 5 is an operation timing chart of main parts in the present embodiment, and FIG. FIG. 7 is a diagram showing combinations that do not occur among combinations of two consecutive quantized difference value data, FIG. 7 is a diagram showing an example of nonlinear quantization characteristics, and FIG. 8 is two successive quantized differences after nonlinear quantization FIG. 9 is a diagram illustrating an example of a combination of value data pairs. FIG. 9 is a diagram illustrating an example of the appearance frequency of the quantized difference value data. 10: DSV calculator, 11: Pattern discriminator, 12: Calculation control circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomohiko Sasaya 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (56) References JP-A-61-99419 (JP, A) (58) Survey Field (Int.Cl. ⁶ , DB name) H04N 7/24-7/68 H04N 1/41-1/419

Claims (1)

(57) [Claims] Encoding means for encoding a difference value signal between adjacent sample point information in an image signal and outputting an encoded signal; and output means for simultaneously outputting a plurality of encoded signals continuously output from the encoding means. Converting the plurality of coded signals output simultaneously from the output means into a converted signal having the same number of bits of DC and low frequency components as the plurality of coded signals corresponding to the combination of the plurality of coded signals, and outputting the converted signals; Conversion means, and a correction signal generation means for outputting a correction signal corresponding to a combination of some of the plurality of encoded signals and having the same number of bits as the plurality of encoded signals and having a bit pattern different from that of the converted signal. A correction signal output control means for detecting a Digital Sum Value (DSV) variation of the conversion signal output from the conversion means and outputting the correction signal from the correction signal generation means in accordance with the DSV variation. Encoding device, characterized in that was e.