JPS6333084A - Encoder - Google Patents

Abstract

PURPOSE:To suppress a DSV fluctuation by encoding a difference value signal between information at adjacent sample points and converting into a converting signal having little direct current and low frequency component according to the combination thereof. CONSTITUTION:When converting data inputted to a pattern discrimination device 11 is discriminated to be the converting data to which plural unused converting data is assigned, a discrimination signal A indicating a discrimination result and the pattern signals 1 and 2 of the two unused converting data for controlling a DSV corresponding to the input converting data are supplied to an arithmetic control circuit 12. In the arithmetic control circuit 12, the unused converting data selected by the pattern signals 1 and 2 is respectively added to the DSV value obtained from a signal DSVO before one data period from a DSV computing element 10, thereby, the respective DSV values(DSV1, DSV2) when the respective unused converting data is generated are operated. Thereby, a picture signal can be encoded so as to suppress the DSV.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a device for encoding an image signal such as a television signal, and in particular to a device for encoding an image signal with high efficiency by utilizing the characteristics of the image signal. The present invention relates to an encoding device for encoding.

[Prior Art] Conventionally, when encoding an image signal such as a video signal, the analog video signal is first A/D converted into digital data with 8 bits per sample, and the resulting 8-bit video is converted into digital data. There is a method of compressing an image signal by predictively encoding data using, for example, a previous value differential encoding method, and nonlinearly quantizing the data into, for example, 4-bit difference data.

FIG. 7 shows an example of the nonlinear quantization characteristic, and the horizontal axis is the difference level Δ from −255 to +255.
, and the vertical axis indicates the nonlinear quantization level Δ' of representative values of 15 levels from -7 to +7 when, for example, mid-tread type nonlinear quantization is adopted.

Regarding difference data obtained by nonlinear quantization as already described above by the applicant, for example, two consecutive
An encoding device has been proposed that converts a set of 4-bit difference data into 8-bit data and converts this into 8-bit converted data having a bit pattern such that direct current and low frequency components are suppressed.

FIG. 8 is a diagram for explaining the concept of the above proposal,
The temporally previous difference data value Δ of two nonlinear quantized difference data values of 4 bits each. The horizontal axis represents the difference data value Δ later in time. is taken on the vertical axis. Here, only the first quadrant is shown, and the lattice shown by solid lines represents the nonlinear quantization characteristics shown in FIG. 7 independently on the horizontal and vertical axes.

As shown in Figure 8, points (Δn-1.Δn) (-255≦Δ, -!≦2
55, -2s5≦Δ. ≦255) corresponds to a region of (i, j) (-7≦i≦7.-7≦j≦7) by nonlinear quantization. Therefore, when expressed two-dimensionally in this way, all two successive sets of difference data of 4 bits each are allocated to any one of 15×15=225 areas.

The above proposal uses this to create an 8-bit code of 256
Among the types, for example, NrlZ (Non l1etur
nt.

In the case of Zero) modulation, it is
225 pieces of conversion data having a bit pattern with a small absolute value of wordDi3italSum) are converted into these (i,
It corresponds to the conversion data of j). In other words, the remaining 31 converted data can be assigned to have a bit pattern with a large absolute value of CDS, so these 31 converted data are also considered unused data, and by assigning the converted data in this way, the I am trying to suppress the DC and low frequency components of the data string.

In addition, this CDS represents the sum of each bit in the car code when the level "1" in each bit of the data pattern is "+1" and the level "0" is "-1", and it is "1". When the sum of the numbers of ``'' and the sum of the numbers of ``0'' are equal, the CDS becomes zero.

Next, 22 bit patterns are selected from among the 256 bit patterns.
How five pieces of conversion data are made to correspond to (i, j) will be explained.

The basic idea is that two successive 4-bit difference data that have been subjected to the nonlinear quantization described above constitute an 8-bit data pair, and each 8-bit data pair (i, j)
Conversion data with a small absolute value of CDS is assigned preferentially from the location where the occurrence frequency is high.

FIG. 9 shows the above (ij) in a general standard image information signal.
This shows the frequency of appearance. Furthermore, when considering NRZ modulation, the 8-bit unused data should preferably be a bit pattern in which °°0'' and °1'' are consecutive, that is, A; 00000000) 1 as shown below. Piece B, 11111
111) 1 piece of 18 converted data in groups A, B, C and D and 13 of 16 converted data in groups E and F
It is sufficient to employ a total of 31 pieces of conversion data.

Furthermore, the bit pattern of the 8-bit conversion data used is one in which 4 bits each of "1" and II OI+ exist among all the bits of the conversion data (CDS
= O, ac4 = 70 pieces), “1” is 3 bits, “o”
” is 5 bits and °°1” is 5 bits.

0” exists in 3 bits (CDS = ±2.8
C3+ac5=112 pieces), “°1” is 2 bits, “°
There are 6 bits of 0", 6 bits of °°1", and 2 bits of 0" (CDS = ±4,8C2+6CG
= 56 codes), excluding the 13 converted data extracted from the E and F groups, resulting in a total of 225 codes.

[Problems to be Solved by the Invention] However, in the above-mentioned encoding device, immediately after the converted data of a CDS with a low frequency of appearance and a large absolute value is output, a CDS with a relatively high frequency of appearance is output. When zero conversion data is output continuously, DSV (Digital Sum) is applied to the output conversion data string.
It takes a relatively long time to settle down to the original zero level while the value (Value) remains fluctuating, and if this state continues for a long time, direct current or low frequency components are generated, so it is difficult to transmit the converted data string. In this case, it is very difficult to transmit these direct current or low frequency components through a transmission line for magnetic recording and reproducing, for example, causing data transmission errors and the like.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an encoding device that can highly efficiently encode image signals with a simple configuration.

[Means for Solving the Problems] The encoding device of the present invention includes an encoding means for encoding a difference value signal between adjacent sample point information in an image signal and outputting an encoded signal, and a continuous output signal from the encoding means. an output means for simultaneously outputting a plurality of encoded signals outputted from the output means; Conversion means for converting bits into a converted signal with less DC and low frequency components and outputting the converted signal, and corresponding to a partial combination of the plurality of encoded signals, the same number of bits as the plurality of encoded signals, but different bits from the converted signal. A correction signal generation means for outputting a correction signal having a pattern, and a correction method for detecting Digital Sum Value (DSV) fluctuations of the conversion signal output from the conversion means, and outputting a correction signal from the correction signal generation means in accordance with the SV fluctuation. It is equipped with a signal output control means.

[Operation] With the above configuration, a plurality of consecutive encoded signals are generated with few DC and low frequency components without adding redundant bits according to the combination of the difference value encoded signals between the plurality of consecutive adjacent sample point information. It can be converted into a converted signal, and furthermore, it is possible to suppress DSV fluctuations in the converted signal sequence.

[Example] Hereinafter, the present invention will be explained using one embodiment of the present invention.

FIG. 1 shows an embodiment of an encoding device to which the present invention is applied.

An analog image signal such as a video signal inputted to a terminal 1 is converted into 8-bit digital video data by an A/D converter 2, and then inputted to a positive input terminal of a subtracter 3. The 8-bit prediction data from the predictor 7 is input to the negative input terminal of the subtracter 3, and the subtracter 3 outputs 8-bit prediction error data.

The 8-bit prediction error data from the subtracter 3 is non-linearly quantized into 4-bit difference data by the non-linear quantizer 4 in accordance with the characteristics described above. The difference data outputted from the nonlinear quantizer 4 is input to the data converter 9 as an 8-bit parallel difference data string together with the difference data delayed by the 1-data period delay device 8, and there, as described above, According to the idea, DC and low frequency components with an equal number of bits (8 bits) are converted into converted data having a suppressed bit pattern.

On the other hand, the difference data output from the nonlinear quantizer 4 is
The signal is also input to a representative value setter 5, which has characteristics opposite to those of the nonlinear inverse quantizer 4, which nonlinearly quantizes a 4-bit signal into an 8-bit signal. This representative value setter 5 includes an adder 6. A well-known local decoder is configured together with the predictor 7, and the 8-bit prediction error data of the predictor 7 is input to the negative input terminal of the subtracter 3, thereby preventing the accumulation of binary errors in the prediction error signal.

225fi obtained with data converter 9! ! The converted data of the same type is input to the terminal A of the switch 13, the DSV calculator 10, and the pattern discriminator 11, respectively.

The DSv calculator 1O has so far been able to manually perform the conversion de=-
> Calculates the fluctuation of the DC component by accumulating the number of °bi and °0'° of the signal, and generates a signal osvo that shows the result.
is input to the arithmetic control circuit 12. The arithmetic control circuit 12 performs control according to a control procedure as shown in FIG.

In the pattern discriminator 11, for example, as shown in FIG.
The 8-bit conversion data output from the data converter 9 is converted into 31 unused conversion data (a bit pattern with a large absolute value of CDS as described above) out of all 8-bit conversion data (256 types). ) is determined whether the converted data corresponds to the following. Here, for example, considering the characteristics of a general image signal, the above-mentioned area (i, j) is used as the conversion data to which unused conversion data is assigned.
= (-2~+2.-2~+2), (upper 3°0), (0,
±3), (3,3).

We have selected 31 points of (-3, -3). The bit patterns of the 31 unused conversion codes are C with different polarities.
The DS values may be assigned to the extraction points in FIG. 2 so that they exist alternately as much as possible.

In addition, for each target conversion data to be discriminated by the pattern discriminator 11, not only one unused conversion data is assigned to one conversion data, but also a plurality of unused conversion data are assigned. But that's fine. That is, CDS
By assigning two types of unused conversion data, positive and negative, with the same absolute value of to the target conversion data,
From among these unused conversion data, one whose DSV is closest to black or flat can be selected as appropriate.

FIG. 3 shows extraction points of converted data to which two unused converted data are assigned, and the converted data is the difference data pair (i, j) before conversion by the data converter 9. =(-2~+2.-2~+2
), (upper 2°0), (0, ±2), (2,2),
Of the 15 old conversion data (-2, -2), 30 of the unused conversion data will be applied to these, and the remaining 1 piece of unused conversion data will be applied to these. It may also be assigned to other converted data located near the 15 target converted data.

The pattern discriminator 11 shown in FIG. i1 will be described in detail below, assuming that it allocates a plurality of unused conversion data to one piece of conversion data.

When the conversion data input to the pattern discriminator 11 is determined to be conversion data to which a plurality of unused conversion data are allocated, a determination signal A indicating the determination result and a DSV control signal corresponding to the input conversion data are transmitted. Two pattern signals 1 and 2 of unused conversion data are supplied to the calculation 1MJ control circuit 12. The arithmetic control circuit 12 sends the DSV correction output signal B1, the pattern signal of unused conversion data selected for DSV control, and the latch control pulse signal to the OSV arithmetic unit IO, respectively, according to a flowchart as described later. It is input to input terminal B of switch circuit 13 and latch circuits 14 and 15, respectively.

Next, the control operation in the arithmetic control circuit 12 will be explained with reference to the flowchart shown in FIG.

First, connect the switch 13 to the A side (5tepl),
A latch operation pulse signal is supplied to the latch 14 at the timing shown in FIG. 5a, and the output conversion data of the data converter 9 is latched (step 2). Next, a signal DSVO+ indicating the DSV value in the converted data string output from the data converter 9 at this point is obtained from the OSV calculation circuit IO (5
step 3), the OSV value indicated by the control signal DSVO (7) is
It is determined whether it is “O” or something else (step 4).

If the DSν value is °°0'', the process proceeds to 5tepH, and then the latch circuit 15 is operated by the next generated pulse signal with the timing shown in FIG.
Latch the conversion data output as is.

On the other hand, if the DSV value is not “0” at 5tep4, s
In step 5, the unused conversion data for OSV control is determined from the discrimination signal (signal A indicating) obtained by the pattern discriminator 11, and if the conversion data currently latched in the latch circuit 14 is not the target conversion data, the conversion data is 5 tepH. Then, the latch circuit 15 is operated at the timing shown in FIG. By adding them to the DSV values obtained from the signal DSVO one data period ago from the i-counter 10, the DSV values (DSVI, DSV2) when each unused conversion data is generated are calculated.

Next, the current DSV value of the signal osvo is compared with the DSV values DSVI and DSV2 obtained by these calculations, and the current DSV value is
It is determined whether there is an effect of DSV suppression that brings the tlSV value closer to the drop than the tlSV value (step 7). Both sides (DSV
If neither I, DSV2) is effective, proceed to 5tepH, and if it is effective, switch 13 at 5tep8.
is switched to the B side, and then unused conversion data corresponding to the effective pattern signal 1 or 2 is supplied to the B side input terminal of the switch 13 (step 9).

Next, at the timing shown in FIG. 5C, a latch pulse signal is applied to the latch circuit 14 to latch the unused conversion data corresponding to the code pattern signal 1 or 2 from the switch 13. Next, the latch circuit 15 is operated at 5 tepH at the timing shown in FIG. 5d to latch the unused conversion data output from the latch circuit 14.

Note that, as shown in Figure S5, the period in which the waveform is at a high level corresponds to the period in which the calculation control circuit 12 performs the calculation and judgment operations from 5tep3 to 5tep9.

In addition, in this embodiment, the case where two consecutive 4-bit quantized difference value signals are converted into an 8-bit encoded signal is shown as an example, but by providing a plurality of delay circuits, m consecutive n-bit quantized The present invention can also be applied to the case of converting a coded difference value signal into an mxn bit encoded signal, and in this case, the effect of suppressing direct current and low frequency components is further improved.

In the embodiment described above, one or two types of unused conversion data are allocated to one target conversion data for DSV control, but the invention is not limited to this, and three or more types may be allocated. In this case, the DSv suppressing effect is further enhanced.

In addition, in Figures 2 and 3, unused conversion data for DSV control was assigned to conversion data with a relatively high occurrence scalp, and active control was performed to reduce high DSV value fluctuations that once occurred. D the unused conversion data for DSV control in advance.
On the other hand, the same effect can be obtained by allocating to converted data that occurs with a slightly lower frequency for the purpose of preventing fluctuations in the SV value.

Furthermore, although the above embodiments were based on NnZ modulation, the same holds true even when NnZI modulation is also performed.

Furthermore, as shown in FIG. 6, by using it in the region (i, j) as a negative signal, the effect of suppressing DSV can be further improved. According to this diagram, a total of six pieces of conversion data including the third quadrant can be obtained as unused conversion data. Furthermore, if we follow this idea, instead of the mid-tread type nonlinear quantization, (i, J), (i = -
8,-7,...,-1,1,...,a,j=-8,
-7, . The present invention can be applied by using it as unused conversion data for control.

[Effects of the Invention] As described above, according to the present invention, an image signal can be encoded so that DSV can be suppressed very effectively, and data can be reliably reproduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an encoding device to which the present invention is applied. Figure 4 is a flowchart showing the operation of this embodiment, Figure 5 is an operation timing chart of the main parts of this embodiment, and Figure 6 is a diagram showing a combination of two consecutive difference data after non-linear quantization. FIG. 7 is a diagram showing an example of nonlinear quantization characteristics; FIG. 8 is a diagram showing an example of a combination of two consecutive difference data pairs after nonlinear quantization; FIG. 9 is a diagram showing an example of the combination of two consecutive difference data pairs after nonlinear quantization; FIG. 7 is a diagram illustrating an example of the frequency of appearance of difference data. 10.I) SV ffi calculator, 11... Pattern discriminator, 12... Arithmetic control circuit. Figure 5 Δn Procedural amendment 1, case display Patent application Sho Ei 1-174728 No. 2, invention title encoding device 3, person making the amendment Relationship with the case Patent applicant (100) Canon Co., Ltd. 4, agent 6th Seiko Building, 3rd floor 7, 5-1-31 Akasaka, Minato-ku, Tokyo 107, Japan Contents of amendment (1) Page 6, line 7, page 11, line 8 of the specification. Page 11, line 9, page 11, line 10, page 11, line 1
Line 1, page 11, line 16, page 13, line 20, page 19, line 20, page 20, line 6, page 20, line 10
line and page 20, page 20, line 12 r difference” respectively.
Quantized difference value”. (2) Delete "the above" on page 6, line 12. (3) Correct the 13th line of the same page as follows. "This shows the frequency of appearance of the difference value, but the difference value is converted to a distribution of quantized difference values after nonlinear quantization, and the converted data is assigned to the above (i, j). Also," (4) Also perform rNRZI modulation on page 18, line 14.
"perform rNRZI modulation". (5) Amend Figure 2 of the drawings as shown in the attached sheet. C correction drawing)

Claims (1)

[Claims] An encoding means for encoding a difference value signal between adjacent sample point information in an image signal and outputting an encoded signal; and an output means for simultaneously outputting a plurality of encoded signals successively output from the encoding means. , converting a plurality of encoded signals simultaneously output from the output means into a converted signal having the same number of bits as the plurality of encoded signals and having fewer DC and low frequency components according to the combination of the plurality of encoded signals, and outputting the converted signal. and a correction signal generating means for outputting a correction signal corresponding to a partial combination of the plurality of encoded signals and having the same number of bits as the plurality of encoded signals and a bit pattern different from the converted signal. , D of the conversion signal output from the conversion means
An encoding device comprising: correction signal output control means for detecting a change in digital sum value (DSV) and causing the correction signal generation means to output the correction signal in accordance with the DSV change.