JPH07107980B2 - Digital-to-analog converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital-analog (D / A) conversion device for converting a digital signal into an analog signal with addition and calculation of a dither.

[Conventional technology]

If the linearity of the relationship between the input and output of the D / A converter is poor, waveform distortion will occur and harmonic noise will occur. In order to reduce the noise due to the non-linearity of the D / A converter, the digital dither is added to the digital information signal (data) input to the D / A converter, D / A conversion is performed, and then analog A method of removing (subtracting) the dither component included in the signal is already known. If the dither is added according to this method, even if the digital information signal that repeatedly outputs the same analog waveform is D / A converted, the same operation is not performed and the non-linear distortion is averaged. Occurrence of jarring noise caused by non-linear distortion is reduced.

By the way, in order to easily and accurately perform the addition and subtraction of the dither as described above, as shown in FIG. 5, the dither addition information signal and the dither are time-division-multiplexed, and the same D / A converter (1 ) Is converted into an analog signal, and one of the time-division multiplexed signals (for example, dither) is extracted and held by the sample and hold circuit (2), and the other signal is time-division multiplexed (for example, dither addition information signal). ) Is input to the analog subtractor (3) in synchronism with the output period, the dither is calculated from the dither addition information signal, and only the information signal is extracted by the deglitch circuit (4). Have been proposed.

[Problems to be solved by the invention]

In the system of FIG. 5, a sample and hold circuit (2)
Cannot completely hold the output of the D / A converter (1) and send it to the subtractor (3). Therefore, it is necessary to provide resistors (5) and (6) on the input line of the subtractor (3) and adjust the level so as to completely subtract the dither. If this level adjustment is incomplete, it becomes impossible to sufficiently remove the dither by the subtractor (3), so that this level adjustment needs to be performed with high accuracy. Further, in the method shown in FIG. 5, since the D / A converter (1) is a voltage type such as PCM53JP-V manufactured by Burr Brown Co., the settling time for D / A conversion is 3 μsec. ,
At least 6 μs is required to perform D / A conversion of both the dither and the dither addition information signal, which is an obstacle to speeding up.

Therefore, an object of the present invention is to provide a digital-analog conversion device that can easily and accurately perform dither subtraction and that can be easily speeded up.

[Means for solving problems]

The present invention for solving the above problems and achieving the above object will be described with reference to the reference numerals of the drawings showing an embodiment. A digital information signal input circuit (11) and a digital dither generator (12) will be described. And the digital information signal supplied from the input circuit (11) and the digital dither generated by the dither generator (12) are added to form a digital dither addition information signal, and the digital dither addition information is generated. An adder / multiplexer circuit (13, 14) forming a time-division multiplexed signal of a signal and the digital dither, and a digital-analog converter for converting the time-division multiplexed signal obtained from the adder / multiplexer circuit into an analog signal Converters (15)
And a subtraction processing circuit (16) for obtaining an analog information signal by subtracting the analog dither from the analog dither addition information signal based on the analog time division multiplexed signal obtained from the digital-analog converter (15). A digital-analog conversion device comprising: a subtraction processing circuit (16) connected to an output line of the digital-analog converter (15) and turned on during a period in which the analog dither is output; Switch (S ₁ ) and an inverting input terminal are connected to the digital-analog converter (15) via the _first switch (S ₁ ) and a non-inverting input terminal is connected to ground. Operational amplifiers (17)
And a first capacitor (C _H1 ) connected between the inverting input terminal and the output terminal of the first operational amplifier (17),
A first resistor (R _f1 ) connected between the input side terminal of the first switch (S ₁ ) and the output terminal of the first operational amplifier (17) and the first switch (S 1). ₁ ) is connected to the input side terminal of the second switch (S ₂ ) which is turned on during the off period of the _first switch (S ₁ ) and the output side terminal of the second switch (S ₂ ). A third switch (S ₃ ) which is connected and is turned on during a period in which the dither addition information signal of the analog time division multiplexed signal is output, and an inverting input terminal of the third switch (S ₃ ). A second operational amplifier (18) connected to the input side terminal of the first switch (S ₁ ) through the second switch (S ₂ ) and having a non-inverting input terminal connected to the ground; is connected between the output terminal and the ground of the second switch (S _2), o the third switch (S ₃₎ Fourth switch which is turned in the period (S ₄₎
And a second capacitor (C _H2 ) connected between the inverting input terminal and the output terminal of the second operational amplifier (18),
A digital circuit comprising a second resistor (R _f2 ) connected between the input terminal of the third switch (S ₂ ) and the output terminal of the second operational amplifier (18). -It concerns an analog converter.

[Action]

The first switch (S ₁ ) acts as a switch for sampling the dither, and while the switch is on, the dither is extracted and sent to the first capacitor (C _H1 ).
The voltage of the first capacitor (C _H1 ) is the first resistance (R _f1 )
Is determined by the voltage ((I _D1 R _f1 ). During the output period of the dither addition information signal, the third switch (S ₃ ) is turned on, and during this period, the second switch (S ₂ ) is also turned on. because it is on, corresponding to the difference between the current I _D1 corresponding to the dither addition information signal output from D / a converter (15) (X '+ Y ') corresponding current I _D2 and dither the (Y ') The current is sampled and sent to the second capacitor (C _H2 ). Hold the first resistor (R _f1 ), the first capacitor (C _H1 ), and the first operational amplifier (17). The current ( _ID1 ) corresponding to the dither component present is added to the dither addition information signal (X '
+ Y ') It works so as to extract from the current I _D2 corresponding to. Since the first resistor (R _f1 ) acts as a feedback resistor at the time of sample-holding and also acts as a dither subtracting resistor, dither subtraction can be sufficiently performed without adjustment.

〔Example〕

Next, a D / A converter according to an embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

In FIG. 1, (11) is a 16-bit information signal input circuit, which is a circuit for supplying a digital information signal (X) corresponding to an audio signal. (12) is a digital dither generator consisting of a pseudo-random pulse generation circuit,
Supply dither (Y). The adder (13) connected to the input circuit (11) and the dither generator (12) is a 16-bit full adder and adds the dither (Y) with the information signal (X) to add the dither. The addition information signal (X + Y) is output. The time division multiplexing circuit (14) connected to the adder (13) and the dither generator (12) is composed of a multiplexer, and selects the dither addition information signal (X + Y) and the dither (Y) alternately, The division multiplexed signal (X + Y) + (Y) is output.

The D / A converter (15) connected to the multiplexing circuit (14) is a current type D / A composed of, for example, PCM53JG-I manufactured by Burr Brown Co.
Consists of a converter, digital multiple signal (X + Y) +
Analog multiplexed signal (X '+ Y') + corresponding to (Y) +
(Y ') is output as a current. Since the D / A converter (15) is a current type and does not have a current-voltage converter, the settling time of current output is about 350 nsec, which is extremely short.

(16) is a subtraction processing circuit according to the present invention, which has a first switch (S ₁ ) connected to the D / A converter (15) and one input terminal (inverting input terminal) of the first switch S 1. D through ₁
A first operational amplifier (17) connected to the A converter (15) and the other input terminal (non-inverting input terminal) thereof connected to the ground, and one input of the first operational amplifier (17) A first capacitor C _H1 connected between the terminal and the output terminal
And a first resistor R connected between the input terminal of the first switch S _{1 and} the output terminal of the first operational amplifier (17).
_f1 and a second switch connected to the input side terminal of the first switch S ₁ .
The switch S _2, and the third switch S ₃ that is connected to the second output terminal of the switch S _2, a fourth coupled between the second output terminal and the ground of the switch S ₂ The switch S ₄ and one input terminal (inverting input terminal) are connected to the input side terminal of the first switch S ₁ via the third switch S ₃ and the second switch S _2, and the other input terminal ( A second operational amplifier (18) whose non-inverting input terminal) is connected to the ground, and a second capacitor C connected between one input terminal and the output terminal of the second operational amplifier (18). _H2 and a second resistor _Rf2 connected between the input terminal of the _third switch _S3 and the output terminal of the second operational amplifier (18). The switch control circuit (19) is provided for on-off controlling the switches S ₁ to S _4.

Next, the operation of the apparatus shown in FIG. 1 will be described with reference to FIG.

When the time division multiplexed signal of the dither addition information signal (X + Y) and the dither (Y) is input to the D / A converter (15), each is converted into an analog signal, and t ₁ to t ₄ , t in FIG. _{7 to} t ₁₀
The current _ID1 indicating the analog dither (Y ') is output at
₄ ~t _7, t ₁₀ ~t ₁₁ in analog dither addition information signal (X '
The current _ID2 indicating + Y ') is output.

As shown in FIG. 2B, the first switch S ₁ is turned on at t ₂ to t ₃ and t _{8 to} t ₉ during the dither period, and the second switch S ₂ is turned on.
Turns on and off, contrary to the first switch S _{1 as} shown in FIG. 2 (C). The third switch S ₃ is turned on at _{t 5 ~t 6, t 11 ~t} 12 in the output period of the dither addition information signal as shown in FIG. 2 (D) (X '+ Y '), fourth The switch S ₄ is a third switch S _{3 as} shown in FIG. 2 (E).
On the contrary, it operates on and off.

Now, at t ₂ , when the first switch S ₁ is turned on, the first current I _D1 output from the D / A converter (15) changes to the first switch S 1.
₁ through which the first capacitor C _H1 is charged to saturation after a sufficient time, after which the first resistor R _f1
Current flows through. First capacitor C _H1 and first resistor R _f1
And are connected in parallel, so the first capacitor C
_H1 is charged to a value in response to I _D1 R _f1 . Then, at t ₃ , I _D1 R _f1 is held even when the first switch S ₁ is turned off. Since the inverting input terminal and the non-inverting input terminal of the operational amplifier (17) are in the marginal short state,
The potential of the inverting input terminal is also ground, so that the output voltage E _A of the operational amplifier (17) becomes −I _D1 R _f1 .

When the second switch S ₂ is turned on at t ₃ , the D / A converter (1
The output terminal of 5) is the second switch S ₂ and the third switch S ₃
This output current I since it is connected to the ground via
_D1 or I _D2 flows to ground. However, the output voltage E _A of the first operational amplifier (17) is held until t ₈ at which the first switch S ₁ is turned on again.

When the third switch S ₃ is turned on at t ₅ ~t _6, goes into the sampling state, current corresponding to the third switch S ₃ to the through connexion I _D2 -I _D1 flows into the second capacitor C _H2, the The voltage corresponding to I _D2 −I _D1 at the output terminal of the second operational amplifier (18)
E ₀ is obtained. FIG. 2 (F) shows the change of the output voltage E _0. During the sampling period of t _{5 to} t ₆ and t _{11 to} t ₁₂ , the voltage value changes according to the sample, and the voltage changes to the next sampling. It is held until the period.

In this manner, not only the first resistor R _f1 is used in the feedback resistor during the sampling of the current I _D1, since it is also used to subtract the resistance of the current I _D1, to perform accurate subtraction of I _D1 You can Next, this will be described in more detail. Even if the resistor (6) is adjusted in the conventional circuit shown in FIG. 5 so that the dither can be completely removed, the two resistors (5) and (6) of the D / A converter are then replaced. If there is a change in the temperature distribution on the circuit board on which it is placed, or if the two resistors (5) and (6) lose their balance due to aging, they pass through the resistors and enter the subtractor (3). The dither component of the input dither addition information signal and the dither component input to the subtractor (3) through the resistor (6) have different values, and the dither subtraction residue occurs. On the other hand, in the case of the D / A converter of the present embodiment shown in FIG. 1, the resistance R _f1 is the sample hold value I _D1 × R corresponding to the first current I _D1 indicating the dither component.
It is used not only to obtain _f1 but also to output the first current I _D1 when subtracting the first current I _D1 indicating the dither component from the second current I _D2 indicating the dither addition information signal. Has been done. That is, the resistor R _f1 is used both for holding the dither component and for subtracting the dither component. The holding of the dither component and the subtraction of the dither component described above are repeatedly executed within a short time as shown in FIG. Therefore, the resistance R
The change in the temperature of the resistor R _f1 during the period in which the dither component is held by using _f1 and the period in which the dither component is subtracted can be almost ignored. Therefore, the held dither component can be output as it is at the time of subtraction, and the dither component can be accurately removed.

FIG. 3 is an equivalent circuit for explaining the current flowing into the sample hold circuit by the second operational amplifier (18) in the first subtraction processing circuit (16). That is, it shows the state when the _second and _third switches S ₂ and S _{3 in} FIG. 1 are on.
D / A converter in this state (15) is a current source I _D2, the current source I _D2 with respect to the first operational amplifier (17) of the output voltage the voltage source E _A and the first resistor consisting of R _f1 is connected in parallel, and the ON resistance R _{S of} the third switch S ₃ , that is, the resistance between the terminals in the ON state of the third switch S ₃ is connected in parallel. The output side terminal of the third switch S ₃ is
It becomes the ground potential by the imaginary short of the two input terminals of the operational amplifier (18).

In FIG. 3, the current I flowing through the resistor R _S when the lower end of the resistor R _f1 is grounded, that is, the voltage source E _A is short-circuited, is represented by the following equation.

The current I flowing through the resistor R _S when the current source I _D2 is opened is given by the following equation.

The power source I of R _S when the two power sources are simultaneously connected by the superposition principle is given by the following equation.

The expression (4) is arranged by substituting −I _D1 R _f1 into E _{A of} (3). As is clear from the equation (4),
I _D2 −I _D1 can be calculated regardless of the values of R _f1 and R _S. Since the current I in the equation (4) is a current flowing into the sample-hold circuit using the second operational amplifier (18), it corresponds to I _D2 -I _D1 and thus the sample, that is, (X '+ Y')-
This means that a sample corresponding to Y '= X' is obtained.

FIG. 4 is an equivalent circuit showing the state of the subtraction processing circuit (16) during subtraction in more detail. Also in FIG. 4, the on-resistance of the third switch S ₃ is shown by R _S. The ON resistance of the second switch S ₂ is ignored. Further, a portion between the ON resistance R _S of the third switch S3 and the capacitor CH2 of FIG. 4 is a portion connected to the inverting input terminal of the operational amplifier (18), and the inverting input is made by the imerginal short (virtual short). The ground level is the same as the terminal. In FIG. 4, the current and voltage of each part when the voltage source E _A is short-circuited can be expressed by the following equations. The symbol S used in some of the following expressions indicates a Laplace transform operator.

I _D2 = I ₁ + I ₂ + I ₃ I ₃ = E ₁ / R _f1 I ₂ = E ₁ / R _S I ₁ = (E ₁ −E ₀ ) / R _f2 When E ₀ is obtained from these, the following equation is obtained.

On the other hand, the voltage and current of each part when I _D2 is opened can be expressed by the following equation.

_{-I 3 = I 1 + I 2} (E 1 -E A) / R f1 = I 3 I 2 = E 1 / R S I 1 = (E 1 -E 0) / R f2 When E ₀ is obtained from these, the following equation is obtained.

The output voltage E ₀ when both the voltage source E _A and the current source I _D2 are connected at the same time is obtained by adding equations (5) and (6) according to the principle of superposition, and become.

As is apparent from the equation (7), the output voltage E ₀ corresponding to I _D2 −I _D1 can be obtained. Then, it can be seen that the calculation of I _D2 −I _D1 is performed without being affected by R _f1 , R _f2 , C _H2 , R _{S and the} like.

[Modifications] The present invention is not limited to the above-described embodiments, but can be modified. For example, in order to form a time division multiplexed signal, a gate circuit is provided between the input circuit (11) and the adder (13) to intermittently remove the information signal and send it to the adder (13). You may make it insert a dither in the part removed intermittently. In this case, the multiplexing circuit (14) becomes unnecessary. Set the D / A converter (15) to voltage type,
A resistor may be connected to this output line to supply a current corresponding to the voltage to the subtraction circuit (16).

〔The invention's effect〕

In the present invention, the first resistor is not only the sample bold,
Since it is also used for subtraction, highly accurate dither subtraction is possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a D / A converter according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the state of each part of FIG. 1, FIG. 3 is a principle diagram of a subtraction circuit, and FIG. Is an equivalent circuit diagram of the subtraction circuit at the time of subtraction, and FIG. 5 is a circuit diagram showing a part of a conventional D / A converter. (11) …… Input circuit, (12) …… Dither generator, (13)
…… Adder, (14) …… Multiplexing circuit, (15) …… D / A converter, (16) …… Subtraction processing circuit, (17) (18) …… Operational amplifier, S _{1 to} S ₄ ...... Switch, C _H1 , C _H2 …… Capacitor, R _f1 , R _f2 …… Resistor.

Claims (2)

[Claims] 1. A digital information signal input circuit (11), a digital dither generator (12), a digital information signal supplied from the input circuit (11) and a digital signal generated from the dither generator (12). An addition and multiplexing circuit (13, 14) that forms a digital dither addition information signal by adding the dither and a time division multiplexed signal of the digital dither addition information signal and the digital dither; A digital-analog converter (15) for converting the time-division multiplexed signal obtained from the adding and multiplexing circuit into an analog signal, and an analog time-division multiplexed signal obtained from the digital-analog converter (15) And a subtraction processing circuit (16) for obtaining an analog information signal by subtracting the analog dither from the analog dither addition information signal. In the analog conversion device, the subtraction processing circuit (16) is connected to the output line of the digital-analog converter (15), and is turned on during the period when the analog dither is output. ₁ ) and the inverting input terminal is connected to the digital-analog converter (15) through the _first switch (S ₁ ) and the non-inverting input terminal is connected to ground. 17), a first capacitor (C _H1 ) connected between the inverting input terminal and the output terminal of the first operational amplifier (17), and an input side terminal of the _first switch (S ₁ ). And a first resistor (R _f1 ) connected between the output terminal of the first operational amplifier (17) and the input terminal of the first switch (S ₁ ). second switch composed of the oN oFF period of the switch (S ₁₎ And S _2), the second is connected to the output terminal of the switch (S _2), turned on in the period in which dither addition information signal is outputted in the time-division multiplexed signal of said analog third switch ( S ₃ )
And an inverting input terminal connected to the input side terminal of the first switch (S ₁ ) through the third switch (S ₃ ) and the second switch (S ₂ ), and a non-inverting input terminal Is connected between the second operational amplifier (18) connected to the ground, the output side terminal of the _second switch (S ₂ ) and the ground, and the third switch (S ₃ ) is turned off. A fourth switch (S ₄ ) which is turned on during the period, a second capacitor (C _H2 ) connected between the inverting input terminal and the output terminal of the second operational amplifier (18), and A digital-analog comprising a second resistor (R _f2 ) connected between the input terminal of the _third switch (S ₃ ) and the output terminal of the second operational amplifier (18). Converter. 2. The digital-analog converter (15)
Is a current type digital-analog converter whose output is obtained as a current.
Analog converter.