JPH0121361Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field This invention is used for converting analog input signals into digital values in measurement control equipment such as controllers and electromagnetic flowmeters and importing them into processing circuits such as CPUs. This invention relates to a signal input circuit.

(b) Conventional technology Conventionally, in the signal input circuit of the measurement control equipment mentioned above,
Analog input signals are often sampled at approximately 200ms. An RC circuit is used to remove commercial 60Hz normal mode noise that mixes into the analog signal.

(c) Problems that the invention aims to solve However, in order to sufficiently attenuate the amplitude of 60Hz noise, the RC value becomes large and the response becomes slow.
Further, a large capacitor (C) must be used, and in the case of a multi-channel input circuit, there is a drawback that just providing this capacitor takes up a considerable amount of space.

This idea was devised by focusing on the above-mentioned problems, and it is possible to use commercial 60Hz without taking up too much space.
An object of the present invention is to provide a signal input circuit that can remove normal mode noise even when the amplitude is large.

(d) Means and operation for solving the problem The signal input circuit of this invention includes a first multiplexer that receives an analog signal of each channel as an input, and a capacitor for cutting off the DC component of the analog signal of each channel. a second multiplexer that receives the signal from the first multiplexer, a channel selection signal generating means for applying a channel selection signal for channel switching to the first multiplexer and the second multiplexer and outputting the channel signal in time sequential order; and an A/D for A/D converting the output of each channel of the second multiplexer.
a conversion means, a signal value obtained by A/D converting the output of each channel of the first multiplexer by the A/D conversion means, and an A/D conversion of the output of each channel of the second multiplexer by the A/D conversion means; and a difference value calculation means for calculating the difference with the D-converted signal for each channel.

In this signal input circuit, the analog signals of each channel are inputted as they are to the first multiplexer, and are outputted from the first multiplexer time-sequentially in response to a channel selection signal. In addition, the analog signal of each channel is input to the second multiplexer via a capacitor for cutting the DC component.
Also in response to the channel selection signal, the signals are output from the second multiplexer in time sequential order. The outputs of these first and second multiplexers are A/D
The signal is converted into a digital signal by the conversion means, and is input to the difference value calculation means. The difference value calculating means calculates the difference value between the first multiplexer output converted into a digital value and the second multiplexer output for each channel, and uses the result as an input signal for each channel.
For example, if 60Hz noise is mixed in the analog input signal, the output of the first multiplexer will be the input + 60Hz noise, and the second multiplexer will output only the DC component, that is, the 60Hz noise with the input removed. Since it outputs, if you take the difference value of both outputs,
The 60Hz noise is removed and only the original input signal is obtained.

(e) Examples This invention will be explained in detail below using examples shown in the drawings.

FIG. 1 is a block diagram of a signal input circuit showing one embodiment of this invention. In the figure, 1 is an input terminal to which an analog input signal Ei of channel ch1 is applied. In addition to the measurement input signal, high frequency noise, commercial frequency noise, etc. are superimposed on this analog input signal Ei. RC ₁ is a resistor and a capacitor that constitute a filter circuit that removes high frequency noise, and the value of RC ₁ is very small. The analog input signal Ei ₁ that has passed through the filter circuit of RC ₁ is connected to be applied to one end of the input of multiplexer 2, and is also connected to a capacitor for DC division.
It is connected to be applied to one end of the input of multiplexer 3 via _C2 . This input point is
Furthermore, it is grounded with a resistor _R1 . Although not shown, the analog input signals of channels ch 2, ch 3, and ch 4 are applied to the other input terminals of multiplexer 2 via input terminals and high-frequency filter circuits, similar to channel ch ₁ . There is. Also, the other input terminals of the multiplexer 3 are connected to channels ch2, ch3,
The channel 4 analog input signal is applied via a DC cut capacitor and grounded via a resistor.

A sampling command signal SI and a channel selection signal CS are applied to multiplexers 2 and 3, and each time the sampling command signal SI is applied, the output of the channel selected by the channel selection signal CS is derived. be done. Note that the sampling command signal SI has a phase shift between the analog signal applied to multiplexer 2 and the DC cut signal applied to multiplexer 3, so multiplexer 2 and multiplexer 3 apply signals whose timings are shifted. There is.

The output of multiplexer 2 is connected to hold amplifier 4, and hold amplifier 4 further connects A/
It is connected to the CPU 8 via the D converter 5.
Further, the output of the multiplexer 3 is similarly connected to a hold amplifier 6, and the hold amplifier 6 is further connected to the CPU 8 via an A/D converter 7. Note that AI is an A/D conversion command signal.

Now, when the analog input signal Ei shown in FIG. 3a is applied to the input terminal 1 of the embodiment circuit shown in FIG. The signal shown at b is applied to multiplexer 2. Also, this third
The DC component of the signal shown in b in the figure is removed by capacitor C ₂ and its phase is shifted, and the signal shown in c in Fig. 3 is applied to multiplexer 3.The signals applied to both multiplexers 2 and 3 are Sampled output is performed according to the sampling signal SI. Note that the sampling signal SI to the multiplexer 3 is applied with a shift from the sampling signal SI to the multiplexer 2 by the amount of the phase difference. For example, if there are four channels, multiplexer 3 first selects channels ch1, ch2,..., ch
4 are sampled in sequence. These four samplings are performed at as short time intervals as possible. On the other hand, at a time shifted by the phase difference from the sampling of channel ch1, multiplexer 2
Similarly, ch1, ch2, ..., ch4 are sampled at short intervals. By doing this, data at approximately the same time can be obtained for channels ch1, ch2, . . . , ch4. In addition to channel 1, analog input signals similar to those shown in FIG. 3 are applied to channels ch2, ch3, and ch4 to multiplexer 2 and multiplexer 3. Further, in the multiplexers 2 and 3, which channel's signal is to be sampled and output is selected by a channel selection signal CS, and the sampling and output of each channel is performed in timing order.

The signal from the channel ch multiplexer 2 outputted by the sampling operation is held by the hold amplifier 4, further converted into a digital value by the A/D converter 5, and then taken into the CPU 8. Similarly, the signal from multiplexer 3 is also held by hold amplifier 6, and the A/D
It is converted into a digital value by the converter 7 and taken into the CPU 8. The CPU 8 subtracts the digital value input from the A/D converter 7 multiplied by a coefficient from the digital value input from the A/D converter 5, and takes in this subtracted value as an input signal value.
This input signal value is obtained by multiplying the signal shown in c by a coefficient and subtracting the signal shown in c from the signal obtained by shifting the signal shown in a in Fig. 3 by the amount of the phase difference.
The 60Hz AC noise contained in the signal is removed and the true measurement input level Vi can be captured. 60 in exactly the same way for other channels.
The input signal Vi from which the Hz AC noise component en has been removed can be taken in.

Here, in Figure 3, ω=2π: Since it is the frequency of en, the coefficient to be multiplied by e′n is , and the phase shift is tan ^-1 for e′n compared to en
It will move forward by (R ₁ C ₂ ω).

In the embodiment circuit shown in FIG. 1, the outputs of multiplexer 2 and multiplexer 3 are converted into digital values using separate A/D converters 5 and 7, but as shown in FIG. The outputs of hold amplifier 4 and hold amplifier 6 are applied to A/D converter 10 via multiplexer 9, and the outputs of hold amplifier 4 and hold amplifier 6 are A/D converted by time division by channel switching by multiplexer 9. and CPU8
You may also import it into In this way, only one A/D converter is required. Furthermore, in this case, by taking in the common voltage as an input to channel ch3, it is possible to detect and correct the shift in the zero point of the A/D converter 10 itself.

(f) Effects of the invention According to this invention, two multiplexers are provided, one multiplexer receives the analog input signal of each channel as is, and the other multiplexer receives the analog input signal of each channel for direct current cutting. The output of each channel of both multiplexers is A/D converted by applying it through a capacitor and grounded by a resistor, and the difference between the A/D converted signal value multiplied by a coefficient is calculated for each channel. Since the resulting value is used as the signal input value for each channel, there is no need for a large-capacity capacitor that constitutes a filter circuit for removing 60Hz AC noise as in the past, and therefore space for circuit implementation can be saved. In addition, true input data can be taken into the CPU despite the noise amplitude without having to send an output response.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal input circuit showing an embodiment of this invention, FIG. 2 is a block diagram showing a partially modified circuit of the embodiment shown in FIG. FIG. 3 is a signal waveform diagram for explaining the operation of the example circuit. 1...Input terminal, 2,3,9...Multiplexer, 4,6...Hold amplifier, 5,7,10...
...A/D converter, 8...CPU.

Claims (1)

[Claims for utility model registration] A/D conversion of multi-channel analog input
This is the input circuit that takes in the CPU, and the first circuit receives the analog signals of each channel as input.
a second multiplexer that receives the analog signal of each channel via a DC cut capacitor, and provides a channel selection signal for channel switching to the first multiplexer and the second multiplexer; channel selection signal generating means for sequentially outputting channel signals; and A/
An A/D conversion means converts each channel output from the first multiplexer into a signal value obtained by A/D conversion by the A/D conversion means, and the output from each channel of the second multiplexer is converted into the A/D conversion means. A signal input circuit comprising difference value calculation means for calculating the difference between each channel and the signal A/D converted by the D conversion means.