JPS58106915A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain an A/D converter having the nonlinear characteristics, by using a comparison voltage terminal of a comparator, which is incorporated in the A/D converter, as an external terminal. CONSTITUTION:Voltage dividing resistors P1-PN of an A/D converter are provided with external terminals T1-TN, and voltage ER1-ERN are applied to these terinals. A voltage of ERP-ER1 can be applied between terminals T0 and T1, and a voltage of (ERP-ER1)/3 can be supplied between voltage dividing points P1 and P2 between them. Similarly, voltages determined by voltages ER1- ERN applied to external terminals T1-TN are supplied to respective voltage dividing points P1-PN, and voltages between respective branch points P1-PN are inputted to comparators C1-Cn and are compared with an input analog signal Vin, and comparison outputs are encoded in an encoder EN, and a digital signal is outputted through a latch circuit. Voltages ER1-ERN are varied to obtain the A/D converter having the optional nonlinear characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention uses a low speed A/D converter to provide a high speed A/D converter.
This is a book about A/D converters useful when performing D conversion.

Figure 1 shows the circuit configuration for converting a high-band analog signal into a digital signal using a low-speed A/D converter, where 1 is an input terminal, 2 is an amplifier, and 3a to 3d sampling and hold circuits s43 to 4d is A/D converter, 5 is parallel-
It is a series converter.

In this circuit, a high-band analog signal inputted from an input terminal 1 is made to have sufficient amplitude by an amplifier 2, and this amplitude level is controlled by each sample refresh hold circuit 38 to 3d operated by a sampling pulse ΦIK supplied in a time-division manner. 4
Detected as phase sample voltage. Thereafter, each of the four-phase sample voltages is converted into a digital signal by YA/D converters 42 to 4d, and the 7spg signal II'c is inputted from the input terminal 1 to the output of the parallel-serial converter 5. A corresponding digital signal is obtained.

In this circuit, the analog signal is sampled and held
i! 3a to 34 make the 4-phase sample voltage, and A/
Since it is input to the D converters 41 to 4d, the A/D converter 4a
~A/D converter 4a has the advantage of being able to use a relatively low-speed converter, but it converts signals in parallel~
4dLf) If there is a difference in the lf# characteristics, the same level value of the analog signal is converted to a different digital food, causing distortion when converted to the original analog signal.

Next, the main causes of conversion errors caused by A/D conversion@4a to 4d VC will be explained.

Figure 2 shows the A/D converter 4a formed by an integrated circuit, where r1 to r, +1 are voltage divider circuit resistors, 01 to Cn are comparators, EN is an encoder, and L is a latch circuit. FI11 is shown.

This circuit divides the voltage supplied between the reference voltage terminal E
At the same time, the voltage obtained by sampling the analog signal is applied to the other terminals of the comparators C and -C.
・Ru. Therefore, depending on the sample voltage value, the output of each comparator C to C is 1 or 0 output t! Input the next encoder ENK. Comparators C8 to C0 are
When converting to n-bit code, 2a pieces are required,
For example, in the case of 8 bits, 256 comparators C2 to C, t- are provided. Therefore, the voltage dividing resistor ", ~"1+,
257 are required, and the value is selected to divide the voltage of the reference voltage terminal E□-E by 256. If this resistance value has an error of %, different digital code signals will be output from each A/D converter 4a to 4d even when the same level of sampled voltage is applied, and as mentioned above, different digital code signals will be output. cause waveform distortion.

This invention was made based on the idea of point pressure.
In order to equalize the comparison voltages of the comparators built into each A/D converter, several comparison voltage terminals are formed so that the converted code signals match in the A/D converters of each phase. This is what I did.

3(a) and 3(b) show a portion of a resistive voltage divider circuit that supplies comparison voltages to the comparators C1 to C2 described above in order to explain a simple embodiment of the present invention. Figure (a) shows a resistor voltage divider circuit of two A/D converters using 12 resistors r.
+-rtt and rI'~r1. This is a diagram illustrating the cases formed by ′.

In this figure, the resistive voltage divider circuit of the first A/D converter is defined as r, ~
"1.", and the voltage value at each voltage dividing point is resistor "1" to "1.
The position of the partial pressure point and mark indicates that the voltage is not equal due to the error of Similarly, for the second A/D converter, the resistor voltage divider circuit is connected to resistors r1' to r, ! ', and the voltage value at the voltage dividing point is represented by the position of the mark, the resistor ', ~rate rl' ~1.
' due to the error of e, ~ε2. It can be seen that an error voltage of

In order to eliminate such errors, each resistance 't
rI=,,+, j,':, r2Z """y
Although it is necessary to set r12 = r+2', it is realistically difficult to arrange all of the several hundred resistors for each A/D converter. However, if a group of terminals for applying comparison voltages are provided to each A/D converter and a common comparison voltage is supplied thereto, if the number of conversion bits is large, the circuit design may be exceeded.

Therefore, in this invention, as shown in FIG.
~T3 and 7, /~Ti are provided, and these are lead drills l, ~1. Make it possible to connect with .

When K is set in this way, at least the partial pressure points (P4, P4
).

(P?t Py ) and (P+.pPl.') have the same potential, so other points, namely (P,, P,'),
(Pt, P; ).

......, error voltage (g.) generated at (Pl!-P+7).

~ε, 1) too! f#KII! Since it is clear that the resistances r1~rat and r, l~f;
The corresponding comparison voltages in the D converters can be made almost the same.

The proportion of external terminals (T, ~Ts) and (T+'+T3') to be provided depends on the resistance (', ~'+2'L).
(It is determined by the accuracy of "rl' to r12", and the number should be at least as long as the range in which the minimum bits of the converted codes match.

When there are four A/D converters to be driven in parallel, the external connection formed on each A/D converter is of course connected to the terminal T1.
~T, all points that have the same potential are connected.

Therefore, if an external terminal voltage is provided at the voltage dividing point that forms the comparison voltage of the A/D converter, the following usage can be considered. Connect externally to the D converter using terminal T.
1 to Tl1 (the number can be set arbitrarily) V is provided. Normally, a reference voltage is connected between the reference voltage terminals E□ and E□, and it is used as a linear A/D converter. However, if the external terminals are operated by applying arbitrary voltages E, . . . , to the terminals T, . can be configured.

Conventionally, as one method for reducing quantization noise, a technique is known in which an analog signal is amplified at a low amplitude level using a nonlinear circuit, and the signal is A/D converted.

When performing such non-linear A/D conversion, voltages Eat to E are applied to the external terminals T and -E shown in FIG. -T.

In between Epw I! A voltage of □ can be applied, and a + voltage can be supplied to the voltage dividing points P, , P, between them.

Similarly, voltages E, -H□ are applied between T and T2, and voltages E-E1 are supplied to voltage dividing points P, and P between this period. Similarly, each partial pressure point P1 to P0
The external terminals are the voltages E□ applied to terminals T and ~T, respectively.
~Voltage determined by EIK (however, E+at > E
□〉Eo...〉E〉) are supplied, so by varying these voltages, an A/D converter with arbitrary nonlinear characteristics can be obtained.

If the voltage dividing point (P, -P,) and the external terminals are different from each other as shown in the figure, the broken line approximation will be applied, but the external terminal will be the terminal T1.
As ~To increases, it becomes a nonlinear curve, and if external terminals are provided as many as the number of voltage dividing points P1 to Pa, the resistor of the resistive voltage dividing circuit becomes unnecessary.

An embodiment of the voltage supply circuit applied to the external terminals T, .about.O is shown in FIGS. 5(a) to 5(d).

Figure 5(a) shows the series resistors R8 to Rx for voltage division set to 1* to obtain a nonlinear voltage Eat~E, and Figure 5(b) shows the series resistors R0 to Rx for voltage division set to 1* to obtain a nonlinear voltage Eat~E. A nonlinear voltage E, 1 to E□ is obtained by using R as a variable resistor.

In addition, Fig. 5(c) and (d) show nonlinear voltages E11~) outputted by a plurality of digital-to-analog converters D/Al-D/Am, and the nonlinear characteristics can be varied by digital signals. can do.

As explained above, the A/D converter of the present invention
Since the comparison voltage terminal of the comparator built into the converter is made to be an external terminal, it is particularly useful for conversion circuits that connect A/D converters in parallel and perform analog-to-digital conversion.
It has the advantage that it can also be used as a nonlinear A/D converter.

[Brief explanation of drawings]

Figure 1 is a block diagram of a circuit that A/D converts a high-band analog signal using a low-speed A/i)f converter, Figure 2 is an internal circuit diagram of the A/D converter, and Figure 3 (a). , (b) is an explanatory diagram for aligning comparison voltages, FIG. 4 is an embodiment of the present invention, and the external device shown is a circuit diagram of an A/D converter provided with terminals.
Figures (a) to (d) are circuit diagrams for generating voltages that operate the A/D converter in a nonlinear manner. In the figure, P and -P are voltage dividing points, T and -T are external terminals, 01 to C are comparators, EN is an encoder, and L is a latch circuit. Fig. 1 Fig. 2 Mu a Fig. 3 (a) (b) Fig. 4 Fig. 5 peak (a) (b) (c) (
d)

Claims (1)

[Claims] In an A/D converter, the A/D converter includes a plurality of comparators each having an input terminal to which a comparison voltage χ is supplied by a resistance divider circuit, an encoder that encodes the output signal of the comparator, and a latch circuit that holds the output of the encoder. , An A/D converter characterized in that an external input terminal to which the comparison voltage is supplied is configured as a terminal.