JPS6367826A - Digital/analog converting device - Google Patents

Abstract

PURPOSE:To subtract a dither with high accuracy by using the feed-back resistance of an operational amplifier for not only sample holding operation, but also the subtraction. CONSTITUTION:A 1st switch 51 operates as a switch for sampling the dither, which is extracted while the switch is on and sent to the 1st capacitor CH1. A 3rd switch S3 turns on in the output period of a dither addition information signal and a 2nd switch S2 also turns on in this period, si a current ID2 corresponding to a dither addition information outputted by a D/A converter 15 and a current corresponding to the dither is sampled and sent to a 2nd capacitor CH2. A 1st resistance Rf1 operates as the feedback resistance at the time of the sample holding operation and also as a resistance for dither subtraction, so the subtraction of the dither is performed sufficiently without any adjustment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital-to-analog (
D/A) Regarding substation equipment.

[Conventional technology]

If the relationship between the input and output of the D/A converter is poor,
Waveform φ distortion occurs, and harmonic noise is generated.

Based on the nonlinearity of the D/A converter (in order to reduce noise, the digital information signal (data) input to the D/A converter is subjected to D/A conversion by adding 7 JD of digital dither, and then A method for removing (subtracting) the dither component contained in an analog signal is already known.If dither is added according to this method, a digital information signal that is repeatedly output with the same analog waveform can be obtained. Repeat D/Af
Even if they are changed, the operation will not be the same, but the non-old linear distortion will be averaged, and the occurrence of harsh noise due to the non-linear distortion will be reduced.

By the way, in order to easily and accurately perform the dither addition and subtraction as described above, the dither 7JD calculation information signal and the dither are time-division multiplexed, as shown in FIG.
One signal (e.g., dither) that is converted into an analog signal by the A converter (1) and time-division multiplexed is extracted and held by the sample-and-hold circuit (2), and this is used as the other time-division multiplexed signal. (for example, dither addition information signal) is input to the analog subtracter (3), and dizan subtraction is performed from the dither addition information signal, and deglitch (deglitch) is performed.
1tch) The applicant has already proposed a system in which only the information signal is extracted using the circuit (4).

[The problem that the invention attempts to solve]

The method VC in Figure 5? sample and hold circuit (2
) completely holds the output of the D/A converter fi+, and g
It is impossible to send it to the calculator +31. For this reason, it was necessary to install a resistor f51 (61) on the input line of the subtracter (3) and adjust the level so that the dither was completely subtracted by VC.If this level adjustment was incomplete, the ′
：X converter (31) This level adjustment had to be performed with high precision in order to avoid the possibility of sufficiently removing the dither. ]), for example, the settling time of D/A conversion is 3 μsec, and the settling time of D/A conversion is 3 μsec, and both the dither and dither addition information signal are converted to D/A. At least 6 μs was required for A conversion, which became an obstacle to increasing the speed.

Therefore, one object of the present invention is to reduce dithering by using a digital digital camera that can easily and accurately reduce dithering.
An object of the present invention is to provide an analog 7R conversion device.

[A means of promise to resolve problems]

The present invention, which aims to solve the above-mentioned problems and achieve the above-mentioned objectives, will be explained with reference to the reference numerals in the drawings showing implementations. A digital dither addition information signal is formed by adding together the digital information signal fed from the input circuit 11) and the digital dither generated from the dither generator 02, and the digital dither addition information signal and the digital dither are time-shared. a summing and multiplexing circuit for forming a multiplexed signal; a digital-to-analog converter Q51 for converting the time-division multiplexed signal obtained from the summing and multiplexing circuit into an analog signal; A digital-to-analog conversion device comprising a subtraction processing circuit (161) that obtains an analog information signal by subtracting analog dither from the dither addition information signal of the final ag based on the analog time division multiplexed signal.

The subtraction processing circuit Q61 is connected to the output line of the digital-to-analog converter Q51, and includes a first switch (
), and one input terminal is connected to the first switch (S, ), and one input terminal is connected to the first switch (S,
), the other input terminal is connected to the digital-7 analog converter α9, and the other input terminal is connected to the ground.
A first capacitor (C□,) is connected between one input terminal and an output terminal of the first operational amplifier (171), an input side terminal of the first switch (Sl) of the front ffi
T′Lfc first resistor (R,
) and the input side terminal Vc of the first switch (G3)
e is connected to a second switch (G2) that is turned on during the off period of the first switch (S,) in ITJ, and is connected to the blade side terminal of the second switch (G2), and is connected to the output side terminal of the second switch (G2), a third switch (G3) that is turned on during the period in which the dither addition information signal in the division multiplexed signal is output; ) and the first switch (81)
a second operational amplifier a & which is connected to the input terminal of the second switch (G2) and whose other input terminal is connected to the ground, and between the output terminal of the second switch (G2) and the ground;
a fourth switch (G4) that is turned on while the third switch (G3) is off; and the second operational amplifier α &
a second capacitor (CH,) connected between one input terminal and an output terminal of the third switch (G3);
This relates to a digital-to-analog conversion system fIK, characterized in that it consists of a second resistor (R4,) connected between the input side terminal of the second operational amplifier and the output terminal of the second operational amplifier marked a. be.

[For production]

The first switch (8+) functions as a switch for dither sampling, and while it is on, dither is extracted and sent to the first capacitor CCH1). The voltage of the second capacitor (C, , ) is determined by the voltage (ID, Rf, ) of the first resistor (R, , ). Since the third switch (G3) is turned on during the output period of the dither addition information signal, and the second switch (St) is turned on during this period, the dither addition information signal output from the D/Af unit α9 is 1 corresponding to (X+Y')
A current corresponding to the difference between the current ``Dz'' and the current l corresponding to the dither (Y') is sampled and sent to the second capacitor (CH2). The first capacitor (CHl) and the first operational amplifier 0D convert the current (ID, ) corresponding to the held dither component into a dither addition information signal (X+Y').
It works to extract the current corresponding to ID from the current.

The resistor (R(1)) acts as a feedback resistance during sample and hold, and also acts as a dither subtraction resistance, so dither subtraction can be performed satisfactorily without adjustment. [Example] Next, a D/A converter according to an embodiment of the present invention will be explained with reference to FIGS. 1 to 4.

In the figure, all are 6-bit information signal input circuits, and are circuits that supply digital information signals (X) corresponding to audio signals. This is a digital dither generator consisting of a21Fi pseudo-random pulse generation circuit and supplies dither (Y)V. The adder Cl31 connected to the input circuit 01) and the dither generator is a 76-bit full adder, and inputs the information signal (X) and dither (Y).
and outputs a dither addition information signal (X + Y). It consists of a time division multiplexing circuit a4Ji'r connected to the adder 3 (131) and the dither generator Q21, and a multiplexer, which outputs the dither addition information signal (X+Y) and the dither (
Y) and time division multiplexed signal (X+Y)+
Output (Y).

Multiple North Times 125 G41 K W &Sat's ft
D/A'R converter (151).

For example, it consists of a current-type D/A converter emitted from Burr-Brown's PCM53JC3-), and an analog multiplex signal r corresponding to the digital multiplex signal (X+Y)+1Y).
Outputs X'+Y') + (Y') as a current.

Since this D/A converter +151 is a current type and does not have a current-voltage converter, the settling time of the current output is approximately 350 nSeC, which is extremely short.

σ61 is a subtraction processing circuit according to the present invention, in which the first switch S1 connected to the D/A converter (151) and one input terminal (inverting input terminal) are connected to the D/A converter (151) through the first switch 81. A converter QSVC is connected to the first operational amplifier a-power whose other input terminal (non-inverting input terminal) is connected to ground, and one input terminal and output terminal of this first operational amplifier a-power. ]th capacitor C connected between
and a tt7' (th) resistor Rf+ connected between the input side terminal of the first switch S1 and the output terminal of the first operational amplifier a, and the input side terminal of the first switch S1. Once connected, the second switch St is connected, the third switch S3 is connected to the output terminal of the second switch S2, and the fourth switch S3 is connected between the output terminal of the second switch S2 and the ground. One input terminal (inverting input terminal) of the switch S4 is connected to the input terminal of the second switch S via the third switch S3 and the second switch S2, and the other input terminal (non-inverting input terminal) is connected to the input terminal of the switch S4. A second operational amplifier 0 & whose inverting input terminal (inverting input terminal) is connected to ground, and #lc connected between one input terminal and output terminal of this second operational amplifier α & 7
and a second resistor R1 connected between the input terminal of the third switch S3 and the output terminal of the second operational amplifier 181. In addition, switch S, %
Switch control circuit 0 to control on/off of s4
is provided.

Next, the operation of the apparatus shown in FIG. 1 will be explained with reference to FIG.

When a time division multiplexed signal of the dither addition information signal (X+Y) and dither (Y) is input to the D/A converter α.

Each is converted into an analog signal, tl to t in Fig. 2.
4. Analog dither (Y) with 17~tlO? Indicating current”
DI is output, and from t4 to t7. tlQ"+ ill
A current ID2 indicating the analog dither addition information signal (X'+Y') is output.

The first switch S1 is turned on from 12 to "3*'8 to t9 during the dither period, as shown in FIG. 2 CB), and the second switch S2n is turned on, as shown in FIG. The third switch S is turned on and off 'IrIJ' in the opposite way to the switch S. The third switch S, as shown in FIG. ~t
12, the fourth switch S4 is turned on, and the fourth switch S4 is turned on.
] As shown in the figure, the switch turns on and off in the opposite way to the third switch S3.

Now oh the first switch 8. When turned on, the current DI output from the D/A converter (15+) flows through the first switch S1'1, and after a sufficient period of time the first capacitor -W C)I, charged to saturation,
After that, the current flows through the first resistor H41tC. Since the first capacitor CH5 and the first resistor Rf1 are connected in parallel, the capacitor CH21-r, ID1Rf
Fill it with the value corresponding to +. And the first one on i3
Even if the switch S1 is turned off, the inverting input terminal and the non-inverting input terminal of the operational amplifier 01 are in an immanent short state, so the inverting input terminal The potential is also ground, so the output voltage of the operational amplifier aD is EA\'i''D+Rf+.

When the second switch S2 is turned on at t3, D/Af
Since the output terminal of the converter (15+) is connected to ground via the second switch S2 and the third switch S3.

This electric current L or "H2" should flow to ground.

DI However, the output voltage EA of the first operational amplifier αD is
switch SI is turned on again t8-! It's in a hold.

When the third switch S3 is turned on at t, ~t6, it enters the sampling state, and 1 is passed through the third switch S3'Y.
D2-ID, the current corresponding to lC is the second capacitor-fr
Flows into CH2 and output terminal V of the second operational amplifier a8
A voltage En corresponding to C'D2''DI is obtained. Fig. 2 CF) shows the change in the output voltage Eo, and t
During the sampling period from 5 to tA and from tll to t12, the voltage value changes according to the sample, and the voltage is maintained until the next sampling period.

In this method, the first resistor Rf+ is not only used as a feedback resistor when the current JD+ is being throttled, but also as a subtraction resistor for the current l, so it is possible to accurately subtract ID1J. can.

This is an equivalent circuit for explaining the current flowing into the sample hold circuit by the second operational amplifier 0&, which is transferred to the subtraction processing circuit a in FIG. 1 as the third factor. That is, the second
and a third switch S2. This shows the state when S is on. In this state, the D/A converter α9 is an island current source, and the first 3N amplifier Q71 is connected to this current source 'D2.
A voltage source EA having an output voltage of 1 and a first resistor Rft are connected in parallel Vcw, and the on-resistance Rs of the third switch S3 depending on the case is connected in parallel. Note that the third switch S3
The output side terminal of the second operational amplifier α& becomes ground potential due to an imaginary short circuit between the two input terminals of the second operational amplifier α&.

In Fig. 3, the lower end of the resistor 'Rf+ is grounded, that is, the voltage source E
The current 1 flowing through the resistor R81C when Av is short-circuited is expressed by the following equation.

According to the principle of superposition, the current of Rs when two t sources are connected at the same time is expressed by a linear equation.

Nao, (41 type tlj (31) EAK IDI R
f+'1 assignment is organized. As is clear from this equation (4).

Irrespective of the value of R, , R8 1CIDz 'Dt operation j
I can do it. (Current 1 in equation 41 is the current flowing into the sample/hold circuit wIK using the second operational amplifier a81, so the sample corresponding to ID, -ID, i.e. (X'+ Y') -Y'= X' This means that a sample corresponding to .

FIG. 4 is an equivalent circuit showing in more detail the state of the subtraction processing circuit (161) during subtraction. In this FIG. 4 as well, the on-resistance of the third switch S3 is indicated by RS.
The on-resistance of the second switch S2 is ignored. In this Figure 4, the pressure source EA'Y! The current and voltage of each part when connected can be expressed by a seventh-order equation.

1D2=z, + h + lx 1 s = E + / R (.

Iy = E+ / RB 1+ = (E+ go) / Rt2 From these, E
The oV is determined by the following formula.

On the other hand, the normal pressure and current of each part when ID and N are open can be expressed by the following equations.

1*= 1+ + 12 (P!II-EA) / R(r = IsI 2 =
El/R8 I+ = (E+ go) R(.

EO”=　　12　s　(2,.

Calculating Eo from these results in the following equation.

・・・・・・・・・・・・ (6) The output voltage E when both the voltage source E and the 11th source D2 are connected at the same time is expressed by equation (5) according to the principle of superposition. It is obtained by adding Equation 61 and becomes the following equation.

It is possible to obtain an output voltage E. and,"])
The calculation of 2'DI is performed using Rfl, Rf2. CI(2, ■
(You can see that it was done without being affected by the 8th grade at all.

[Modified example]

The present invention is not limited to the above-described embodiments.

It is also deformable. For example, in order to release the one-time division multiplexed signal, a gate circuit is provided between the input circuit αD and the adder αe, and the information signal is intermittently removed.
31, and dither may be inserted into the intermittently removed portions. In this case, the multiplexing circuit α is not required. The D/A converter may be a 4-voltage type, and this output line resistance may be connected to supply a current corresponding to normal pressure to the subtraction circuit aD.

〔Effect of the invention〕

In the present invention, the first resistor is used not only for sample and hold, but also for sample and hold.
Since it is also used for subtraction, highly accurate dither subtraction n is possible. .

[Brief explanation of drawings]

Figure 1 shows a D/A variable power substation according to an embodiment of the present invention. The circuit diagram shown. FIG. 2 is a waveform diagram showing the states of each part in FIG. 1, and FIG. 3 is a diagram of the principle of the subtraction circuit. FIG. 4 is an equivalent circuit diagram of the subtraction circuit during subtraction. FIG. 5 is a circuit diagram showing part of a conventional D/A cost conversion device. (Ill...input circuit, α2...dither generator, 0
31... Force multiplier, (141... Multiplexing circuit, Q5
1...D/A converter, aD...subtraction processing circuit, Q
71 (181... operational amplifier, 31~S4... switch. CHl, CH2... capacitor R(++R(z・
··resistance. Agent Noriji Takano;
-Extinction 1=Ki=Bi-Tsugumi, ■Gen ε included, Hiroshi-+★Kataya

Claims (1)

[Claims] A digital information signal input circuit (11), a digital dither generator (12), a digital information signal supplied from the input circuit (11) and a digital signal generated from the dither generator (12). an addition and multiplexing circuit that forms a digital dither addition information signal by adding the dither and a time division multiplexed signal of the digital dither addition information signal and the digital dither; a digital-to-analog converter (15) for converting the time-division multiplexed signal into an analog signal; and a digital-to-analog converter (15) for converting the time-division multiplexed signal into an analog signal; A digital-to-analog conversion device comprising a subtraction processing circuit (16) that obtains an analog information signal by subtracting analog dither, wherein the subtraction processing circuit (16) is connected to the output line of the digital-to-analog converter (15). a first switch (S_1) connected to the analog dither and turned on during the period in which the analog dither is output; and one input terminal is connected to the digital-to-analog converter (15 ) and the other input terminal is connected to ground.
7) and a first capacitor (C_H_1) connected between one input terminal and output terminal of the first operational amplifier (17).
), the input side terminal of the first switch (S_1) and the first
a first resistor (R_f_1) connected between the output terminal of the operational amplifier (17) and the input side terminal of the first switch (S_1); a second switch (S_2) that is turned on during the off period; and a period in which the dither addition information signal in the analog time division multiplexed signal is output, which is connected to the output side terminal of the second switch (S_2). The third switch (S
_3), one input terminal is connected to the input side terminal of the first switch (S_1) via the third switch (S_3) and the second switch (S_2), and the other input terminal is connected to the input terminal of the first switch (S_1). a second operational amplifier (18) connected to ground;
a fourth switch (S_4) connected between the output side terminal of the second switch (S_2) and the ground and turned on while the third switch (S_3) is off; A second capacitor (C_H_2) connected between one input terminal and output terminal of the operational amplifier (18)
and the input side terminal of the third switch (S_3) and the second
and a second resistor (R_f_2) connected between the output terminal of the operational amplifier (18) and the output terminal of the operational amplifier (18). (2) The digital-to-analog converter according to claim 1, wherein the digital-to-analog converter (15) is a current-type digital-to-analog converter whose output is obtained as a current.