JPS61230428A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce the round-off error, overflow at a high input level and to expand the dynamic range at a low input level by adjusting an analog signal level, using a signal in response to the gain so as to express an exponent part of a floating decimal point digital signal and expressing the mantissa part of the floating decimal point by a fixed decimal point digital signal corresponding to the analog signal whose level is adjusted. CONSTITUTION:A digital signal (a) subject to A/D conversion by an A/D conversion circuit 32 is expressed in the fixed decimal point but it is considered to be represented in a floating decimal point when the 1st control signal (b) outputted from the 1st level adjusting circuit 31 is taken into account. The fixed decimal point digital signal (a) and the 1st control signal (b) are subject to signal processing by the floating decimal point by a floating decimal point digital signal processing circuit 33 and outputted as a digital signal (c) representing the mantissa part and the 2nd control signal (digital signal) (d) corresponding to the exponent part. The 2nd level adjusting circuit 35 is constituted as, e.g., variable gain circuit and the signal level of the analog signal from a D/A conversion circuit 34 is adjusted by a gain corresponding to the 2nd control signal.

Description

[Detailed description of the invention] 1L1 The present invention relates to a digital signal processing circuit.

Conventionally, this type of circuit converts an inputted predetermined analog signal into a fixed-point A/D converter circuit 1, as shown in FIG.
1, a fixed-point digital signal processing circuit 12 performs fixed-point signal processing, and then a D/A conversion circuit 13 converts the signal into an analog signal.

In such conventional circuits, since signal processing is performed using fixed-point representation, there is a drawback that rounding errors occur after calculations due to signal processing.

In addition, as another conventional example, as shown in FIG.
The fixed point/floating point conversion circuit 22 converts the signal into a fixed point digital signal, and the fixed point/floating point conversion circuit 22 converts it into a floating point digital signal.
, a floating point/fixed point conversion circuit 24 converts the floating point digital signal into a fixed point digital signal, and a D/A conversion circuit 25 converts the floating point digital signal into an analog signal. There were also some.

Although the conventional circuit with such a configuration can reduce rounding errors after calculations like the conventional circuit described above, it has the disadvantage that rounding errors occur when converting a floating-point digital signal to a fixed-point digital signal.

In addition, in both of the above two conventional circuits, the digital signal after A/D conversion is expressed as a fixed point number, so if the analog signal has a high input level, an overflow may occur when converting it to a digital signal, or if the input level is low, an overflow may occur. In the case of level, there was a drawback that the dynamic range was reduced.

To 11 11 The present invention has been made to eliminate the drawbacks of the conventional methods as described above, and provides digital signal processing that can reduce rounding errors and overflow at high input levels, and expand the dynamic range at low input levels. The purpose is to provide circuits.

The digital signal processing circuit according to the present invention inputs a predetermined analog signal, adjusts the signal level, outputs a first control signal according to the gain at that time, converts this analog signal into a fixed-point digital signal, This fixed-point digital signal is subjected to floating-point signal processing in accordance with the first control signal, and at this time, outputted as a second control signal corresponding to the mantissa digital signal and the exponent part,
The configuration is such that the mantissa digital signal is converted into an analog signal, and the signal level of this analog signal is further adjusted in accordance with the second control signal.

Support-1-9 Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

In the figure, an input analog signal is level-adjusted in a first level adjustment circuit 31 and then converted into a digital signal a in an A/D conversion circuit 32. As shown in FIG. 4, the first level adjustment circuit 31 includes a reference voltage generation circuit 40 that generates a predetermined reference voltage, and a signal level of an analog signal that is detected based on the reference voltage and corresponds to the detected level. It consists of a level detection circuit 41 that generates a gain control signal from the level detection circuit 41, and a variable gain circuit 42 that adjusts the signal level of the analog signal by changing the gain according to the gain control signal from the level detection circuit 41. The level is adjusted so that when it is converted into a digital signal by the D conversion circuit 32, it is less than the full scale and more than -6'' of the full scale, and the gain control signal output from the level detection circuit 41 is adjusted according to the gain at that time. This becomes the first control signal (digital signal) b.

Here, full scale is the ±maximum value of digital expression. For example, in the case of 4-bit 2's complement representation, + full scale is "0111" and - full scale is rl 0.
Becomes OOJ. In addition, each bit of a digital signal has a level difference of ±6cE between adjacent bits, so if we consider exponential expression, if we express the exponent part in units of 6 dB, we only need to shift the real part according to the value of the exponent part. , easy to express,
Since it becomes easier to perform actual calculations, the level adjustment is performed to be less than full scale or more than 16 dB of full scale. Note that the sign (-) is based on the full scale (maximum value) standard.

The digital signal a that has been A/D converted by the A/D conversion circuit 32 is in fixed-point representation, but the first level adjustment circuit 3
When considered together with the first control signal output from 1, it becomes a floating point representation. In other words, the fixed-point digital signal a and the first control signal A correspond to the mantissa and exponent parts of the floating-point digital signal, respectively.

The fixed point digital signal a and the first control signal S are subjected to signal processing in floating point by the floating point digital signal processing circuit 33, and are converted into a digital signal C of the mantissa part and a second control signal (digital signal C) corresponding to the exponent part. )d
is output as As the floating point digital signal processing circuit 33, one having a well-known circuit configuration can be used. The digital signal C of the mantissa part is converted into an analog signal by the D/A conversion circuit 34 and supplied to the second level adjustment circuit 35. The second level adjustment circuit 35 has, for example, a variable gain circuit configuration, and adjusts the signal level of the analog signal from the D/A conversion circuit 34 with a gain corresponding to the second i control signal.

In a digital signal processing circuit having such a configuration, the signal level of the analog signal is adjusted, and a signal corresponding to the gain at that time is used to represent the exponent part of the floating point digital signal, and a fixed point signal corresponding to the level-adjusted analog signal is expressed. Since signal processing is performed so that the digital signal represents the floating point mantissa, it is possible to eliminate rounding errors that conventionally occur when converting fixed point digital signals and floating point digital signals. Furthermore, since the level of the analog signal is adjusted to prevent overflow when converted to a digital signal, overflow will not occur even at a high input level within the level adjustment range. Furthermore, even if the analog signal has a low input level, the level is adjusted using the analog signal, so when converting to a digital signal, the entire number of motherboard bits is used, so the dynamic number of hanger bits is reduced. This allows you to secure a microwave.

In addition, in the above embodiment, a case has been described in which the level of the analog signal is adjusted so that when converted to a digital signal, it is 6 dB or more below the full scale, but the level adjustment of the analog signal is performed when converted to a digital signal. It may be done so that the width is less than or equal to the full scale.

Further, in the above embodiment, the first and second control signals (exponential parts) b and d are digital signals, but they may be analog signals, and in this case, the digital signal processing circuit 33
An encoder and a digital signal processing circuit 33 may be added to the control signal line between the first level adjustment circuit 31 and the digital signal processing circuit 33. It is necessary to insert a decoder into each control signal line between the second level adjustment circuit 35 and the second level adjustment circuit 35.

1g As explained above, according to the digital signal processing circuit according to the present invention, the signal level of an analog signal is adjusted, and a signal corresponding to the gain at that time is used to represent the exponent part of a floating-point digital signal. Signal processing is performed by converting a fixed-point digital signal corresponding to an analog signal into a floating-point mantissa, and level adjustment is performed at the analog signal stage to prevent overflow when converted to a digital signal. This makes it possible to reduce rounding errors and overflow at high input levels, and expand the dynamic range at low input levels.

Note that such a digital signal processing circuit is applied to a digital filter and the like.

[Brief explanation of drawings]

1 and 2 are block diagrams showing a conventional example, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 shows a specific configuration of the first level adjustment circuit in FIG. 1. It is a block diagram. Explanation of symbols of main parts

Claims (1)

[Claims] a first level adjustment circuit that inputs a predetermined analog signal, adjusts the signal level, and outputs a first control signal according to the gain at that time; and an analog signal output from the first level adjustment circuit. an A/D (analog/digital) conversion circuit that converts into a fixed-point digital signal;
a signal processing circuit that processes the fixed point digital signal in floating point according to the first control signal and outputs it as a mantissa part digital signal and a second control signal corresponding to the exponent part; and the mantissa part digital signal. a D/A (digital/analog) conversion circuit that converts the D/A conversion circuit into an analog signal, and a second level adjustment circuit that adjusts the signal level of the analog signal from the D/A conversion circuit in accordance with the second control signal. A digital signal processing circuit comprising: