JPH04354208A - Bit length expanding device - Google Patents

Abstract

PURPOSE:To improve distortion at the reproduction of a small level. CONSTITUTION:A data difference such as 'minimum bit', 'no change', and 'large amplitude change', is extracted from the sampling data of a prescribed bit by a difference extracting circuit 1, inputted to a shirt register 2 and a data pattern by an interval or the like in a change in a small level from the shifty register 2 is extracted by a data pattern extracting device 3 and when a discrimination data such as a minimum bit change interval is long or short is inputted to a shift register 4, the data of a low-order bit (less then LSB) is generated by a data generating circuit 5 based on the discrimination data and the inputted data is fed to an adder circuit 7 together with a data generating timing with a shift register 6 and added, all bits are expanded, before and after the original LSB change is smoothly changed by all bit data and when a small data is reproduced, the quantization distortion by the LSB is decreased.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of reproduction distortion particularly at minute levels when used in digital-to-analog conversion of digital audio and the like.

0002

[Prior Art] Conventionally, in the digital transmission, recording and reproduction of analog signals via AD and DA, one sample data consisting of a limited bit length is used in the digital stage. with commensurate quantization distortion.

0003

Particularly in minute level reproduction, distortion increases as the signal approaches the least significant bit (LSB), so that even with a sine wave signal, distortion increases as the signal approaches a square wave.

0004

SUMMARY OF THE INVENTION Therefore, the present invention provides an apparatus that can perform DA conversion by reducing these minute level quantization distortions and increasing the bit length. To achieve this, by extracting the difference between each sample data of the reproduced digital signal, we extract sections where there is no data change between samples, sections where only 1 LSB change occurs, or larger amplitude changes, etc. We extract a very small level part where there is no change over several samples and only 1LSB changes, and then output a gradual level change over several samples before and after this 1LSB change.
Generate data below B. This generated output is 1LSB
By outputting corresponding to the change point, even when the LSB change point is close, by adding these generated outputs, an extended bit is obtained that makes the data change smoothly overall, and this is converted into analog.

[0005]

Embodiments will be explained below with reference to block diagrams. A block diagram showing the entire system is shown in FIG. 1, and a waveform diagram thereof is shown in FIG. Data Din for each sample, which is a word consisting of reproduced finite-length bits, is used by a difference extraction circuit 1 to detect changes in data between the sample data.

Shift registers 1-1 and 1-2 are provided which move data every sample clock fs as shown in FIG. Differences such as the same data with no change output 0, a change of +1LSB, a change of -1LSB or less, or a large amplitude change H of more than that are extracted. Next, these differential data are input to the shift register 2, and in order to detect these change patterns over several to several tens of samples depending on the purpose, the data are also input to the shift register 2 so as to be shifted using the sample clock.

Based on the data of this Schauft register 2, a minute level section or its change interval (frequency) is extracted, that is, a pattern is extracted, and data generation corresponding to one LSB change, which is a minute level change, is determined. .

The pattern extraction unit 3 generates lower extended data according to the LSB change based on the sample distance from the LSB change point as shown in FIG. Now, two data generation means, F1 corresponding to a relatively gentle low frequency component and F2 corresponding to a high frequency component, will be explained.

As shown in d, the interval of χ in which the intermediate sample changes to -1LSB without data change from the 1LSB change point in the positive direction, or conversely, the interval of χ' from -1 to +1, is shown in (i ), and the interval of the same polarity is (y
) is greater than or equal to (ii), the output of F1 is output from the pattern extraction unit 3 corresponding to the 1LSB change point, and as shown in e, if χ is less than or equal to (i) and greater than or equal to (i'), Make it output F2. (Here, (ii) is not used and F1
F2 No output if both outputs are H input. )

001
0] Based on this pattern output data, the data of F1 and F2 are shifted to the shift register 4, and during this, data of d1 or d1 is shifted for each sample corresponding to F1.
', F2, data as shown in d2 or d2' is generated, respectively. By adding these, extended data is generated, which is added to the upper data and subjected to DA conversion as bit-extended data. Here, the phase of the upper data is adjusted by the shift register 6 in order to align it with the same position as the data generation output.

Using the upper data of the input data a in FIG. 2, the pattern extraction data at each LSB change point is as shown in FIG.
The broken line shown in c in Figure 2 will be obtained.By adding these, a solid line generated output will be obtained, and the overall output when added with the upper data will produce a smooth distortion-free waveform as shown in b in Fig. 2. can.

Further, each part will be explained in detail. Figure 4
The pattern extractor 3 will be explained. The output of F1 is shown in (i) with 17 samples or more and (ii) with 5 samples or more. OR circuits a24 and a8 take +1LSB and H from the outputs of registers 2-24 and 2-8, and by these ORs, counter a12
Clear and counter b1 again with the or of -1 and H
Clear 3. These counters 12 and 13 count 16 samples and output from the 17th sample. When the output of register 2-8 is +1 or -1, the output of counter b13 or counter a1 is cleared with the opposite polarity.
This gate is established by taking the output of 2 and the AND gate G1 or G2.
There is no LSB change and no H signal within around 16 samples where the 1LSB change occurs, and condition (i) is detected.

These outputs are sandwiched between registers 2-8 and OR gates C4 to C12 of the outputs of ±4 sample registers 2-4 to 2-12 are detected by OR gate G3, and are detected by AND gate G4 and AND gate G4', respectively. Take Andgate. This becomes condition (ii). Here, in C4 to C12, inputs other than the same polarity are input, but if there is a reverse polarity or an H signal, G1 or G2 will not hold, and in the end only condition (ii) will hold. These outputs are input into shift register 4. Regarding F2, the take-out position and counter value of the shift register 2 may be set in the same manner. F
If the condition (i') in 2 is 5 or more samples, then F1
Register 2-4 corresponds to register 2-8, and register 2-1 corresponds to the output of register 2-24.
2 and set the counter to 1/2 of 8 samples. Also, there is no need for something equivalent to ORGATE G3 here. Here, if there is an output of F1 in response to one 1LSB change, it will meet the conditions of F2, so F1 can be used to make use of F2.
is not output. Therefore, if F1 is present at gate G5 or G5', F2 is inhibited via an inverter 15 which takes an OR gate of ±F1 and latches a flag of F1 in a latch 14 every time the data changes. As a result, only F1 has a long period, and only F2 has a short period, so that they are not output the same.

As a result, one of the outputs of F1F1' and F2F2' appears corresponding to a predetermined 1 LSB change point, and is input to the shift register 4 and shifted. Here, shift register 4 is used for data generation, and the input timing of F1 and F2 is 4 because 4 samples F2 are output later, corresponding to registers 2-8 and 2-4.
If you delay the input by a sample amount, the timing will be correct. The states of F1 and F2 above are shown in FIG. Here, for convenience of the output from shift register 4, +F
Take the OR of 1 and -F1 and get the ±F1 signal (±1LS
B) and +F1, that is, at the change point due to F1 of ±1LSB, the sign bit (Sign
) and similarly put ±F2 and the sign bit into the shift register 4.

Next, FIG. 6 shows a block diagram of the data generation circuit 5 based on register output. Each register 4-8~
4--8 is divided into left and right parts from the center, and the sign bit output on the left side remains unchanged, while the sign bit on the right side is inverted via the inverter I. Also, the left and right data should be the same data across the center. As shown in Figure 7, there are 8 types of data for F1, D11 to D1.
It is preferable to use 1/4 cycle of the sine wave up to 8 as shown in the figure. This data is output from the register to which ±1 LSB change, ie, F1 or F2, is output for each register. For example, F1 in register 4-8, register 4--4
If there is F2 in , these data will be output from two places. Of course, here these polarities are Sign
Bits are also output at the same time. Here, if the data is 4 bits, everything other than Sign is represented by 3 bits.

In FIG. 8, these data are output by a full adder Σ. Data addition is omitted because various methods are known. Each data can be generated only by wiring in accordance with the necessary data values as shown in FIG. Here, the data is as shown in Figure 7, where 1/4 part of the sine wave is D18~
In response to a + LSB change input like D11 or D24 to D21, positive data rises, becomes negative data across the center, and then reverses and decreases to 0. In the -1 LSB change, since the Sign bit is 0, the data changes in the opposite way, with negative data increasing, becoming positive across the center, and decreasing toward 0.

[0017] As a result, d1 or d2 shown in FIG.
Obtain data corresponding to etc. In the addition output of Fig. 5,
As shown in data C in FIG. 2, this becomes one generated output, and by adding it to the upper data, bit-expanded smooth data with little distortion can be obtained.

In the embodiment, two types of data generation have been explained, but of course it is possible to increase the frequency range to correspond to a wide frequency range, and it is also possible to correspond to a 2LSB change, etc., and it is possible to correspond to a single change. Even if only one data is generated, the output data of the changing points are added up one after another, so the final data connection can correspond to a waveform with a smooth and wide frequency change as shown in the figure.

[0019]

[Effects of the Invention] As described above, according to the present invention, even if there is an LSB change due to a small signal, the output signal can smoothly correspond to a waveform with a wide frequency change, and noise caused by pulse distortion can be removed. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a diagram for explaining waveforms.

FIG. 3 is a block diagram showing difference extraction.

FIG. 4 is a block diagram illustrating a pattern extractor.

FIG. 5 is a diagram showing timing.

FIG. 6 is a block diagram of a data generation circuit.

FIG. 7 is a diagram for explaining data-generated signals.

FIG. 8 is a block diagram showing addition.

[Explanation of symbols] 1 Difference extraction circuit 2-1~n Shift register 3　　　　　　　Pattern extraction section 4 Shift register 5 Data generation circuit 6 Shift register 7 Adder circuit

Claims (1)

[Claims] 1. An apparatus for DA converting a sample data string having a predetermined word bit length, comprising means for extracting a difference between sample data and detecting minute level changes and change intervals between the data; It is equipped with means for generating data less than or equal to the LSB of the sample data corresponding to the above detection over several samples before and after the detection, and means for adding the data generation output of each minute level change to form one lower data, and adding the data to the upper sample data. Added LS
A bit expansion device characterized by making a smooth level change before and after a slight level change using bits of B or less.