JPH04115626A - Digital/analog converter device - Google Patents

Abstract

PURPOSE:To improve an error at the time of low level output while acquiring high resolution by always making first main output data to be outputted when a first and a second main DACs are used in response to the increase of input data to a positive or a negative direction a positive or a negative maximum value. CONSTITUTION:A digital data conversion circuit 1 inputs the input data of N-bits showing a positive or a negative decimal value, and outputs the first main output data of M-bits (M<N) showing the positive or the negative decimal value and a second main output data of N-bits showing the positive or the negative decimal value. The first and the second main digital/analog conversion circuits(DAC) 2A, 2B D/A-convert the first and the second main output data into analog signals, and an analog addition circuit 5 adds each analog signal so that the weights of a first and a second LSBs coincide with each other. Then, the first main output data to be outputted is made always the positive or the negative maximum value. Thus, an output error at the time of the low level output can be reduced while acquiring the high resolution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital/analog conversion device suitable for use in digital audio equipment such as a compact disc (CP) player, a digital audio tape (DAT) recorder, etc. By using a DAC (hereinafter abbreviated as DAC),
The present invention relates to a digital/analog conversion device that can improve output errors when outputting low level while achieving high resolution.

[Prior art] Generally, a DAC has ±1/2LS over the entire output level range.
Although they are manufactured to satisfy a nonlinear output error of B or less, high-resolution ACs such as DACs used in digital audio equipment do not have perfect weight accuracy on the upper bit side even when adjusted by laser trimming. ,
Many of them do not satisfy the above-mentioned output error. Therefore,
Although the upper bit side, which is the cause of output errors, can be further adjusted externally, this also has various problems, such as being susceptible to changes in temperature, humidity, and vibrations.

Furthermore, in order to simplify the circuit configuration, most of the DACs used in digital audio equipment are composed of unipolar output DACs, and the output is given a midpoint offset to create a bipolar output (bipolar output). Since the input data represents an audio signal, it is output as unipolar, and the DC offset generated in the output is removed by a coupling capacitor, a DC servo circuit, etc.

In digital audio equipment, the digital data that is input to the DAC is represented by a 2'S combination code or binary offset code that indicates a bipolar analog signal (positive and negative decimal values), so the low-level analog Even when a signal is indicated, the upper bit side is in the 771N state.

Therefore, in the case of the above-mentioned DAC, even when digital data indicating a low-level analog signal is input, the output includes the output component on the high-order bit side, and as a result, the analog signal becomes low level. Despite this, the output error does not decrease.

On the other hand, data shift circuits, mantissa DACs, one index DACs, etc., conventionally called floating DACs, index DACs, etc.
A digital/analog conversion device consisting of
No. 5) Proposed in publications, etc.

[Problems to be Solved by the Invention] According to this digital/analog conversion device, digital data is shifted to the upper bit side in response to the level of an analog signal indicated by the digital data, and D/A conversion is performed by the mantissa DAC. By doing so, it is possible to substantially reduce the output error when outputting a low level, but when outputting a high level, the resolution of the mantissa DAC needs to be increased, which complicates the configuration. Since it employs a configuration of two connected DACs, there is a problem in that the switching noise of the exponential DAC is included in the analog signal.

[Circuit for Solving the Problems] The present invention provides a digital/analog conversion device that can achieve high resolution and improve output errors during low-level output without causing the above-mentioned problems. The first device of the present invention inputs input data of N bits indicating positive and negative decimal values, and inputs the first main input data of M (M<N) bits indicating positive and negative decimal values. digital data converting means for outputting output data and N-bit second main output data indicating a positive/negative decimal value; and a D/A converter for converting at least the first main output data into an analog signal.
a first main DAC capable of converting; and a second main DAC capable of D/A converting at least second main output data into an analog signal.
and an analog adding means for adding each analog signal so that the weight of the LSB of the first main output data and the weight of the LSB of the second main output data match.

Further, the second device of the present invention has N
The first main output data of M (MAN) bits indicating a positive or negative decimal value, the second main output data of N bits indicating a positive or negative decimal value, and the second main output data of 1 bit indicating a positive or negative decimal value are input. a first main DAC capable of D/A converting at least the first main output data into an analog signal; and a first main DAC capable of D/A converting at least the second main output data into an analog signal. A second main DAC capable of A conversion, sub-output means capable of converting at least sub-output data into an analog signal, LSB weight of the first main output data, LSB weight of the second main output data, and sub-output means capable of converting at least sub-output data into an analog signal; It is comprised of an analog addition means for adding each analog signal so that the bit weights of the output data all match.

[Operations] According to the first device of the present invention, the digital data converting means converts the first data in response to an increase in the input data in the positive or negative direction.
Although each output data is output to perform D/A conversion of input data using at least the main DAC 1 or the first and second main DACs, the first and second main DACs
When using , the first main output data to be output is always the maximum positive or negative value.

Further, according to the second device of the present invention, the digital data converting means converts the first main DAC 1 or the first and second main DACs in response to an increase in the input data in the positive or negative direction.
Although each output data is output to perform D/A conversion of input data using at least an AC, when the first and second main DACs are used, the lower order (M-1) of the second main output data to be output is The sub-output data is output so that the bits are all in the same or opposite states as the lower (M-1) bits of the input data, and the first main output data to be output is always set to the maximum positive or negative value.

[Example] Hereinafter, a first example of the digital/analog conversion device of the present invention when applied to a CD player is shown in FIGS. 1 to 4.
This will be explained with reference to the figures.

FIG. 1 shows a block diagram of the device of the first embodiment. Input data of an 18-bit, 2' S combination code output from a digital filter (not shown) is input to the input terminal D1 of the digital data conversion circuit 1. ~D
18, and as shown in the data conversion table in Figure 2, the 16-bit first main output data, the 18-bit first main output data, and the 18-bit first 2 main output data and 1 bit sub output data, respectively, are output to the output terminal (AI-A1
6), (Bl-B18), and (sl).

The output first main output data is input to the upper 16 bits of the first main DAC 2A with an 18-bit resolution and is D/A converted into an analog current converter, and the second main output data is input into the upper 16 bits of the first main DAC 2A with an 18-bit resolution. 2 main DAC 2B
The signal is input to the analog current controller 2 and is D/A converted.

Note that the input of the lower two bits of the DAC 2A is connected to the ground and is always in the "O" state. In addition, DAC2A and DAC2B are composed of two DACs with the same circuit configuration integrally formed in order to have the same characteristics, and the output currents 1 and 2 have main output data of positive 1.
When it shows a decimal value, it moves towards the inside of the DAC (in the direction of the arrow in the drawing), and when it shows a negative decimal value, it moves towards the DAC.
Flows outward.

Also, since DAC2A and 2B have a high resolution of 18 bits, 18 bit data can only be digitized with 1816 bit precision.
/A conversion is not possible. That is, each DAC is ±2L
A nonlinear output error of SB occurs.

Note that D/A conversion of n-bit data with an output error of ±2 LSB or less is referred to as (n+m-1) bit precision.

On the other hand, the sub output data is +I of the second main DAC 2B.
In order to assist the LSB output, it is input to the sub-output circuit 3 composed of resistors R2 to R4, and the +ILS of the DAC2B
The current value (absolute value) corresponding to B is converted to the same current value 3.

Note that the sub-output circuit 3 is composed of only a resistor to convert the logic level voltage (5■) when the sub-output data becomes "1" state into a predetermined current.
The direction of its output current is DAC2 as shown in the figure.
Although the direction is opposite to that of the output current (2) of B, the relative direction is made to match by inverting the state of the sub output data with respect to the original state, as will be described later. That is, the current I3 flows when the +ILSB output of the DAC 2B is not assisted, and when it is assisted.

Then, the output current I□ of the DAC2A is I/V converted to a voltage ■1 with a gain α by the I/V conversion circuit 4A constituted by the OP amplifier A1 and the resistor R, and the DAC2A
After the output current 2 of B is added to the output current of the sub-output circuit 3, it is converted by the I/V conversion circuit 4B to a voltage v2 with the same gain .alpha./V. Note that if there is a difference in slew rate, phase characteristics, etc. between the I/V conversion circuits 4A and 4B, pulse-like noise (glitch) will occur in the output signal of the analog addition circuit 5, which will be described later. They are composed of the same circuit.

Then, each output voltage V, v2 is added in an analog manner at a gain ratio of 1/4:1 by an analog adder circuit 5 composed of an OP amplifier A2 and resistors R5 to R.
aliasing components accompanying D/A conversion are removed, and the coupling capacitor C removes the DC offset generated in the sub output circuit and I/V conversion circuit, and the signal is output as an analog signal from the analog output terminal 7. Ru.

In the above embodiment, the first main output data, second main output data, and sub output data for the input data are 35B-LSB of the input data, as shown in FIG.
The weights of the MSB-LSB of the first main output data match, the weights of the MSB-LSB of the input data match the weights of the MSB-LSB of the second main output data, and the weights of the MSB-LSB of the input data match, respectively. The weight of the LSB of data and the weight of sub-output data match. Therefore, the MSB-LSB weight of the first main output data and the 3S of the second main data
The weights of the B-LSBs also match, and the weights of the LSB of the first main output data, the weights of the LSB of the second main output data, and the weights of the sub-output data also match.

The details of the above-mentioned data conversion table shown in FIG. 2 will be explained below while taking this weighting relationship into consideration. In addition, () after each data
The inside shows the decimal value.

First, the input data for the sub output data is "11100...
・00''～“00011...11” (-13107
2 to +32767), it is always “1” (+1), and “00100...00” to “01111...1
1” (+32768 to +131071), it is always “o” (o).As mentioned above, the sub output data is set by changing the direction of the output current of the sub output circuit 3 to the output current of the main DAC 2B. In order to match the direction of , the state is reversed from the original state.

Next, the first main output data is input data “111”.
00...00"~"00011...11" (-3
2768~+32767), 1 indicated by the input data
"1000...ooo" to "01" to indicate the decimal value
11...111" (-32768 to +32767), and the input data changes to "00100...00" (
+32768) or more, it always becomes “0111...111” (+32767), which indicates the maximum positive value, and the input data becomes “11011...11” (-32
769) or below, “1” always indicates the maximum negative value.
0oo...000" (-32768).

Next, the second main output data is input data “111
00...00"~"00011...11" (-3
2768~+32767), it is always "oooo...
000” (0), and the input data becomes “00100”.
...00''' (+32768) ~ "01111・
...11" (+131071), the decimal value indicated by the input data becomes 1 indicated by the first main output data.
000 to indicate the value obtained by subtracting the decimal value (+32767) and the decimal value (+1) indicated by the original sub output data.
0...000"~"0101...ut" (0~
+98303) respectively. In addition, the second main output data has input data “11011...1” to “
10ooo...00" (-32769~-1310
72), "1111...111" to "1" indicate the value obtained by subtracting the decimal value (-32768) indicated by the first main output data from the decimal value indicated by the input data.
010...ooo" (0 to -98304), respectively.

In this way, the first and second main output data and sub-output data change so that when the decimal values indicated by each are added together, they become the same as the decimal value indicated by the input data, In particular, the sub output data changes so that the lower 15 bits of the second main output data are in the same state as the lower 15 bits of the input data.

Below, as shown in the same diagram, the input data is “001
UP the range that is greater than or equal to “00...00” (+32768), “11011...11” (-32769)
DOWN the following range, remaining “11100...0”
0"~"00011...11" (-32768~+
32767) as MID, a detailed circuit example of the digital data conversion circuit 1 that achieves the data conversion shown in FIG. 2 will be described with reference to FIG. 4.

First, a data value detection circuit is configured to detect which of the above ranges the input data is included in.

To detect whether the input data is within the UP range,
It is only necessary to detect that the MSB is "0" and that both 28B and 38B are not "0", so input terminal D1 is set to INVI.
input terminal D to the input of ANDII (7) through O.
2, D3 are each I NVERT-NAND (hereinafter, I
-NAND)) connected to each of the 12 inputs, I-
The output of NAND12 is connected to the other input of ANDII.

According to this circuit configuration, when the input data is in the UP range, the output of ANDII becomes "1".

Next, to detect whether the input data is within the DOWN range, the MSB must be “1” and both 28B and 38B must be “1”.
It is only necessary to detect that it does not become 1", so input terminal D1
is connected to one input of AND13, input terminals D2 and D3 are connected to each input of NAND14, and the output of NAND14 is connected to the other input of AND13. According to this circuit configuration, when the input data is in the DOWN range, the output of AND13 becomes u 1 h.

In order to detect whether the input data is within the MID range, it is sufficient to detect that it is not within the UP or DOWN range, so the ANDII and AND13 (7) outputs are respectively INVERT-AND (hereinafter referred to as , I-AND) are connected to each of the 15 inputs, and the input data is connected to the MID
When in the range of , the output of I-AND 15 becomes "1".

Based on the output of this data value detection circuit, sub output data and first and second main output data shown in FIG. 2 are formed.

As shown in Figure 2, the sub output data becomes "1" only when the input data is in a range other than UP, so the AND
II(7) output (UP) is connected to INV16 and indicates sub output data.

The formed sub-output data has a time lag with the main output data due to the delay time of each logic circuit, so the INV
16 is connected to the data terminal D1 of the latch circuit 17, and is latched based on the latch clock LCK having a predetermined phase delay with respect to the output clock of the input data. It is output from the output terminal S1 of the circuit 1.

On the other hand, the MSB of the first main output data is in the same state as the MSB of the input data regardless of the range of the input data, so the state of the input terminal D1 immediately changes to the MSB of the first main output data. shows.

The 25B-LSB of the first main output data is
45 of the input data when the input data is within the MID range
They are in the same state as B-LSB, and all become "1'" when in the UP range, and all become "0" when in the DOWN range.

Therefore, input terminals D4 to D20 are AND 18 to 3, respectively.
2 and the output of AND13 (DOW
N) is connected to the other input of each of the ANDs 18 to 32 via the INV33. In addition, the outputs of AND18-32 are connected to one input of 0R34-48, respectively, and
The output of DII (UP> is connected to the other input of 0R34 to 48. With the above connections, ○R34 to 48
The outputs of each are 23B-LSB of the first main output data.
will be shown.

The formed first main output data also has a time lag in the same way as above, so the input terminals D1.0R34-48
The outputs of the data terminals D1 to D18 of the latch circuit 49 respectively
The output terminals are connected to and latched based on the latch clock LCK, and outputted from the output terminals Q1 to Q16 thereof and further from the output terminals A1 to A16 of the digital data conversion circuit 1.

Next, the MSB of the second main output data becomes 1 (I 11) only when the input data is in the DOWN range, so
The output state (DOWN) of AND13 immediately indicates the MSB of the second main output data.

Then, 2SB and 38B of the second main output data are 28B and 38B of the input data when the input data is in the UP range.
It is the value obtained by subtracting "Ol" from 35B, and when the input data is in the DOWN range, 25B and 35B of the input data
The value is obtained by adding "01" to

Therefore, input terminals D2 and D3 are input terminals A1 . A2, and the output of ANDll is connected to the input terminal B1 of the digital addition circuit 50, and the input terminal B2 is connected to the power supply. and the data value consisting of 38B and 4111 II, and when the input data is in the DOWN range, 28B
Add the data value consisting of and 35B and It 0171,
The lower two bits are outputted from output terminals Q1 and Q2.

Furthermore, It 11? The value of the lower two bits as a result of adding + is the same as the value obtained by subtracting II 01 II.

Furthermore, since the second main output data 23B and 38B become "0" when the input data is within the MID range, the output terminals Q1. Q2 is AN
Connected to one input of D52.53, I-AND15
The output (MID) is AND52.5 via INV51
3(7) each connected to the input of the other. With the above connection, the outputs of AND52 and 53 respectively indicate 28B and 33B of the second main output data.

The 4SB-LSB of the second main output data are all 0'' when the input data is within the MID range, and are the same as the 4SB-LSB of the input data when the input data is outside the range.

Therefore, input terminals D4-D18 are AND54-68, respectively.
The output of INV51 is connected to the input of each other. With the above connections, AND54 ~
68 outputs are 4SB-L of the second main output data, respectively.
Indicates SB.

Since the formed second main output data also has a time lag in the same manner as described above, the outputs of AND13. , the output terminals Q1 to Q18, and further the output terminal of the digital data conversion circuit 1, the operation of the device of the first embodiment will be explained.

First, "11100...00" to "00011...
The operation while input data within 11" (-131072 to +131071) is input will be explained.

During this time, the input terminal Di (sub output data) of the latch circuit 17 is always 111 I+ since the output (UP) of ANDII becomes "0" (FIG. 3).

Furthermore, since the input terminal Di (MSB of the first main output data) of the latch circuit 49 is connected to the input terminal D1 of the digital data conversion circuit 1, the MSB of the input data
The input terminals D2 to D16 (28B-LSB of the first main output data) change to the same state as the output of AND13 (DOWN) and the output of ANDII (UP).
Since it is turned on, it changes to the same state as 48B-LSB of the input data. That is, during this time, the first main output data becomes data indicating the decimal value indicated by the input data. For example, input data is "00010...oo"
(+16384), the first main output data is “
0100...000" (+16384), when the input data is "11111...10" (-2),
The first main output data is 1111...110'' (
-2).

On the other hand, since the input terminal Di (MSB of the second main output data) of the latch circuit 69 is connected to the output (DOWN) of the AND13, it always becomes "011" and the input terminal D2
~D18 (28B-LSB of second main output data)
Since the output (MID) of AND15 becomes "1", all become "0".

That is, during this time, the second main output data is always "000".
...becomes 00" (0).

The sub-output data and the first and second main output data described above are each taken into each latch circuit based on the rising edge of the latch clock LCK, thereby eliminating the time lag between bits in each data and the time lag between each data. is removed and output from each output terminal of the digital data conversion circuit 1. In this case, only the first main output data changes, so only the time lag between bits in the first main output data is removed.

The output first main output data is D/A converted into an analog signal (current I/V) by the DAC2A.
The conversion circuit 4A converts the voltage V□ (V1=I, 'R,)
It is converted to I/V (Fig. 1).

Then, the second main output data is D/A converted into an analog signal (current 2) by DAC2B, but since its value is always "0000...000", the current 2 also always remains zero. . On the other hand, the sub output data is always 4
11 I+, so the output current of sub-output circuit 3 also always flows equivalent to ILSB of DAC 2B. Therefore, electrician,
Only the I/V conversion circuit 4B outputs a voltage V, (V, = -
LR, )4;: will be subjected to I/V conversion.

These output voltages v1 and v2 are added at a ratio of 1/4:1 by the analog adder circuit 5, and the added voltage V3 (V,
= R, ((L/4) -
/V conversion circuit) is removed and output from the analog output terminal 7.

In this way, "11100...00" to "00011"
...11" (-32768 to +32767) is being input, the input data is substantially the first
Since D/A conversion is achieved only by the main DAC 2A, the output error of the analog signal output from the analog output terminal 7 is also determined only by the output error of the DAC 2A.

Here, as mentioned above, the DAC 2A performs D/A conversion on 18-bit input data with an error of ±2LSB or less, but the first main data is D/A converted using its upper 16 bits.
By converting, the output error appears to be 1/4
+1 for the 16-bit first main data
D/A conversion can be performed with an error of /2LSB.

That is, for the input data between the above, the device of this embodiment has 1
Even though a 6-bit precision DAC is used, it is possible to perform D/A conversion in the same way as a DAC with 18-bit resolution and precision.

Next, "001(to...00" to "01111...
・The operation while input data within 11" (+32768 to +131071) is being input will be explained.

During this time, the input terminal D1 of the latch circuit 17. (Sub output data) becomes 1101+ because the output (UP) of ANDII becomes "1".

Furthermore, since the input terminal Di (MSB of the first main output data) of the latch circuit 49 is connected to the input terminal D1 of the digital data conversion circuit 1, the MSB of the input data
LL OIT is in the same state as the input terminal D2-D1.
6 (28B-LSB of first main output data) is AN
DI3 output (DOWN) + ANDI 1 output (U
P) becomes “0” and “1” respectively, so all tt 1 y+
become. That is, the first main output data is always the plus maximum data "011]1" (+32767).

On the other hand, since the input terminal DI (MSB of the second main output data) of the latch circuit 69 is connected to the output (DOWN) of ANDI3, it is always 1'O'', and the input terminal D2
, D3 (2SB, 33B of the second main output data) indicates the output (UP) of ANDll + I-A
The outputs (MID) of NDI5 are each “1” 11 Q
Since it is an IT, "01'" is subtracted from the lower 2 bit value obtained by digitally adding the data value consisting of 28B and 35B of input data and rt 11 u, that is, the data value consisting of 28B and 38B of input data. value. In addition, the input terminals D4 to D18 of the latch circuit 69 are I-AN
Since the output (MID) of D15 becomes "0", it changes to the same state as 48B-LSB of the input data. That is, during this period, the second main output data is +32768 from the decimal value indicated by the input data (+32768 from the decimal value indicated by the first main output data "011...11")
67) and the original sub output data (10 shown by 11IT)
The data indicates the value obtained by subtracting the decimal value (the value obtained by adding +1). For example, if the input data is "00100...00"
” (+32768), the second main output data is “'oooo...000” (0), and when the input data is “01111...11” (+131071), the second main output data is “0101...111
” (+98303).

The sub-output data and the first and second main output data described above are each taken into each latch circuit based on the rising edge of the latch clock LCK, thereby eliminating the time lag between bits in each data and the time lag between each data. is removed and output from each output terminal of the digital data conversion circuit 1.

The output first main output data is D/A converted into an analog signal (current signal X) by the DAC2A, and the I/V
The conversion circuit 4A performs I/V conversion to voltage V (V□=1□・R) (FIG. 1).

The second main output data is then D/A converted into an analog signal (current I2) by the DAC 2B. on the other hand,
Since the sub output data is always 0'', the output current of the sub output circuit 3 is zero.

Therefore, only the output current of the sub-output circuit 3 is I/V converted by the I/V conversion circuit 4B to the voltage V, (V2=L·R,).

becomes zero, so that the voltage v2 becomes substantially +
This means that the ILSB has increased considerably.

These pressure voltages V□, v2 are added at a ratio of 1/4:1 by the analog addition circuit 5, and the added voltage V3 (V, =
R, ((I, /4) - L) ) is D by LPF6
The aliasing component accompanying the /A conversion is removed, and the DC component (DC offset generated by the I/V conversion circuit) is removed by the coupling capacitor C□, and the result is output from the analog output terminal 7.

In this way, "00100...00" to "01111"
...11” (+32768 to +131071) is being input, the input data is substantially the first
and D/D by the second main DAC and sub output circuit 3.
Since A conversion is achieved, the output error of the analog signal output from the analog output terminal 7 also becomes the sum of the output errors of the DACs 2A, 2B and the sub-output circuit 3. However, since the output error of the sub-output circuit 3 can be easily reduced, it can be ignored in practice.

Therefore, if the output error of the sub-output circuit 3 is ignored, in the device of this embodiment, the DAC 2A outputs D with an error of ±1/2LSB to the 16-bit first main data, as described above.
/A conversion, but DAC2B performs D/A conversion on the 18-bit second main data with an error of ±2LSB, so the input data between the above is converted with an error of 2°5LSB after adding up each output error. Perform D/A conversion. That is, for input data between the above, the device of this embodiment performs D/A conversion of the input data with a resolution of 18 bits and an accuracy of approximately 16 bits, which is the original performance of the DAC 2.

Note that according to the device of this embodiment, the input data is “0010
0...00"～"01111...11" (+3
2768~+131071), the first main output data will be "011...11" (+
32767), that is, the output current of DAC2A is always kept at the maximum positive value, so even if there is a difference in output operation timing between DAC2A and 2B, I/V conversion circuit 4
Even if there is a difference in slew rate or phase characteristics between A and 4B, glitch noise will not be caused in the analog signal output from the analog output terminal.

Furthermore, the input data is "11100...00" to "0"
0011...If'' (-131072~+1310
71) from “0 (1100...00” to “0111”)
1...11" (+32768~+131071)
Even if the output current of DAC2A changes within or vice versa,
Since the output current 2 and the output current 2 of the DAC 2B always change in the same direction, even if there is the above-mentioned deviation, the analog signal only changes stepwise, and the most harmful glitch noise is not caused.

Next, "10oo...00" to "11011...
The operation while input data of 11" (-131072 to -32769) is being input will be explained.

During this time, the input terminal Di (sub output data) of the latch circuit 17 is “θ” because the output (UP) of ANDII becomes “θ”.
It becomes 1”.

Furthermore, since the input terminal Di (MSB of the first main output data) of the latch circuit 49 is connected to the input terminal D1 of the digital data conversion circuit 1, the MSB of the input data
The input terminals D2 to D16 (28B to LSB of the first main output data) become "1" in the same state as AND13.
The output (DOWN) of ANDll and the output (UP) of ANDll become "1" and "O", respectively, so they all become "O", that is, the first
The main output data is always minus maximum data “100
0...00" (-32768).

On the other hand, the input terminal Di (MSB of the second main output data) of the latch circuit 69 is always 1" because it is connected to the output (DOWN) of the AND13, and the input terminals D2, D
The data value indicated by 3 (23B, 38B of the second main output data) is the output (UP) of ANDll, I-AND
Since the outputs (MID) of 15 are respectively It 031.00'', the value of the lower 2 bits obtained by digitally adding the data value consisting of 28B and 38B of input data and 1101 PI, that is, from 25B and 38B of input data. It is the value obtained by adding "01" to the data value. Also, the latch times N
Since the output (MID) of I-AND 15 becomes "0", the input terminals D4 to D18 of r69 change to the same state as 48B-LSB of the input data. That is, during this time,
The second main output data is -32768 from the decimal value indicated by the input data (the first main output data "100.
...The decimal value (-32768) indicated by "00" and the decimal value (0) indicated by the original sub-output data "0") are subtracted.For example, the input The data is “11011...11” (-32769
), the second main output data is '1111...1
11" (-1), the input data is "10000...
00" (-131072), the second main output data becomes "1010...000" (-98304).

The sub-output data and the first and second main output data described above are each taken into each latch circuit based on the rising edge of the latch clock LCK, thereby eliminating the time lag between bits in each data and the time lag between each data. is removed and output from each output terminal of the digital data conversion circuit 1.

The output first main output data is D/A converted into an analog signal (current input) by the DAC2A, and the I/V
The conversion circuit 4A performs I/V conversion to a voltage V (V□=D)/R (FIG. 1).

The second main output data is then D/A converted into an analog signal (current L) by the DAC 2B. On the other hand, since the sub output data is always 1", the current □ of the sub output circuit 3 always flows equivalent to the ILSB of DAC 2B. Therefore, the current I, 1, is the current of the I/V conversion circuit 4 B Voltage VZ (v.

=R, (I2-L)).

This output voltage V, v2 is added at a ratio of 1/4:1 by the analog adder circuit 5, and the added voltage 3 (V3=
R1 (I, /4) - (L + l3)), the aliasing component accompanying D/A conversion is removed by LPF6, and the DC component (sub output circuit, I
/V conversion circuit) is removed and output from the analog output terminal 7.

In this way, "1000...OO" ~ "11011"
. . 11" (-131072 to -32769) is being input, the input data is substantially D/A converted by the first and second main DACs.

The output error of the analog signal output from the analog output terminal 7 is also the sum of the output errors of DAC 2A and 2B (±2
．． 5LSB).

Therefore, even for input data between the above, the device of this embodiment performs D/A conversion of the input data with a resolution of 18 bits and an accuracy of approximately 16 bits, which is the original performance of the DAC 2.

Also, if the input data is "1000...00" to "110"
11...11" (-131072 to -32769
), the first main output data is “
100...00'' (-32768), i.e., DA
Since the output current 1 of C2A is always kept at the negative maximum value, the bit switch operation timing difference between DAC 2A and 2B and I/V conversion circuits 4A and 4 will occur as described above.
Even if there is a difference in slew rate or phase characteristics between B,
Glitch noise is not caused in the analog signal output from the analog output terminal.

Furthermore, the input data is "11100...00" to "0"
0011...11" (-131072~+1310
71) “1000...00” to “11011・
...11" (-131072 to -32769) or vice versa, the output current of DAC2A and D
Since the output current 2 of AC2B always changes in the same direction, even if there is the above-mentioned deviation, the analog signal will only change stepwise.
An embodiment will be described with reference to FIGS. 5 to 8. It should be noted that since this second embodiment omits the sub-output circuit 3 from the first embodiment, only the differences in the circuit will be explained.
The same numbers are given to the same parts as in the first embodiment.

FIG. 5 shows a block diagram of the device of the second embodiment, and its circuit configuration differs from that of the first embodiment in that the sub-output circuit 3 is omitted.

Therefore, when the digital data conversion circuit 1' receives 18-bit input data, it outputs the first and second main output data corresponding to the data value, as shown in the data conversion table in FIG. It is configured.

Furthermore, as shown in FIG. 7, the first main output data and the second main output data for the input data in this embodiment are the weights of the MSB to LSB of the input data
The weights of the 38B-LSB of the input data and the weights of the MSB-LSB of the second main output data match, respectively.

The details of the above-mentioned data conversion table shown in FIG. 6 will be explained below while taking this weighting relationship into consideration.

First, the first main output data is input data "11100...00" to "00011..." as in FIG.
11" (-32468 to +32767), "1000...oo" indicates the decimal value indicated by the input data.
"~"0111...11" (-32468~+32
767) respectively, and the input data changes to “00100...
・When the value exceeds 00” (+32768), it always returns “01”.
11...11" (+32767), "11011
...11" (-32769) or less, it is always "1"
0oo...QQ" (-32768).

Similarly to FIG. 2, the second main output data also has input data ranging from "11100...00" to "00011...
・Always “ during 11” (-32768 to +32767)
000...00''(0), ``11011・
・・11"～"10000...00" (-327
69 to -131072), 10 indicated by the input data
-32768 from the decimal value (first main output data “10
"1111...111" to "1010...0" to indicate the value obtained by subtracting the decimal value indicated by "0...00"
00" (-1 to -98304), but since there is no sub-output data, the input data changes to (+3
2768 to +131071), "oooo... 001"～"0110・
...ooo" (o~+98303).

In this way, the value obtained by adding the decimal values indicated by the first and second main output data is the 10 indicated by the input data.
Changes as much as possible to be the same as the hexadecimal value.

Next, a circuit example of the digital data conversion circuit 1' that accomplishes the data conversion shown in FIG. 6 will be explained with reference to FIG.

First, in order to detect which of the above ranges the input data falls within, logic circuits 10 to 16 are connected to form a data value detection circuit in the same way as in the first embodiment, and logic circuits 18 to 48 are connected in the same way. ．． By connecting the latch circuit 49, first main data is formed and output from the output terminals A1 to A16 of the digital data conversion circuit 1.

On the other hand, since only the second main data is slightly different from the first embodiment, it is connected as follows.

First, the MSB of the second main output data becomes at 1 pp only when the input data is in the DOWN range, so the output state (DOWN) of AND13 immediately indicates the MSB of the second main output data. .

The 28B-LSB of the second main output data is the 28B-LSB of the input data when the input data is in the UP range.
It is the value obtained by subtracting “00111111111111111” from the LSB, and when the input data is in the DOWN range, the 2SB-LSB of the input data is '010oooooo.
oooooooooo” is added.

Therefore, the input terminals D2 to D18 are connected to the input terminals A1 to A17 of the digital adder circuit 50', respectively, and the ANDl
The output of l is input to the input terminals B1 and B of the digital adder circuit 50.
17, input terminal B2 is connected to the power supply, input terminal B3 is connected to
~B18 is connected to ground.

Therefore, when the input data is in the UP range, the digital adder circuit 50' adds "11000000000000001" to the data value consisting of 28B-LSB of the input data, and when the input data is in the DOWN range, the digital adder circuit 50' adds 25B-LSB to the data value consisting of 28B-LSB of the input data.
Data value consisting of LSB and “0100000000oo
ooooo" and outputs the lower 17 bits from output terminals Q1 to Q17. Note that 28B of input data
-The value of the lower 17 bits of the result of adding “11000000000000001” to the LSB is “0011111”
1111111111'' is subtracted.

Furthermore, 2SB-LSB of the second main output data is "ooo" when the input data is in the MID range.

ooooooooooooooo", the output terminals Q1 to Q17 of the digital adder circuit 50" are ANDed, respectively.
Connected to one input of 52 to 68, I - AND 1
5 output (MID) is AND52~ via INV51
68 inputs. With the above connections, the outputs of ANDs 52 to 68 each indicate 28B-LSB of the second main output data.

The outputs of AND13.52-68 are connected to the data terminals D1-D18 of the latch circuit 69, respectively, and are latched based on the latch clock LCK.
Q18 and further output from output terminals B1 to B18 of the digital data conversion circuit 1.

In this way, the second embodiment does not require the sub-output circuit 3, but as described above, the digital adder circuit 50
' requires 17-bit operation, which has the disadvantage of complicating the circuit configuration.

Note that the operation in this second embodiment is based on the second main D.
The only difference is that AC2B outputs an amount corresponding to the output of sub-output circuit 3, so a detailed explanation thereof will be omitted.

Note that the device of the present invention is not limited to the first and second embodiments described above, but can take various forms.

For example, when the input data represents an audio signal,
When the analog signal does not require a DC component, within the range that does not overflow to the second main output data (in the first embodiment, "1110...ooo" to "00")
Any offset data (within the range of 10...000") can be added. Note that the DC generated in the output of the second main DAC due to the addition of the offset data to the second main output data The offset is removed by providing a coupling capacitor, a DC servo circuit, etc. at the final stage of the analog circuit.

In addition, although the digital data conversion circuit is mainly composed of logic circuits, it is also possible to use a ROM that uses input data as an address.
, a digital signal processor (DSP), or the like.

In addition, although the input data and main output data are represented by a 2'S combination code, they may also be represented by a binary offset code, and the input data and main output data are not necessarily represented by the same code. but not limited to. Furthermore, when the output of the DAC is in reverse phase due to the configuration of the analog circuit, the output data takes an inverted state.

Further, the number of bits of each data is not limited to the above embodiment, and the first main DAC may also have the same resolution (16 bits) as the first main data. In this case, the 16-bit first main DAC is
D whose 8-power error is less than the second main DAC
AC must be used.

However, if the first main DAC is connected to the second main DAC
Using a DAC with a resolution different from C is an independent DA.
Since C is used, differences in gain characteristics due to temperature changes are likely to occur between the DACs. This is equivalent to an error in the addition ratio of the analog adder circuit caused by a temperature change, which causes distortion in the analog signal, which is not very desirable.

Furthermore, the DAC may have either bipolar output or unipolar output, and when a bipolar output DAC is used, the amount of DC offset that occurs is small, so the coupling capacitor can be omitted. be.

Further, the coupling capacitor can also be changed to a DC servo circuit or the like.

In addition, although a parallel input DAC is used to simplify the explanation, a serial input DAC may also be used. In particular, when using a serial input main DAC in the first embodiment, digital data conversion The circuit is configured not only to serially output main output data but also to output sub output data at a timing synchronized with the conversion clock of the main DAC.

Furthermore, it goes without saying that the sub-output circuit may also be composed of a constant current circuit, a switching circuit, etc. in order to improve output accuracy.

Furthermore, the analog circuit section including the I/V conversion circuit that adds the output of each main DAC and the output of the sub-output circuit, and the analog addition circuit is not limited to the above-mentioned example circuit. , any changes may be made as long as the weight outputs of the LSB of each output data are added to be the same.

[Effects of the Invention] As explained above, according to the device of the present invention, while achieving high resolution, it is possible to perform D/A conversion with high precision for input data representing a low level, so it is particularly suitable for digital audio. High sound quality can be obtained by using it in equipment.

In addition, the output of the first main DAC and the output of the second main DAC
Since the outputs of the two main DACs are simply added together, switching noise is not included in the analog signal unlike in conventional devices, and while the input data changes slightly, only the output of one main DAC changes, and the output of the other main DAC changes. Since the output of the main DAC is constant, even if there is a difference in output timing between main DACs or a difference in slew rate or phase characteristics between I/V conversion circuits, there will be no pulse-like glitch noise in the analog signal. never occurs.

Furthermore, even if the outputs of the first and second main DACs change simultaneously due to a large change in input data,
Since the output changes in the same direction, glitch noise is not caused in the analog signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the device of the present invention, FIG. 2 is a data conversion table performed by the digital data conversion circuit 1 in the same embodiment, and FIG. FIG. 4 is a detailed circuit diagram of the digital data conversion circuit 1 in the same embodiment, and FIG. 5 is a diagram showing the bit weight relationship of main output data, second main output data, and sub output data. 6 is a block diagram showing the second embodiment. FIG. 6 is a data conversion table performed by the digital data conversion circuit 1' in the same embodiment. FIG. 7 is a block diagram showing input data, first main output data, and second main output data in the same embodiment. FIG. 8 is a diagram showing the bit weight relationship of output data, and a detailed circuit diagram of the digital data conversion circuit 1' in the same embodiment. 1.1'...Digital data conversion circuit, 2A...
First main DAC12B...second main DAC1
3... Sub output circuit, 4A, 4B... I/V conversion circuit, 5... Analog addition circuit.

Claims (3)

[Claims] (1) Input N-bit input data indicating positive and negative decimal values, and input first main output data of M (M<N) bits indicating positive and negative decimal values and indicating positive and negative decimal values. and a first main D converter capable of D/A converting at least the first main output data into an analog signal.
AC, a second main DAC capable of D/A converting at least the second main output data into an analog signal, and a weight of the LSB of the first main output data and the second main output data.
and analog addition means for adding the respective analog signals so that the weights of the LSBs of the main output data of the main output data of The first main DAC or at least the first and second main DACs are used to output the respective output data in order to perform D/A conversion of the input data; 1. A digital/analog conversion device characterized in that when using the above, the first main output data to be outputted always has a positive or negative maximum value. (2) Input N-bit input data indicating positive and negative decimal values, and input first main output data of M (M<N) bits indicating positive and negative decimal values and indicating positive and negative decimal values. a digital data conversion means for outputting N-bit second main output data and 1-bit sub-output data; and a first main DAC capable of D/A converting at least the first main output data into an analog signal. a second main DAC capable of D/A converting at least the second main output data into an analog signal; a sub output means capable of converting at least the sub output data into an analog signal; and a second main DAC capable of converting at least the second main output data into an analog signal; The weight of the LSB of the data and the second
and an analog addition means for adding the respective analog signals so that the LSB weight of the main output data of the main output data and the bit weight of the sub output data match, outputting each of the output data to perform D/A conversion of the input data using at least the first main DAC or the first and second main DACs in response to the increase in the negative direction; When using the first and second main DACs, the lower (M-1) bits of the second main output data to be output may be in the same or opposite state as the lower (M-1) bits of the input data. A digital/analog conversion device characterized in that the sub output data is output as much as possible, and the first main output data to be output is always set to a positive or negative maximum value. (3) The first and second main DACs each have a resolution of N bits and are integrally formed, and
3. The digital/analog conversion device according to claim 1, wherein said first main DAC performs D/A conversion of said first main output data using its upper M bits.