JPS59160319A - Da converter - Google Patents

Abstract

PURPOSE:To secure the continuity of output analog values without requiring high precision for respective resistances which constitute a ladder circuit by summing up weighted currents, etc., separately according to the values of respective bits for only a part consisting of a specific number of bits and calculating the difference between two addition outputs. CONSTITUTION:A current Is flowing from a constant current circuit 5 is supplied to a resistance ladder 6. The weighted currents flow to respective branch points of the resistance ladder 6 and are supplied to respective switch units S34, S33- S30 of the switch circuit 7. The switch units of the switch circuit 7 are changed over according to the value of respective bits and output currents are supplied to respective inputs of a current difference and voltage converting circuit 8. When each switch unit is placed at a position 1, the current from the resitance ladder is supplied to an input terminal 11, and when placed at a position 0, the current is supplied to an input terminal 12, but when each switch unit is placed at a position G, the current flows to the ground.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DA converter, and more particularly to a DA converter that uses a three-position switch to reduce the required accuracy of a ladder resistor while having a simple configuration.

FIG. 1 shows an example of a conventional ODA converter. The ODA converter shown in the figure includes a constant voltage source 1, a resistance ladder 2 that generates a weighted voltage corresponding to each bit of human-powered digital data, and a switch and a switch S that are turned on and off depending on the input digital data. .

The switch circuit 3 includes a switch circuit 3 including So, . . .

In the ODA converter shown in FIG. 1, a voltage E of a constant voltage source 1 is sequentially divided by a resistor ladder 2, and voltages E, E/E/
2, E/4, E/8, and E/16 are generated. Each switch S of the switch circuit 3 corresponds to the value of each bit of the input digital data. .

S1+...)S4 is turned on or off, and the weighted voltage corresponding to each bit passes through the switch circuit 3 and is input to the high input impedance mixer 4 in accordance with the human-powered data. The high input impedance mixer 4 adds these input voltages and outputs an analog voltage V. This generates an output analog voltage V according to the input digital data. A DA conversion operation is performed to obtain .

As shown in Figure 1, in a DA converter that receives multi-bit digital data as input, a resistor ladder 2 is required to generate an analog voltage or current that matches the weight of each bit. The accuracy of each resistor that makes up the ladder 2 is an important issue. For example, in the 5-bit ODA converter shown in Figure 1, the accuracy of each resistor is (1/'25) x 100 inches, and in an N-bit ODA converter, it is generally 1/2N x 100.
% accuracy is required. If a resistor outside this accuracy is used, as shown in Figure 2, the change in the output analog value will be discontinuous with respect to the change in the input digital data, and the change in the output analog value will be caused by the change in the input digital data. T-
There may be cases where it is no longer able to follow changes in the temperature.

For this reason, in the conventional DA converter having the configuration shown in FIG.
In the case of a converter, there is an inconvenience in that an accuracy such as 1/216 x 100 -0,0015 (a), which is difficult to realize in practice, is required.

Conventionally, input digital data is composed of bits representing significant figures and pits representing an exponent part, and after converting the bits representing the significant figures into an analog quantity, the changed analog quantity is converted into the bits representing the exponent part. A DA controller that shifts the level according to the value has been proposed (see Japanese Patent Laid-Open No. 51-150961).

In such an A converter, it is possible to increase the dynamic range by using a circuit configuration with a relatively small number of bits, but it has the disadvantage that the circuit configuration becomes somewhat complicated.

In view of the problems in the conventional type described above, the purpose of the present invention is to
In the DA converter, a 3-position switch is used to add weighting current, etc. separately according to the value of each pit for a predetermined number of bits less than the total number of bits of input digital data, excluding the most invalid pits. Based on the concept of obtaining two summation outputs and finding the difference between these summation outputs, we ensure continuity of output analog values with a simple configuration and without requiring high accuracy from each resistor that makes up the ladder circuit. There is a particular thing.

According to the present invention, when M is a positive integer, N is an integer greater than M, and E is O or a positive integer, the number of invalid focus points located in the upper part of N bits of input digital data. means for detecting E, an N-stage ladder circuit means having a number of stages corresponding to the number of bits N of the input digital data and generating an output weighted from each stage according to the respective stage; and the ladder circuit means. switch means for obtaining two added outputs by separately adding the outputs of the E+1 bits to M bits from the higher order bits according to the values of each bit of input digital data ``'1'''' and ``o''; The present invention will be described in detail with reference to the drawings below, which is characterized by comprising means for generating an analog signal proportional to the difference between two summation outputs. This was done in consideration of the fact that even if the dynamic range of the input digital data is, for example, 16 bits, the output analog signal only needs to have a resolution of about 10 bits in many cases.In other words, the range of change in the input digital data is 0000000000000000. to 1111111111111111, that is, even if the dynamic range is 16 bits, there is very little need to distinguish between two data values such as 0101101000101.011 and 010110100010 1010.Therefore, the present invention In the embodiment, the configuration is such that, for example, 10 pits of 16 bits of input digital data can be distinguished.

For example, 0], 011.01000...and 0], O], ], 0], 001...
When two pieces of digital data such as are input, the upper 10 bits of both pieces of data are distinguished. For example, if digital data with a low overall level is input, such as 0000101101010... or 0000101], 01011..., for example, the upper 3 bits and g are set as invalid bits and 1. After removing the signal, DA conversion is performed using the subsequent 10 pins. The lower three bits are ignored, for example.

FIG. 13 shows a schematic configuration of a DA converter according to an embodiment of the present invention, and this figure shows the configuration when the input digital data is 5 bits. Same figure ODA
The converter includes a constant current circuit 5, a resistance ladder 6, a switch circuit 7, a current difference/voltage conversion circuit 8, and the like. The switch circuit 7 includes a 3-position switch unit S30+ corresponding to each bit of input digital data.
s3tl...

S34 is provided.

FIG. 4 shows a detailed configuration of the current difference/voltage conversion circuit 8 used in the DA converter shown in FIG. The circuit shown in the figure is composed of operational amplifiers (hereinafter simply referred to as OP amplifiers) 9 and 10, resistors, and the like. In the circuit shown in the figure, the currents at input terminals 11 and 12 are each 1
1 and I2, the output voltage v1 of the OP amplifier 9 is V=-R, bow, (1) Also, the current I6 flowing from the output of the OP amplifier 9 through the resistor R1' is v1/R
1', the current flows from the inverting input terminal of the OP amplifier 10 through the resistor R2. Hato becomes. Also, the output voltage V of the current difference/voltage conversion circuit 8. is vo--R2・I, ...(3), so R4=R,', and 3) into equation (2) and (
Substituting the equation 1) results in = R2 (I, -I, . . . ) (4), and the output voltage V becomes a value proportional to the current difference between the two input currents ■ and I2.

Next, the operation of the DA converter configured as described above will be explained. In the circuit of FIG. 3, a current I8 flowing from a constant current circuit 5 is supplied to a resistor ladder 6, and each branch point of the resistor ladder 6 receives a sequentially weighted current I8/2 #I,
/41-I Is/32 flows, and each switch unit of the switch circuit 7) S34 + 833 +...
l sso. Each switch unit of the switch circuit 7 is switched according to the value of each bit of input digital data, and the output current from each switch unit is supplied to each power of the current difference/voltage conversion circuit 8. When each switch unit is switched to position 1, the current from the resistance ladder is supplied to the input terminal 11 of the current difference/voltage conversion circuit 8, and when it is switched to position 0, the current from the resistance ladder is supplied to the input terminal 12 of the current difference/voltage conversion circuit 8. However, when switched to position G, it flows into ground. Therefore, the current 1 flowing into the input terminal 11 of the current difference/voltage conversion circuit 8 is equal to the sum of the currents flowing from the switch units 1 and 1 of the switch circuit 7, and terminal 12
The current flowing into the switch unit 0 is equal to the sum of the currents flowing out of each switch unit that is switched to the switch unit 0.

In the ODA converter shown in FIG. 3, each switch unit of the switch circuit 7 is not directly controlled according to the value of each bit of the input digital data, but converts the input digital data into another code by a code converter (not shown). The converted value controls the switch circuit 7. That is, when the input digital data or input binary code is, for example, 5 bits, each input binary code is converted into a converted value by a predetermined method, as shown in FIG. In FIG. 5, the input binary code is shown as a two's complement number, and the code pit of the most significant bit (MSB) of this manual binary code is 0 and there is one or more code pits in the code bit. If there are consecutive O's, the consecutive O's including the sign bit are determined to be invalid bits.

In addition, if the sign bit of the input binary code is 1, the following consecutive 1s are invalidated along with the sign bit. It is determined that Assuming that the number of invalid bits obtained in this way is n, the most significant bit, that is, the 1st bit to the (n-1)th bit, is G, and the 1nth bit is the code obtained by inverting the most significant bit. do. In this way, a converted value is created, and each switch unit of the switch and slave circuit 7 shown in FIG. 3 is controlled by the converted value.

That is, the switch unit corresponding to the bit indicated by G among the bits of the conversion value is set to the G position, and the ■ and 0 bits are switched to 1 and 0, respectively. Accordingly, the weighting of the input terminal 11 of the current difference/voltage conversion circuit 8 corresponding to the 1 bit is the sum of the currents, and the weighting of the current I2 corresponding to the 00 bit is the sum of the currents. Therefore, as shown in FIG. 5, when the difference between currents 11 and I2 is determined, this value becomes an analog value corresponding to the input binary data, and DA conversion is performed.

In addition, the values of I and I2 in Fig. 5 are obtained as follows. When the gain of the current difference/voltage conversion circuit 8 is K, vo=K(11-I,) (5). If the input binary code is, for example, 01111, this code is converted to 11111. Therefore, K,,Vo--7,31...(6). Further, when the input binary code is 01110, the converted value is 11110. Furthermore, the input binary data is, for example, 1ooo.

If so, the converted value will be oooooo. Therefore, if I/32 is ignored as a proportionality constant, the output value -I2 shown in FIG. 5 can be obtained.

FIG. 6 shows an embodiment in which the input digital data is 16 bits. The ODA converter in the figure consists of a 16-bit resistor ladder 13, a switch circuit 14 consisting of 16 3-position switch units, a current difference/voltage conversion circuit 8, the same as the one in Figure 3, a constant current source 5, and a cord. It is composed of a converter 15 and the like. Each 3 of the switch circuit 14
The position switch unit is the same as that used in the ODA converter shown in FIG. 3, and is controlled according to the value of each bit of the converted binary data from the code converter 15. That is, if the bits of the corresponding converted binary data are 1.0. G, the branch currents of the resistance ladder 13 are input to the input terminals 11. of the current difference/voltage conversion circuit 8, respectively.
12 and ground. Note that each switch unit of the switch circuit 14 is an electronic switch constituted by an electronic circuit.

In the DA converter shown in FIG. 6, 16-bit input binary data is first converted into converted binary data in the code converter 15. This converted binary data, that is, the converted value, is not 16 bits, but 3 with 10 significant digits.
It is assumed to be a base number (1, Q, G). First, the upper 7 bits of the human binary data are examined to determine invalid bits.

The method for determining invalid bits is the same as in the case of the ODA converter shown in Figure 3.
If SB ) is O, the following consecutive O's are determined to be invalid bits, and if the most significant bit is 1, the following consecutive 1's are determined to be invalid bits. Then, the most significant bit is the first bit, and the nth bit (n is an integer from 1 to 7)
If the bits up to are invalid bits (1) The first to n4th bits are set to G.

(2) The n-th bit is the sign obtained by inverting the most significant bit of the input binary data.

(3) Lower 7 of 16 bits of input binary data
-n bits are G.

A converted value is created by the above operations, and each of the three position switch units of the switch circuit 14 is controlled based on the converted value to perform DA conversion.

FIG. 7 shows the data structure of the converted value created as described above. Take. In this case, the blank space within each type of data takes a value of either 1 or O. By performing such a conversion operation, it becomes possible to make only the upper 6 bits, digits, and lower 6 bits of each switch unit of the switch circuit 14 into a 3-position switch, and the others into 2-position switches. At the same time, the circuit configuration can be simplified since the data conversion operation only needs to be performed on the upper 7 bits and the lower 6 bits. It should be noted that the same conversion operation as explained with reference to FIG. Since it is necessary to check all 16 bits of data, the conversion circuit becomes complicated, and the circuit configuration of the DA converter becomes somewhat complicated.

Also, in the above conversion operation, it is not necessarily necessary to set the lower 7-n bits to G as shown in (3), and these 7-n bits should be the same data as the input binary data. is also possible. The reason is the bottom 7
- Even if the resolution of the converted value is already secured at least 10 bits without using n bits, and the accuracy of each resistor that makes up the resistance ladder is secured only by the equivalent of 10 bits. This is because it was taken into consideration. In this case, it is only necessary to use a 3-position switch for the upper 6 bits of each switch unit of the switch circuit 14, and it is possible to use a 2-position switch for all the others. Since it is only necessary to perform data conversion on the top seven pits, the circuit configuration of the switch circuit, conversion circuit, etc. is further simplified.

In the above-mentioned DA converter, if the input digital data is, for example, 16 bits, only 10 bits out of the 16 bits are outputted as output power 11 and I2 according to each value, taking into account invalid bits. , currents corresponding to other bits flow directly to ground. Therefore, since the actual output operates as if it were a 10-bit ODA converter, the accuracy of each resistor used in the resistance ladder is 0.1 (A) out of 1/210X 10020.098. This is much more advantageous than the 0.0015% accuracy required for conventional 16-bit ODA converters.

Note that although the above description has been made for the case where the output from the resistance ladder is a current, the present invention is not limited to this, and the weighting according to each bit of the resistance ladder can also be applied to a case where the resistance ladder outputs a voltage. can. Further, the resistor ladder can be replaced with another circuit, such as a dividing circuit using a capacitor.

Note that the above example uses one DA converter with 10-bit accuracy and a dynamic lens of 16 pisoto, but this DA converter can be divided into four
Similar characteristics can also be obtained by using four I)A converters each consisting of a bit unit connected in series or in cascade. Furthermore, by constructing a unit with a desired precision, for example 10 bits, using a small number of bits, for example 4 bits, it is possible to easily obtain a DA converter with 10 bits precision and a dynamic range of 4N bits (N is an integer). can.

As described above, according to the present invention, it is possible to ensure continuity of changes in output analog values with a simple circuit configuration and without requiring high accuracy from each element constituting the ladder circuit.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the configuration of a conventional ODA converter, FIG. 2 is a graph for explaining the discontinuity of output analog voltage that occurs in a conventional ODA converter, and FIG. 3 is a diagram showing one implementation of the present invention. A block circuit diagram showing the circuit of the DA converter related to the example, Figure 4 is the ODA shown in Figure 3.
A block circuit diagram showing the detailed configuration of the current difference/voltage conversion circuit used in the converter, Figure 5 is the DA of Figure 3.
Code conversion processing performed in the converter and D
FIG. 6 is a professional circuit diagram showing the configuration of a DA converter according to another embodiment of the present invention, and FIG. 7 is a diagram showing data in the DA converter of FIG. 6. FIG. 3 is a data configuration diagram for explaining a conversion operation. 1: Constant voltage source, 2: Resistance ladder, 3: Switch circuit, 4
: High input impedance mixer, 5: Constant current source, 6: Resistance ladder, 7: Switch circuit, 8: Current difference/voltage conversion circuit, 9.10: Operational amplifier, 11, 12: Input terminal, 1
3: Resistance ladder, 14: Switch circuit, 15: Code converter. Patent Applicant Nippon Gakki Mfg. Co., Ltd. Agent Patent Attorney Tatsuo Ito Agent Patent Attorney Yukitome Ito No. 11 Figure 2') - Power Figure 3 Figure 4

Claims (1)

[Claims] When M is a positive integer, N is an integer larger than M, and E is 0 or a positive integer, a means for detecting the number E of invalid bits located in the upper part of N-bit manual digital data; N-stage ladder circuit means having a number of stages corresponding to the number of bits N of input digital data and generating an output weighted from each stage according to the respective stage; an N-stage ladder circuit means from the E+1th bit to M from the higher order of the ladder circuit means; switch means for obtaining two summation outputs by separately adding bit outputs according to the values II, IM and "o" of each bit of input digital data; and an analog switch proportional to the difference between these two summation outputs. D, characterized in that it comprises means for generating a signal.
A converter.