JPH03178223A - D/a converter circuit - Google Patents
D/a converter circuitInfo
- Publication number
- JPH03178223A JPH03178223A JP31723989A JP31723989A JPH03178223A JP H03178223 A JPH03178223 A JP H03178223A JP 31723989 A JP31723989 A JP 31723989A JP 31723989 A JP31723989 A JP 31723989A JP H03178223 A JPH03178223 A JP H03178223A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- conversion circuit
- digital
- register
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 35
- 238000005070 sampling Methods 0.000 claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/04—Differential modulation with several bits, e.g. differential pulse code modulation [DPCM]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
- H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing (AREA)
- Analogue/Digital Conversion (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
この発明は、コンパクトディスクプレーヤ(CDプレー
ヤ)などの各種デジタルオーディオ機器におけるデジタ
ル/アナログ変換回路(以下D/A変換回路ともいう。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a digital/analog conversion circuit (hereinafter also referred to as a D/A conversion circuit) in various digital audio equipment such as a compact disc player (CD player).
)に関する。) regarding.
〈従来の技術〉
一般に、デジタルオーディオ機器のCDプレーヤ社おけ
るD/A変換回路は、デジタル信号処理回路から入力さ
れてくる所定ビット数例えば16ビツトのデジタル信号
をアナログ信号に変換してローパスフィルタに出力する
よう構成されている〈発明が解決しようとする課題〉
しかし、従来のラダー抵抗型のD/A変換回路において
は、抵抗の誤差がD/A変換回路の精度を大きく左右す
るため、各抵抗をレーザ・トリミングにより調整された
精度に設定している。しかし、この誤差はMSB(th
e Mo5t Stgnificant Bit
)で最大となり、MSBのビット反転時にゼロクロス歪
が発生し、微小レベルの信号を忠実に再現することが難
しく、この忠実度を高めるために、例えば、D / A
変j&回路出力に誤差を打ち消すような電流または電
圧を加えて誤差の補償をしていた。<Prior Art> Generally, a D/A conversion circuit in a CD player company of digital audio equipment converts a digital signal of a predetermined number of bits, for example 16 bits, input from a digital signal processing circuit into an analog signal and passes it through a low-pass filter. <Problem to be Solved by the Invention> However, in the conventional ladder resistance type D/A conversion circuit, the error in the resistance greatly affects the accuracy of the D/A conversion circuit. The resistors are set to a controlled precision by laser trimming. However, this error is MSB (th
e Mo5t Stgnificant Bit
), and zero-crossing distortion occurs when the MSB bit is inverted, making it difficult to faithfully reproduce minute-level signals.
The error was compensated for by adding a current or voltage to the circuit output that canceled out the error.
この発明は、上記問題点にかんがみ、ゼロクロス歪自体
の発生を抑制し、上記のような誤差補償処理を要しない
D/A変換回路を提供することを主な課題とする。In view of the above-mentioned problems, the main object of the present invention is to provide a D/A conversion circuit that suppresses the occurrence of zero-cross distortion itself and does not require error compensation processing as described above.
く課題を解決するための手段〉
この課題を解決するため、この発明のデジタル/アナロ
グ変換回路は、
ラダー抵抗型のデジタル/アナログ変換回路部と、
デジタル信号処理回路のデジタル信号が示す今回サンプ
リング値と前回サンプリング値との差分値を示すデジタ
ル信号を生威し前記デジタル/アナログ変換回路部に出
力する・差分値生成回路と、前記デジタル/アナログ変
換回路部からのアナログ電流信号をアナログ電圧信号に
変換してローパスフィルタに出力するサンプルホールド
キャパシタとからなることを特徴とする。Means for Solving the Problem> In order to solve this problem, the digital/analog conversion circuit of the present invention includes a ladder resistance type digital/analog conversion circuit section and a current sampling value indicated by the digital signal of the digital signal processing circuit. A digital signal indicating the difference between the value and the previous sampling value is generated and outputted to the digital/analog conversion circuit section.The analog current signal from the difference value generation circuit and the digital/analog conversion circuit section is converted into an analog voltage signal. It is characterized by comprising a sample and hold capacitor that converts the data and outputs the converted signal to a low-pass filter.
〈実施例〉 以下この発明の実施例を図面にもとづいて説明する。<Example> Embodiments of the present invention will be described below based on the drawings.
第1図はデジタル/アナログ変換回路の一実施例構成、
第2図はこのデジタル/アナログ変換回路が適用された
CDプレーヤのブロック構成を示している。Figure 1 shows the configuration of one embodiment of the digital/analog conversion circuit.
FIG. 2 shows a block configuration of a CD player to which this digital/analog conversion circuit is applied.
D/A変換回路1は、D/A変換回路部2と、D/A変
換回路部2の前段にもうけた差分値生成回路3と、D/
A変換回路部2の後段に配されたサンプルホールドキャ
パシタ4とからなる。The D/A conversion circuit 1 includes a D/A conversion circuit section 2, a difference value generation circuit 3 provided before the D/A conversion circuit section 2, and a D/A conversion circuit section 2.
It consists of a sample and hold capacitor 4 arranged after the A conversion circuit section 2.
差分値生成回路3は、デジタル信号処理回路5からMS
B FST (ファースト)でシリアルに入力されて
くるデジタル信号が示す今回サンプリング値(例えば1
6ビツトデータ)と、前回サンプリング値(同16ビツ
トデータ)との差分値を示すデジタル信号を生威し、こ
のデジタル信号をMSB FSTでシリアルにD/A
変換回路部2に出力する。差分値生成回路3は具体的に
は、デジタル信号処理回路5の出力側とD/A変換回路
部2の入力端との間に、5IPO(シリアルイン・パラ
レルアウト)レジスタ31.PISO(パラレルイン・
シリアルアウト)レジスタ32、シフトレジスタ33、
減算器34、他の5IPOレジスタ35、他のprso
レジスタ36を直列的に接続した構成である。ここで、
S!POレジスタ31、PISOレジスタ32はMSB
FSTからLSB FSTに変換する回路、シフ
トレジスタ33、減算器34は現在のデータと1つ前の
データを減算する回路、5IPOレジスタ35、PIS
Oレジスタ36は減算結果をLSB FSTからMS
B FSTに変換する回路である。The difference value generation circuit 3 receives the MS from the digital signal processing circuit 5.
B The current sampling value (for example, 1
6-bit data) and the previous sampling value (16-bit data), and serially D/A this digital signal using MSB FST.
It is output to the conversion circuit section 2. Specifically, the difference value generation circuit 3 includes 5 IPO (serial in/parallel out) registers 31 . PISO (parallel in)
serial out) register 32, shift register 33,
subtractor 34, other 5 IPO registers 35, other prso
This configuration has registers 36 connected in series. here,
S! PO register 31 and PISO register 32 are MSB
A circuit that converts FST to LSB FST, a shift register 33, a subtracter 34 that subtracts the current data and the previous data, 5IPO register 35, PIS
O register 36 subtracts the result from LSB FST to MS
This is a circuit that converts to B FST.
D/A変換回路部2は公知のラダー抵抗型のものであり
、差分値生成回路3からMSB FSTで人力されて
くる差分値デジタル信号を正負のアナログ電流信号に変
換してサンプルホールドキャパシタ4に出力する。The D/A conversion circuit section 2 is of a well-known ladder resistance type, and converts the difference value digital signal manually inputted from the difference value generation circuit 3 by MSB FST into a positive/negative analog current signal and sends it to the sample hold capacitor 4. Output.
一サンプルホールドキャパシタ4はD/A変換回路部2
から入力されてくる正負のアナログ電流信号により充放
電しアナログ電圧信号をローパスフィルタ6に出力する
。ここで、アナログ電流信号をΔi、サンプルホールド
キャパシタ4の容量をC1同充電電圧をVc (t)と
すると、充電電圧Vc (t)は、
Vc(t)=Δ i −t/C+ Vc(Vc:
1クロツク前の充電電圧)
で与えられ、る。この式から明らかなように、充電を圧
Vc(t)は時間tに対してリニアに変化することがわ
かる(第3図参照)。One sample hold capacitor 4 is the D/A conversion circuit section 2
It is charged and discharged by the positive and negative analog current signals inputted from the terminal and outputs an analog voltage signal to the low-pass filter 6. Here, if the analog current signal is Δi, the capacitance of the sample-and-hold capacitor 4 is C1, and the charging voltage is Vc (t), then the charging voltage Vc (t) is Vc (t) = Δ i -t/C+ Vc (Vc :
The charging voltage one clock ago) is given by . As is clear from this equation, it can be seen that the charging pressure Vc(t) changes linearly with respect to time t (see FIG. 3).
なお第2図において、符号7は光学デツキメカニズム、
8はデジタル信号回路、9はアナログ信号回路、10は
システム制御部を表わしている。In Fig. 2, the reference numeral 7 indicates an optical deck mechanism;
8 represents a digital signal circuit, 9 represents an analog signal circuit, and 10 represents a system control section.
〈発明の作用・効果〉
以上説明したように、この発明のデジタル/アナログ変
換回路は、ラダー抵抗型のデジタル/アナログ変換回路
部と、デジタル信号処理回路のデジタル信号が示す今回
サンプリング値と前回サンプリング値との差分値を示す
デジタル信号を生成し前記デジタル/アナログ変換回路
部に出力する差分値生成回路と、前記デジタル/アナロ
グ変換回路部からのアナログ電流信号をアナログ電圧信
号に変換してローパスフィルタに出力するサンプルホー
ルドキャパシタとからなることを特徴とする。<Operations and Effects of the Invention> As explained above, the digital/analog conversion circuit of the present invention has a ladder resistance type digital/analog conversion circuit section and a current sampling value and a previous sampling value indicated by the digital signal of the digital signal processing circuit. a difference value generation circuit that generates a digital signal indicating a difference value and outputs it to the digital/analog conversion circuit section; and a low-pass filter that converts the analog current signal from the digital/analog conversion circuit section into an analog voltage signal. It is characterized by consisting of a sample and hold capacitor that outputs to.
このため、差分値デジタル信号の所要ビット数が少ない
ことからD/A変換回路部におけるゼロクロス歪の絶対
値が小さく、微小レベル信号を忠実に再現することが可
能になる。Therefore, since the required number of bits of the differential value digital signal is small, the absolute value of zero-cross distortion in the D/A conversion circuit section is small, making it possible to faithfully reproduce minute level signals.
またアナログ電圧信号は階段状でなくリニアに変化する
ことから、後段のローパスフィルタを必要に応じて省略
することも可能になるなどの効果を奏する。Furthermore, since the analog voltage signal changes linearly rather than stepwise, it is possible to omit a low-pass filter at the subsequent stage as necessary.
なお、本発明は上記実施例に限定されるものではなく、
入力形式がパラレルなものや、LSBFSTのものでも
十分適用できる。さらに本発明は2の補数、オフセット
バイナリ−のいずれのデジタル信号形式に対しても適用
できる。Note that the present invention is not limited to the above embodiments,
It can be applied even if the input format is parallel or LSBFST. Further, the present invention can be applied to both two's complement and offset binary digital signal formats.
第1図はこの発明のデジタル/アナログ変換回路の一実
施例構成図、
第2図は上記デジタル/アナログ変換回路が適用された
CDプレーヤのブロック構成図、第3図は上記デジタル
/アナログ変換回路の出力波形説明図である。
1・・・デジタル/アナログ変換回路、2・・・デジタ
ル/アナログ変換回路部、3・・・差分値生成回路、
4・・・サンプルホールドキャパシタ、5・・・デジタ
ル信号処理回路、
6・・・ローパスフィルタ。
特 許 出 願 人
新白砂電機株式会社
Vc
第
図Figure 1 is a block diagram of an embodiment of the digital/analog conversion circuit of the present invention, Figure 2 is a block diagram of a CD player to which the digital/analog conversion circuit is applied, and Figure 3 is the digital/analog conversion circuit described above. FIG. 2 is an explanatory diagram of an output waveform. DESCRIPTION OF SYMBOLS 1... Digital/analog conversion circuit, 2... Digital/analog conversion circuit section, 3... Difference value generation circuit, 4... Sample hold capacitor, 5... Digital signal processing circuit, 6...・Low pass filter. Patent application Hitoshi Shirasago Electric Co., Ltd. Vc Figure
Claims (1)
リング値と前回サンプリング値との差分値を示すデジタ
ル信号を生成し前記デジタル/アナログ変換回路部に出
力する差分値生成回路と、前記デジタル/アナログ変換
回路部からのアナログ電流信号をアナログ電圧信号に変
換してローパスフィルタに出力するサンプルホールドキ
ャパシタとからなることを特徴とするデジタルオーディ
オ機器のデジタル/アナログ変換回路。[Claims] A ladder resistance type digital/analog conversion circuit unit, which generates a digital signal indicating a difference value between the current sampling value and the previous sampling value indicated by the digital signal of the digital signal processing circuit; A digital audio device comprising: a difference value generation circuit that outputs to a circuit section; and a sample-hold capacitor that converts an analog current signal from the digital/analog conversion circuit section into an analog voltage signal and outputs it to a low-pass filter. digital/analog conversion circuit.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31723989A JPH03178223A (en) | 1989-12-06 | 1989-12-06 | D/a converter circuit |
DE19904038641 DE4038641C2 (en) | 1989-12-06 | 1990-12-04 | Digital / analog converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31723989A JPH03178223A (en) | 1989-12-06 | 1989-12-06 | D/a converter circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03178223A true JPH03178223A (en) | 1991-08-02 |
Family
ID=18086035
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31723989A Pending JPH03178223A (en) | 1989-12-06 | 1989-12-06 | D/a converter circuit |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH03178223A (en) |
DE (1) | DE4038641C2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5268688A (en) * | 1992-05-13 | 1993-12-07 | Hughes Aircraft Company | Linear signal reconstruction system and method |
DE19931132A1 (en) * | 1999-03-25 | 2000-09-28 | Univ Ilmenau Tech | Non-linear transmission function provision method using operational amplifiers has personal computer software used for function modelling and testing and provision of assembler codes for digital signal processor |
US9055687B2 (en) * | 2010-08-20 | 2015-06-09 | Rockwell Automation Technologies, Inc. | Input/output circuits and devices having physically corresponding status indicators |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4567463A (en) * | 1982-02-23 | 1986-01-28 | Burr-Brown Corporation | Circuit for improving the performance of digital to analog converters |
-
1989
- 1989-12-06 JP JP31723989A patent/JPH03178223A/en active Pending
-
1990
- 1990-12-04 DE DE19904038641 patent/DE4038641C2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE4038641A1 (en) | 1991-06-13 |
DE4038641C2 (en) | 1994-04-07 |
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