JP2004112014A - Da converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the size and cost of a DA converter applied to a digital audio apparatus. <P>SOLUTION: The DA converter 1 comprises an SDF conversion circuit 2 for converting the data format of a digital audio signal inputted in a serial data format, a one bit DA conversion circuit 3 generating a first analog signal and a second analog signal delayed by one sampling time behind the analog signal by the DA conversion of original audio data for the L/R channels of audio data outputted from the SDF conversion circuit 2, and an ASP circuit 4 for generating an analog signal connecting signal levels between sampling points from the first and second analog signals and outputting it as an analog audio signal. Since a one-bit DA conversion circuit can e used, reduction in size and cost is attained. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a D / A converter (digital / analog converter) for converting a digital signal into an analog signal, and in particular, a D / A converter for outputting, as a D / A conversion signal, an analog signal in which signal levels at sampling points of a digital signal are smoothly connected. About.
[0002]
[Prior art]
2. Description of the Related Art In digital audio equipment, for example, a ladder resistance type DA converter and an integrating type DA converter are known and used as AD converters for converting a digitized sound signal into an analog signal. These known D / A converters simply convert each sampled value (digital value) of a digital signal that is discretely sampled and digitized into an analog value, and the output signal waveform is a step-like waveform. And contains unnecessary high-frequency components not included in the original signal. For this reason, an analog low-pass filter is generally provided downstream of the DA converter to remove unnecessary high-frequency components and obtain a smooth analog signal.
[0003]
However, this DA conversion method has a problem that a delay occurs due to a phase characteristic of the analog low-pass filter and a waveform distortion such as an overshoot occurs, thereby deteriorating the sound quality of the reproduced sound.
[0004]
Therefore, as shown in Japanese Patent No. 3134403, a staircase-shaped first analog signal obtained by DA conversion in real time and a staircase-shaped second analog signal delayed by one sampling time with respect to the first analog signal are conventionally disclosed. An analog signal is generated by generating an analog signal and adding to the second analog signal while integrating the level difference between the first and second analog signals during each sampling period, thereby smoothly connecting each sampling value of the digital signal. Is output as a DA conversion signal.
[0005]
FIG. 6 is a block diagram showing the configuration of a conventional new type DA converter.
[0006]
The DA converter 100 includes a digital filter 101, two delay circuits 102 and 103, four multi-bit DA converters (hereinafter, referred to as multi-bit DAC), and two analog signal processing circuits (hereinafter, referred to as ASP circuits). .) 108 and 109 are provided.
[0007]
To the digital filter 101, an audio signal digitized from a digital sound source such as a CD (Compact Disc) is transmitted in, for example, an I2S mode and input. As shown in FIG. 7, the I2S mode audio signal identifies audio data DATA (hereinafter, referred to as DATA signal) obtained by mixing L channel audio data and R channel audio data, and word data of the DATA signal. Clock signal LRCK (hereinafter, referred to as LRCK signal) and a bit clock BCLK (hereinafter, referred to as BCLK signal) for identifying bit data of the audio data DATA.
[0008]
Note that the I2S mode is an example, and generally, as shown in FIG. 8, a Right-Justified (right-justified) mode (FIG. 8A) and a Left-Justified (left-justified) mode (FIG. 8). (B)), various modes such as a Left-Justified DSP mode ((c) in the figure) and a 32 × Fs Packed mode ((d) in the figure) exist and are used. In these modes, similarly to the I2S mode, L-channel audio data and R-channel audio data are mixed.
[0009]
The DATA signal pairs the data DLi of the L channel (corresponding to one word data with n bit data) and the data DRi of the R channel (corresponding to one word data with n bit data) at the same sampling position i. Are serial data (DL1 / DR1, DL2 / DR2,... DLm / DRm) arranged in sampling order. The LRCK signal is a clock having one cycle of one word data DLi / DRi of the DATA signal. In FIG. 7, the L level period of the LRCK signal is synchronized with the L channel word data DLi of the DATA signal, and the LRCK signal is high. The level period is synchronized with the R-channel word data DRi of the DATA signal. The BCLK signal is a clock synchronized with the bit data of the DATA signal.
[0010]
The digital filter 101 is composed of an oversampling digital filter, samples input I2S mode audio data at a speed several times (for example, 8 times) the actual sampling frequency (for example, 44.1 kHz), and performs L channel audio. The data is separated from the R channel audio data, the L channel audio data L (T) (word data string signals DL1, DL2,... DLm) is output from the L terminal, and the R channel audio data R is output from the R terminal. (T) (word data string signals DR1, DR2,... DRm) are output.
[0011]
The delay circuits 102 and 103 delay input audio data by one sampling time. The L-channel audio data L (T) output from the digital filter 101 is input to the multi-bit DAC 104 and is delayed by one sampling time in the delay circuit 102. The delayed audio data L (-T) is The data is input to the multi-bit DAC 105. The R-channel audio data R (T) output from the digital filter 101 is input to the multi-bit DAC 106 and is also delayed by one sampling time in the delay circuit 103. The delayed audio data R (-T) Is input to the multi-bit DAC 107.
[0012]
The multi-bit DACs 104 to 107 convert audio data into analog signals in word data units. The multi-bit DACs 104 to 107 simultaneously convert each bit (each digit) of the n-bit word data into an analog value and add the analog values to generate an analog signal.
[0013]
The multi-bit DAC 104 converts the L-channel audio data L (T) into an analog signal L (t), and the multi-bit DAC 105 converts the L-channel audio data L (T) delayed by one sampling time from the audio data L (T). −T) is converted to an analog signal L (−t), and is input to the L-channel ASP circuit 108. The multi-bit DAC 106 converts the R-channel audio data R (T) into an analog signal R (t), and the multi-bit DAC 107 outputs the R-channel audio data R (T) delayed by one sampling time. R (−T) is converted into an analog signal R (−t), and is input to the ASP circuit 109 for the R channel.
[0014]
The ASP circuits 108 and 109 are provided with a first analog signal S (t) having a staircase waveform input and a second analog signal having a staircase waveform delayed by one sampling time from the analog signal S (t). By converting the level difference (difference voltage) from the signal S (−t) into a current, charging the current to a capacitor, and adding the charged voltage to the signal level of the second analog signal S (−t). As shown in FIG. 9, an analog audio signal S (t) ′ in which respective sampling levels are smoothly connected is generated and output as a DA conversion signal.
[0015]
The ASP circuits 108 and 109 are constituted by, for example, the circuit shown in FIG. In the ASP circuit shown in the figure, a negative terminal of an operational amplifier OP1 is connected to an input terminal IN1 of a first analog signal S (t) via a resistor r1, and a positive terminal of the operational amplifier OP1 is a series circuit of a capacitor C1 and a resistor r3. Is connected to the input terminal IN2 of the second analog signal S (−t) via The output terminal of the operational amplifier OP1 is connected to a negative terminal via a resistor r2, and is connected to an output terminal OUT of the ASP circuit via a resistor r6. A resistor r4 is connected between the + terminal of the operational amplifier OP1 and the ground, and a capacitor C2 is connected between the output terminal OUT and the ground. Further, a series circuit of an operational amplifier OP2 and a resistor r5 is connected between a connection point of the resistor r3 and the capacitor C1 and the output terminal OUT.
[0016]
The operational amplifier OP1 operates as a negative feedback differential amplifier, and the operational amplifier OP2 operates as a buffer amplifier when a part of the output signal of the operational amplifier OP1 is fed back to the + terminal of the operational amplifier OP1 via the resistor R5. The capacitor C1 cuts the input to the + terminal of the operational amplifier OP1 in a steady state when the first analog signal S (t) and the second analog signal S (-t) are substantially the same, and suppresses the generation of noise. Things. The resistor r6 and the capacitor C2 constitute an integrating circuit SC, and generate a signal obtained by integrating the output of the operational amplifier OP1 (the difference between the first analog signal S (t) and the second analog signal S (-t)). It is.
[0017]
In the above configuration, the first and second terminals of the operational amplifier OP1 are respectively provided with the first analog signal S (t) at each sampling point and the second analog signal S (t) delayed by one sampling time from the analog signal S (t). (−t) is input, and a voltage having a difference value from the reference voltage of the first analog signal S (t) using the second analog signal S (−t) as a reference voltage is converted from the operational amplifier OP1 into a current. Output. This current charges the capacitor C2 of the integration circuit SC with the time constant C2 · r6, and the charged voltage of the capacitor C2 is supplied to the second analog signal S (−) which is input next via the buffer amplifier and the resistor r5. t).
[0018]
Since the change in the charging voltage of the capacitor C2 indicates a voltage vector connecting the level difference between the previous sampling point and the subsequent sampling point in the sampling period, as shown in FIG. 9, each sampling point t1, t2,. When the first analog signal S (t) and the second analog signal S (−t) are input at ti, the output level of the ASP circuit at the sampling point ti becomes the first analog signal S (ti) or the second analog signal S (ti). In the period ti <t <ti + 1, a voltage vector connecting the level difference between the output level of the sampling point ti and the output level of the sampling point ti + 1 is determined by the charging voltage of the capacitor C2. Generated. Therefore, the ASP circuit outputs an analog signal S (t) ′ connecting the voltage levels at each sampling point.
[0019]
The ASP circuit 108 smoothly connects the respective sampling values of the L-channel digital signal from the L-channel first analog signal L (t) and the second analog signal L (-t) to the analog signal L (t). 'Is generated and output as a DA conversion signal. Further, the ASP circuit 109 smoothly connects the sampling values of the R channel digital signal from the R channel first analog signal R (t) and the second analog signal R (−t) to the analog signal R ( t) ′ is generated and output as a DA conversion signal.
[0020]
[Patent Document 1]
Japanese Patent No. 3134403
[0021]
[Problems to be solved by the invention]
By the way, in the DA converter 100 applied to the conventional digital audio equipment, since the digital audio signal is input in, for example, the I2S mode, the L channel analog signals L (t) and L (−t) are converted from the I2S mode DATA signal. ) And R-channel analog signals R (t) and R (−t) are relatively easily obtained by a digital filter integrated circuit, and multi-bit DACs 104 to 107 are used.
[0022]
That is, when the multi-bit DACs 104 to 107 are used, for example, in the case of the I2S mode, audio data L (T) composed of an L-channel word data string DLi and audio data composed of an R-channel word data string DRi are obtained from the DATA signal. R (T) is separated from the original audio data L (T), L (T), R (T) by simply delaying the audio data L (T), R (T) of both channels by one sampling time. Since R (T) and audio data L (-T) and R (-T) obtained by delaying this by one sampling time are obtained, these four audio data L (T), R (T), L ( -T) and R (-T) are DA-converted by the multi-bit DACs 104 to 107, respectively. One of the analog signal L (t), R (t), L (-t), it is possible to easily obtain R (-t).
[0023]
However, a D / A converter using a conventional multi-bit DAC, for example, in the case of two channels, receives four audio data L (T), R (T), L (-T) and R (-T) respectively. Since it is necessary to provide a multi-bit DAC, the number of DA converters is increased, and the unit price of the multi-bit DAC is high, which is disadvantageous in terms of circuit configuration and cost. In particular, when the number of channels of an audio device increases, a multi-bit DAC that is twice as many as the number of channels is required, resulting in an increase in circuit size and an increase in cost.
[0024]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a DA converter that is small in size and low in cost by using a one-bit DAC that is cheaper than a multi-bit DAC and easily available. And
[0025]
[Means for Solving the Problems]
According to the present invention, there are provided: data obtained by serially arranging L-channel audio data and R-channel audio data alternately in word units; a word clock for identifying word data of the data; and bit data of the data. And generating a delay data obtained by delaying the input data by one sampling time for at least one channel in a data format of a digital audio signal including a bit clock for identifying the input data and the delay data. And audio data converting means for converting the audio data into a format of audio data which is alternately and serially arranged in word units, and the audio data converted by the audio data converting means using the word clock as input data and delay data. Separated into The input data is serially D / A converted bit by bit using the bit clock to generate a first analog signal, and the delayed data is serially DA converted bit by bit using the bit clock to generate a second analog signal. A one-bit D / A conversion means for generating an analog signal of the first type and an analog signal obtained by connecting signal levels between sampling points using the first analog signal and the second analog signal generated by the one-bit D / A conversion means An analog signal processing means for generating and outputting the analog audio signal as an analog audio signal (claim 1).
[0026]
The audio data conversion means calculates an AND of the data and the word clock to extract input data of one channel, and an AND circuit that extracts input data of the one channel from the input data extracted by the AND circuit. And a delay circuit for generating the delay data by delaying the delay data by a half of one cycle of the word clock, and the one of the input data output from the AND circuit and the delay data output from the delay circuit. The output to the bit DA conversion means may be constituted by a switch circuit that alternately switches in word units based on the word clock. Further, the delay circuit may be constituted by a shift register.
[0027]
According to the above configuration, the input digital audio signal data is separated into the L-channel audio data and the R-channel audio data by the audio data conversion means, and the separated input data is sampled for at least one channel by one sampling. Delay data delayed by a time is generated, and is converted into audio data in which input data and delay data are alternately serially arranged in word units.
[0028]
The audio data is separated into input data and delay data by a one-bit DA conversion means using a word clock, and the input data and the delay data are serially DA-converted bit by bit using a bit clock to obtain a first data. And a second analog signal delayed by one sampling time from the first analog signal.
[0029]
Then, the analog signal processing means uses the first analog signal and the second analog signal to generate and output an analog audio signal connecting the signal levels between the sampling points.
[0030]
As described above, the audio data converting means and the one-bit DA converting means generate the first analog signal and the second analog signal delayed by one sampling time from the first analog signal. The circuit configuration is simpler than that of a DA converter using a bit DA converter, and the cost can be reduced.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0032]
FIG. 1 is a block diagram of a DA converter according to the present invention.
[0033]
The DA converter 1 includes a serial data format conversion circuit 2 (hereinafter, abbreviated as SDF conversion circuit 2), a one-bit DA conversion circuit 3, and an analog signal processing (ASP) circuit 4. The one-bit DA conversion circuit 3 includes a one-bit DAC 31L that converts an L-channel digital signal into an analog signal and a one-bit DAC 31R that converts an R-channel digital signal into an analog signal. The ASP circuit 4 also processes the two types of analog signals L (t) and L (-t) of the L channel, and converts the analog signal obtained by smoothly connecting each sampling value of the digital signal to a DA conversion signal (analog audio signal). An ASP circuit 41L that outputs the analog signal and two types of analog signals R (t) and R (−t) of the R channel are processed, and the analog signal obtained by smoothly connecting the sampling values of the digital signal is converted into a DA conversion signal (analog audio signal). And an ASP circuit 41R that outputs the signal as a signal.
[0034]
The SDF conversion circuit 2 separates L-channel audio data L (T) and R-channel audio data R (T) from a DATA signal of a digital audio signal (see FIG. 7) input in a serial data format, and Is converted into data in a format that can be DA converted by the one-bit DAC 3.
[0035]
The SDF conversion circuit 2 separates the L channel word data DLi (i = 1, 2,... M) and the R channel word data DRi (i = 1, 2,... M) of the DATA signal by the LRCK signal. For both channels, word data DLi ′ and DRi ′ are generated for each word data which are delayed by 時間 of one cycle T of the LRCK signal (corresponding to the sampling cycle T of the digital signal), and this word data DLi ′ is The word data DRi ′ is inserted between the word data DLi and the word data DLi + 1 and sequentially output, and the word data DRi ′ is inserted between the word data DRi and the word data DRi + 1 and sequentially output.
[0036]
That is, the SDF conversion circuit 2 generates word data DLi ′ delayed by T / 2 for each word data DLi every time it extracts the word data DL1, DL2,... DLm of the L channel, and converts this word data DLi ′. It is output after the word data DLi. Since the contents of the word data DLi ′ are the same as the word data DLi, the data composed of the word data strings DL1 ′, DL2 ′,... DLm ′ is different from the data composed of the original word data strings DL1, DL2,. The data has a phase delayed by T / 2. Therefore, the L channel output terminal of the SDF conversion circuit 2 outputs a DATA signal composed of word data strings DL1, DL1, DL2, DL2,... DLi, DLi, DLi + 1, DLi + 1,. Similarly, a DATA signal composed of word data strings DR1, DR1, DR2, DR2,... DRi, DRi, DRi + 1, DRi + 1,.
[0037]
FIG. 2 is a block diagram showing a specific circuit configuration of the SDF conversion circuit 2 in the I2S mode.
[0038]
The SDF conversion circuit 2 includes two AND circuits 201 and 202, two inversion circuits 203 and 204, three delay circuits 205, 206 and 207, two switch circuits 208 and 209, and three latch circuits 210 , 211, 212.
[0039]
These circuits are connected as follows. That is, one input terminal of the AND circuit 201 and one input terminal of the AND circuit 202 are connected to the DATA input terminal IN1 of the I2S mode, and the other input terminal of the AND circuit 201 is connected to the I2S mode via the inverting circuit 203. And the other input terminal of the AND circuit 202 is directly connected to the I2S mode LRCK input terminal IN2.
[0040]
The output terminal of the AND circuit 201 is connected to one contact a of the switch circuit 208, and the delay circuit 205 is connected between the output terminal of the AND circuit 201 and the other contact b of the switch circuit 208. The output terminal of the AND circuit 202 is connected to one contact e of the switch circuit 209, and the delay circuit 206 is connected between the output terminal of the AND circuit 202 and the other contact d of the switch circuit 209.
[0041]
The delay circuit 205 generates word data DLi ′ obtained by delaying the word data DLi by T / 2, and the delay circuit 206 generates word data DRi ′ obtained by delaying the word data DRi by T / 2. Each of the delay circuits 205 and 206 is specifically configured by an n / 2-bit shift register. For example, when the word data DLi is 64-bit data, the delay circuits 205 and 206 are constituted by 32-bit shift registers. The I2S mode BCLK signal is input to each of the delay circuits 205 and 206, and the delay circuit 205 shifts each bit data constituting the word data DLi using the BCLK signal, thereby delaying the word data DLi 'by T / 2. The delay circuit 206 generates word data DRi ′ delayed by T / 2 by shifting each bit data forming the word data DRi using the BCLK signal.
[0042]
The delay circuit 207 is connected between the common terminal c of the switch circuit 208 and the latch circuit 210, and the output terminal of the latch circuit 210 is connected to the L-channel DATA output terminal OUT1. The delay circuit 207 adjusts the phase of the L channel word data to the phase of the R channel word data by delaying the L channel word data by T / 2. Like the delay circuits 205 and 206, the delay circuit 207 is configured by an n / 2-bit shift register. For example, when the word data DLi is 64-bit data, the delay circuit 207 is configured by a 32-bit shift register. The BCLK signal is also input to the delay circuit 207. The delay circuit 207 delays the L-channel word data DLi and DLi 'by T / 2 by shifting each bit data of the word data using the BCLK signal.
[0043]
The input terminal of the latch circuit 211 is connected to the common terminal f of the switch circuit 209, and the output terminal of the latch circuit 211 is connected to the DATA output terminal OUT2 of the R channel. An LRCK signal is input to each of the switch circuits 208 and 209, and the switch circuits 208 and 209 perform a contact switching process using the LRCK signal.
[0044]
The latch circuit 212 is connected between the input terminal IN2 of the LRCK signal and the output terminal OUT2, and the inversion circuit 204 is connected between the input terminal IN3 of the BCLK signal and the output terminal OUT4. The latch circuits 210, 211, and 212 synchronize the L-channel data output from the switch circuit 208 via the delay circuit 207, the R-channel data output from the switch circuit 209, and the LRCK signal to output the L-channel signals, respectively. The terminal OUT1, the R channel output terminal OUT2, and the LRCK terminal OUT3 output the signal. A BCLK signal is input to each of the latch circuits 210, 211, 212. The latch circuits 210, 211 perform a latch process of each bit constituting data using the BCLK signal, and the latch circuit 212 uses the BCLK signal to perform an LRCK signal. Is performed.
[0045]
The inversion circuit 204 inverts the BCLK signal and outputs the inverted signal from the BCLK output terminal OUT4, so that the L-channel data, the R-channel data, and the L-channel data output from the L-channel output terminal OUT1, the R-channel output terminal OUT2, and the LRCK output terminal OUT3, respectively. This is for adjusting the timing of the BCLK signal with respect to the LRCK signal.
[0046]
Next, the operation of the SDF conversion circuit 2 will be described with reference to FIGS.
[0047]
FIGS. 3 and 4 are diagrams showing the relationship between the input / output data of the switch circuits 208 and 209 and the data output from the output terminals in the signal processing based on the LRCK signal in the SDF conversion circuit 2. FIG. FIG. 3 relates to the data of the L channel, and FIG. 4 relates to the data of the R channel.
[0048]
3 and 4, “No” is a serial number assigned to each cycle of the LRCK signal. “LRCK” indicates an LRCK signal, “Low” indicates an L level state, and “High” indicates an H level state. “DATA” indicates a DATA signal, and DL1, DL2,... DLi, DR1, DR2,. Also, “La”, “Lb”, and “Lc” in FIG. 3 indicate L-channel signals at the contact points a, b, and the common terminal c of the switch circuit 208, respectively, and “Lout” indicates a signal from the L-channel output terminal OUT1. The output L channel signal is shown. “Re”, “Rd”, and “Rf” in FIG. 4 indicate R channel signals at the contact e, the contact d, and the common terminal f of the switch circuit 209, respectively, and “Rout” is output from the R channel output terminal OUT2. 3 shows an R channel signal.
[0049]
When the LRCK signal is at the L level, the AND circuit 201 outputs the DATA signal input in the I2S mode from the DATA input terminal IN1. When the LRCK signal is at the H level, the AND circuit 202 outputs the DATA signal from the DATA input terminal in the I2S mode. Since the input DATA signal is output, the L-channel word data DLi (i = 1, 2,... M) is output from the AND circuit 201 and the R-channel data is output from the AND circuit 202 from the signal waveform shown in FIG. Are output as word data DRi (i = 1, 2,... M).
[0050]
The L-channel word data DLi output from the AND circuit 201 is input to the contact “a” of the switch circuit 208, and is input to the contact “b” of the switch circuit 208 after being delayed by a half of the sampling period T by the delay circuit 205. Is done. The switch circuit 208 connects the common terminal c to the contact a when the LRCK signal is at the L level, and connects the common terminal c to the contact b when the LRCK signal is at the H level.
[0051]
Therefore, the switch circuit 208 alternately outputs L-channel word data DLi and word data DLi ′ delayed by T / 2 from the word data DLi. That is, the switch circuit 208 outputs word data strings DL1, DL1 ', DL2, DL2',... DLi, DLi ', DLi + 1, DLi + 1',. Since the contents of the word data DLi and the word data DLi ′ are the same, if the data contents represent a word data string, the switch circuit 208 outputs the L-channel word data strings DL1, DL1, DL2, DL2,. DLi, DLi + 1, DLi + 1,... Are output (see Lc in FIG. 3).
[0052]
The switch circuit 209 connects the common terminal f to the contact d when the LRCK signal is at the L level, and connects the common terminal f to the contact e when the LRCK signal is at the H level. Accordingly, the switch circuit 209 alternately outputs word data DRi of the R channel and word data DRi ′ delayed by T / 2 from the word data DRi. That is, the switch circuit 209 outputs the R channel word data strings DR1, DR1 ', DR2, DR2', ..., DRi, DRi ', DRi + 1, DRi + 1', .... When a word data string is represented by the data content, the switch circuit 209 outputs the R channel word data strings DR1, DR1, DR2, DR2,... DRi, DRi, DRi + 1, DRi + 1,. .
[0053]
The word data DLi of the L channel output from the switch circuit 208 and the word data DRi of the R channel output from the switch circuit 209 are data at the same sign pulling position. However, the data of the L channel depends on the format of the DATA input in the I2S mode. The word data DLi is output T / 2 earlier than the word data DRi of the R channel. From the SDF conversion circuit 2, the serial signals of the L-channel word data strings DL1, DL1, DL2, DL2,... DLi, DLi, DLi + 1, DLi + 1, and the R-channel word data strings DR1, DR1, DR2, DR2,. , DRi, DRi + 1, DRi + 1,..., Must be output in the same phase as the serial signal. Therefore, the word data DLi of the L channel output from the switch circuit 208 is delayed by T / 2 by the delay circuit 207 to obtain the word of the R channel. It is adjusted to the output timing of the data DRi.
[0054]
Then, serial data composed of L-channel word data strings DL1, DL1, DL2, DL2,... DLi, DLi, DLi + 1, DLi + 1,... Outputted from the switch circuit 208 via the delay circuit 207, and outputted from the switch circuit 209. , And serial data composed of word data strings DR1, DR1, DR2, DR2,... DRi, DRi, DRi + 1, DRi + 1,. After that, the signals are output from the L channel output terminal OUT1, the R channel output terminal OUT2, and the LRCK output terminal OUT3 (see LRCK, Lout, and Rout in FIGS. 3 and 4). The BCLK signal is output from the BCLK output terminal OUT4 via the inversion circuit 204.
[0055]
By the above operation, the SDF conversion circuit 2 converts the I2S mode digital audio signal including the DATA signal (digital composite signal) obtained by mixing the L-channel audio data and the R-channel audio data, the LRCK signal, and the BCLK signal into one. .., DLi, DLi,..., And the R channel word data strings DR1, DR1, DR2, DR2,. The digital audio signal is converted into a digital audio signal including the DATA ′ signal, the LRCK signal, and the BCLK signal, and is output.
[0056]
Returning to FIG. 1, the one-bit DA conversion circuit 3 converts an input digital signal into an analog signal serially for each bit and outputs the analog signal. The one-bit DAC 31L included in the one-bit D / A conversion circuit 3 includes a DATA ′ signal, an LRCK signal, and a BCLK from the SDF conversion circuit 2 which are composed of the word data strings DL1, DL1, DL2, DL2,..., DLi, DLi,. Are input to the one-bit DAC 31R. The DATA ′ signal, the LRCK signal, and the BCLK signal including the word data strings DR1, DR1, DR2, DR2,..., DRi, DRi,. Is entered.
[0057]
As shown in FIG. 5, the one-bit DAC 31L includes an audio data L (T) composed of the original word data DLi column from the DATA 'signal and a word data DLi' column delayed by T / 2 from the audio data L (T). A digital filter 311 that separates audio data L (-T) from audio data L (T) and DA conversion circuits 312 and 313 that convert each audio data L (T) and L (-T) into an analog signal serially for each bit. It is configured. One-bit DAC 31R has the same configuration as one-bit DAC 31L.
[0058]
Therefore, from the one-bit DAC 31L, the analog signal L (t) obtained by DA-converting the L-channel audio data L (T) by the DA conversion circuit 312 and the L-channel audio data L (-T) are converted by the DA conversion circuit 313. The D-converted analog signal L (-t) is output, and the one-bit DAC 31R outputs an analog signal R (t) obtained by DA-converting the audio data R (T) of the R channel by the DA conversion circuit 312 and an analog signal R (t) of the R channel. An analog signal R (-t) obtained by DA-converting the audio data R (-T) by the DA conversion circuit 313 is output.
[0059]
The ASP circuit 4 performs the same function as the ASP circuits 108 and 109 of the conventional DA converter 100 described above. The ASP circuit 41L in the ASP circuit 4 corresponds to the ASP circuit 108, and the ASP circuit 41R corresponds to the ASP circuit 109. In this embodiment, each of the ASP circuits 108 and 109 has the same circuit configuration (the circuit configuration shown in FIG. )have.
[0060]
Therefore, although the detailed description of the ASP circuits 41L and 41R is omitted here, an analog signal connecting the signal levels between the sampling points of the L-channel audio signal L (T) is output from the ASP circuit 41L as an audio analog signal. And the ASP circuit 41R outputs an analog signal obtained by connecting the signal levels between the sampling points of the R channel audio signal R (T) as an audio analog signal.
[0061]
As described above, the DA converter 1 according to the present embodiment includes the SDF conversion circuit 2, the one-bit DA conversion circuit 3, and the ASP circuit 4, and converts the L-channel audio data and the R-channel audio data into words. I2S mode digital audio comprising a DATA signal alternately serially arranged in units, a word clock for identifying the word data of the DATA signal, and a bit clock for identifying the bit data of the DATA signal The signal is separated into L-channel audio data and R-channel audio data by the SDF conversion circuit 2, and for both channels, delayed data is generated by delaying the input data by one sampling time. Audio that is serially arranged alternately in word units The first analog signal S (t) corresponding to the input data and the second analog signal corresponding to the delayed data are converted by the one-bit DA conversion circuit 3 using the audio data, the word clock and the bit clock. S (-t) is generated, and the ASP circuit 4 generates and outputs an audio analog signal connecting the signal levels between the sampling points by using the analog signals S (t) and S (-t). Therefore, the circuit configuration becomes simpler and the cost can be reduced as compared with the case where the DA converter is configured using the conventional multi-bit DAC.
[0062]
That is, in a DA converter using a conventional multi-bit DAC, for example, in the case of two channels, the multi-bit DAC is used to generate a first analog signal S (t) and a second analog signal S (−t). Although four components were required, the present embodiment requires only two one-bit DACs, and the unit cost of the one-bit DAC is lower than that of the multi-bit DAC, so that the circuit configuration is simplified and the cost is reduced. Becomes possible.
[0063]
In the above-described embodiment, a case has been described in which a new type of D / A converter is configured for both the L channel and the R channel. The invention can be applied.
[0064]
【The invention's effect】
As described above, according to the present invention, the data format of a digital audio signal input in various modes is changed by serially changing the input data and the delayed data delayed by one input sampling time in units of words. The first analog signal obtained by DA conversion of the original audio data by the one-bit DA converter using the data after the format conversion, and the first analog signal are sampled for one sampling time. And a second analog signal delayed by only the second analog signal, and using both analog signals to generate an analog signal connecting signal levels between sampling points and outputting the analog signal as an analog audio signal. Low cost D / A converter with simple circuit configuration compared to conventional D / A converter It can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram of a DA converter according to the present invention.
FIG. 2 is a block diagram illustrating a circuit configuration of an SDF conversion circuit.
FIG. 3 is a diagram illustrating a relationship between input / output data of a switch circuit on an L channel side and data output from an output terminal in signal processing based on an LRCK signal in an SDF conversion circuit.
FIG. 4 is a diagram illustrating a relationship between input / output data of a switch circuit on an R channel side and data output from an output terminal in signal processing based on an LRCK signal in an SDF conversion circuit.
FIG. 5 is a functional block diagram of a one-bit DAC.
FIG. 6 is a block diagram showing a configuration of a conventional new type DA converter.
FIG. 7 is a diagram showing a signal waveform of a digital audio signal transmitted in the I2S mode.
FIG. 8 is a diagram showing a signal waveform of a digital audio signal transmitted in another mode.
FIG. 9 is a waveform chart for explaining an analog signal generated by analog signal processing in the ASP circuit.
FIG. 10 is a diagram illustrating an example of a circuit configuration of an ASP circuit.
[Explanation of symbols]
1 DA converter
2 Serial data format conversion circuit (format conversion means)
IN1, IN2, IN3 Input terminals (input means)
OUT1, OUT2, OUT3, OUT4 output terminals
201, 202 AND circuit
203,204 Inverting circuit
205, 206, 207 delay circuit
208, 209 switch circuit
210, 211, 212 Latch circuit
3. One-bit DA conversion circuit (one-bit DA conversion means)
4 Analog signal processing circuit (analog signal processing means)

Claims (3)

Data in which L-channel audio data and R-channel audio data are alternately serially arranged in word units, a word clock for identifying the word data of the data, and a bit clock for identifying the data. The data format of the digital audio signal constituted by the bit clock is generated by generating delay data obtained by delaying the input data by one sampling time for at least one channel, and the input data and the delay data are converted into word units. Audio data conversion means for converting into an audio data format that is serially and alternately arranged with
The audio data converted by the audio data conversion means is separated into input data and delay data using the word clock, and the input data is serially DA converted bit by bit using the bit clock, and the first One-bit DA conversion means for generating an analog signal and serially DA-converting the delayed data bit by bit using the bit clock to generate a second analog signal;
Analog signal processing means for generating an analog signal connecting signal levels between sampling points using the first analog signal and the second analog signal generated by the one-bit DA conversion means, and outputting the analog signal as an analog audio signal When,
A DA converter comprising: The audio data conversion means calculates an AND of the data and the word clock to extract an input data of one channel, and converts the input data from the input data extracted by the AND circuit to the input data. A delay circuit that generates the delay data by delaying by a half of one cycle of the word clock; and the one-bit DA of input data output from the AND circuit and delay data output from the delay circuit 2. The DA converter according to claim 1, further comprising a switch circuit that alternately switches the output to the conversion means in word units based on the word clock. 3. The DA converter according to claim 2, wherein said delay circuit comprises a shift register.

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