JPH08274644A - Digital signal processing method and device therefor - Google Patents

Abstract

PURPOSE: To suppress the noises which are caused through the switching carried out between an original ΣΔ signal and this signal that undergone the ΔΔprocessing again by changing gradually both through and operating states of the second ΣΔ modulation processing. CONSTITUTION: This signal processing method/device is provided with a ΣΔmodulator 5 which receives the output from a multiplier 4 and can perform the switching between a through state where the input signal is outputted as it is and an operating state where the input signal is outputted after it undergone the second ΣΔmodulation, and a gain controller 9 which gradually changes both through and operating states. Then the through and operating states of the second ΣΔ modulation processing are gradually changed, so that the switching is carried out between a state where an input signal of a small number of bits is outputted as it is and a state where the input signal is outputted after it undergone the second ΣΔ modulation. Therefore the noises caused when the switching is carried out between an original ΣΔsignal and this signal that undergone the ΣΔ modulation again can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing method and apparatus for performing signal processing in the amplitude direction on a voice signal digitized with a small number of bits such as 1 bit.

[0002]

2. Description of the Related Art For example, a method of digitizing an audio signal and recording, reproducing and transmitting it has been conventionally known as a compact disc (CD) or a digital audio tape (DAT).
It is carried out by a recording / reproducing apparatus such as the above, and digital audio broadcasting such as satellite broadcasting. In such a digital audio transmission apparatus, conventionally, when digitizing the digital audio transmission apparatus, the sampling frequency is 48 kHz or 44.1 kHz.
Etc., and a format such as 16 bits has been defined as the number of quantization bits.

However, in such a conventional digital audio transmission apparatus, the number of quantization bits of digital audio data generally defines the dynamic range of a demodulated audio signal. Therefore, for example, in order to transmit a higher quality audio signal, it is necessary to increase the number of quantization bits from the current 16 bits to 20 or 24 bits or the like. However, once the format is specified, it is not possible to easily increase the number of quantization bits, so that it is not possible to extract a higher quality audio signal from these devices.

By the way, a method called sigma delta (ΣΔ) modulation has been proposed as a method for digitizing a voice signal (Acoustic Society of Japan, Vol. 46, No. 3, (199).
0) pp. 251-257, "AD / DA converter and digital filter (Yoshio Yamazaki)", etc.).

FIG. 11 is a block diagram of a ΣΔ modulation circuit for performing ΣΔ modulation processing on 1-bit digital data, for example. In FIG. 11, the input audio signal from the input terminal 51 is supplied to the integrator 53 through the adder 52. The signal from the integrator 53 is supplied to the comparator 54, is compared with, for example, the midpoint potential of the input audio signal, and is quantized by, for example, 1 bit for each sampling period. The frequency (sampling frequency) of the sampling period is 64 times or 128 times that of the conventional 48 kHz and 44.1 kHz. The quantization may be 2 bits or 4 bits.

This quantized data is a 1-sample delay unit 55.
And is delayed by one sample period. This delay data is converted into an analog signal by, for example, a 1-bit D / A converter 56 and supplied to the adder 52, and the input terminal 51
Is added to the input audio signal from. Then, the quantized data output from the comparator 54 is taken out to the output terminal 57. Therefore, according to the ΣΔ modulation processing performed by this ΣΔ modulation circuit, as described in the above-mentioned document, by sufficiently increasing the frequency of the sampling period (sampling frequency), for example, even a small number of bits of 1 bit is high. A dynamic range audio signal can be obtained. Moreover, it is possible to have a wide transmittable frequency band. Further, since the ΣΔ modulation circuit has a circuit configuration suitable for integration and the accuracy of A / D conversion can be obtained relatively easily, it has been conventionally used often in an A / D converter. . The ΣΔ modulated signal can be converted back into an analog audio signal by passing through a simple analog low pass filter. Therefore, Σ
The Δ modulation circuit can be applied to a recorder that handles high quality data and data transmission by making the most of these characteristics.

By the way, in the digital audio transmission apparatus using the ΣΔ modulation circuit, a digital audio transmission apparatus (hereinafter, referred to as a multi-bit digital audio transmission apparatus) that handles a digital signal in a multi-bit format such as 16 bits described above. It is difficult to realize signal processing in the amplitude direction, such as fade processing, equalization processing, filter processing, crossfade processing, and mixing processing, which are types of attenuation processing that could be realized with. I couldn't take advantage of the characteristics of wide band and high dynamic range.

For example, the fade processing includes a fade-out processing for gradually decreasing the level of a reproduced audio signal with time and a fade-in processing for gradually increasing the level of an audio signal from zero level. Such a fade process is common as a signal process in the amplitude direction of an audio signal.

Therefore, a case where the fade process is performed by the multi-bit digital audio transmission device will be described with reference to FIG. In FIG. 12, a multi-bit digital audio signal of, for example, 16 bits from the input terminal 61 is a multiplier 6
2 to the output terminal 63. Here, for example, when a control signal designating a fade start timing and a speed is supplied to the control input terminal 64, this control signal is supplied to the control circuit 65 to generate an arbitrary fade signal. Then, by supplying this fade signal to the coefficient generator 66, for example, a coefficient that gradually reduces the level of the audio signal to zero level is generated, and this coefficient is supplied to the multiplier 62.

As a result, the level of the audio signal with respect to the digital audio signal supplied to the digital signal input terminal 61 is gradually output to the output terminal 63 at a specified speed from the timing specified by the control signal, for example. The signal that is lowered and muted to zero level is taken out,
The fade-out process is performed. It is also possible to perform a fade-in process of gradually increasing the level of the audio signal from zero level by reversing the order of generation of the coefficients.

However, as described above, such processing cannot be performed on the ΣΔ-modulated digital audio signal. That is, since the amplitude information of the ΣΔ-modulated 1-bit signal is also expressed as a 1-bit pattern on the time axis, it is difficult to perform the multiplication by the multiplier 62 and realize the amplitude operation processing as in the conventional case. It was

On the other hand, for example, as shown in FIG. 13, a ΣΔ signal is converted into a conventional CD or DA by using a low-pass filter.
It is conceivable to convert into a signal format such as T and perform processing. That is, in FIG. 13, the input terminal 7
For example, the 1-bit ΣΔ signal supplied to 1 is supplied to the low-pass filter 72 and converted into, for example, a 16-bit multi-bit digital audio signal. The converted digital audio signal is supplied to the multiplier 73.

Further, for example, a control signal designating a fade start timing and a speed is supplied to the control input terminal 74, and this control signal is supplied to the control circuit 75 to generate an arbitrary fade signal. By supplying the fade signal to the coefficient generator 76, for example, a coefficient that gradually reduces the level of the audio signal to zero level is generated, and the coefficient is supplied to the multiplier 73.

As a result, the multiplier 73 extracts the digital audio signal from the low-pass filter 72 from the digital audio signal whose level is controlled by the coefficient from the coefficient generator 76. Then, the digital audio signal is further supplied to the ΣΔ modulator 77, and again converted into, for example, a 1-bit ΣΔ signal, and the reconverted ΣΔ signal is taken out to the output terminal 78.

Thus, the output terminal 78 is connected to the input terminal 71.
With respect to the ΣΔ signal from, the level of the audio signal is gradually reduced at a specified speed from the timing specified by the control signal, and a signal of which the level is zero is taken out, and so-called fade-out processing is performed. In addition,
For example, the fade-in process of gradually increasing the level of the audio signal from the zero level can be performed by reversing the order of generation of the coefficients. That is, according to this apparatus, it is possible to perform processing such as fade in the same manner as in the past.

[0016]

By the way, when this apparatus is used, the ΣΔ signal supplied to the input terminal 71 is always converted into a 16-bit multi-bit digital audio signal by the low-pass filter 72. That is, in this device, the ΣΔ signal is processed by the low-pass filter 72 and the ΣΔ modulator 77 even when processing such as fading is not performed.
Pass through. For this reason, the characteristics of the signal become the same as those of the conventional CD, DAT, etc., and the characteristics of the original ΣΔ modulation such as wide band and high dynamic range cannot be utilized.

Therefore, as shown in FIG. 14, when the amplitude operation such as the fade process is not performed, the switch 78 is used.
The ΣΔ modulator supplied to the selected terminal B of the switch 78 is derived only when the original ΣΔ signal supplied to the selected terminal A of the switch 78 is derived from the output terminal 80 via the delay device 79 and the above amplitude operation is performed. It was considered to derive the ΣΔ signal remodulated at 77 from the output terminal 80.

However, the two ΣΔ signals switched by the switch 78 are signals modulated on the time axis by different ΣΔ modulators although they have substantially the same analog audio signal component, and thus are directly switched. Then, a big noise was generated at the switching point and it was not practical.

The present invention has been made in view of the above circumstances, and noise is generated when switching between an original sigma delta signal and a re-sigma delta signal obtained by subjecting the original sigma delta signal to sigma delta processing again. An object of the present invention is to provide a digital signal processing method and apparatus capable of suppressing the above.

[0020]

A digital signal processing method according to the present invention is a digital signal processing for performing signal processing including sigma delta modulation again on an input signal of a small number of bits obtained by sigma delta modulation. In this method, switching between a state in which the minority bit input signal is output as it is and a state in which the sigma-delta modulation is performed again is output, and the through state and the operating state of the sigma-delta modulation process again is gradually changed. By doing so, the above problems are solved.

Further, the digital signal processing apparatus according to the present invention is such that arithmetic means for arithmetically processing an input signal of a few bits obtained by sigma-delta modulation using a multi-bit signal, and an output from this arithmetic means are inputted. The sigma-delta modulation means capable of switching between the through state in which the input signal is output as it is and the operation state in which the sigma-delta modulation is performed again, and the through state and the operation state of the sigma-delta modulation means are gradually changed. The above-mentioned problem is solved by providing a control means for controlling.

[0022]

The sigma-delta modulation processing is performed by increasing or decreasing the amplitude component of the input signal of a small number of bits obtained by the sigma-delta modulation and using the nth (n is 3 or more) order filter provided for the integration at the output. When applied, the gain of the nth-order filter is changed so as to be gradually suppressed or demodulated. As a result, when transmitting and recording 1-bit digital data that is ΣΔ modulated, it is possible to switch between the original signal of high quality and the second sigma-delta modulated signal that has undergone signal processing such as amplitude manipulation, as necessary. .

[0023]

Embodiments of the digital signal processing method and apparatus according to the present invention will be described below with reference to the drawings.

In this embodiment, an input audio signal is sigma delta (ΣΔ) modulated and recorded on a magnetic tape in the form of, for example, a 1-bit digital signal (hereinafter referred to as 1-bit digital data), and 1 bit from the magnetic tape. This is a preferable digital signal processing device applied to a digital audio recording / reproducing device for reproducing and outputting digital data, and the 1-bit digital data is subjected to an amplitude direction such as a fade process, an equalize process, a filter process, which is a kind of attenuation process. Signal processing can be performed. The signal processing in the amplitude direction is processing for increasing or decreasing the amplitude component of the 1-bit digital data.

As shown in FIG. 1, the digital signal processing apparatus 1 includes a multiplier 4 for performing an arithmetic operation using a multi-bit signal on the ΣΔ-modulated 1-bit digital data supplied from an input terminal 2. An output from the multiplier 4 is input, and a ΣΔ modulator 5 capable of switching between a through state in which the input signal is output as it is and an operating state in which the ΣΔ modulation is performed again, and the through state of the ΣΔ modulator 5 And a gain control unit 9 for gradually changing the operating state.

Here, the multiplier 4 and the ΣΔ modulator 5 constitute an amplitude control block 3. When a signal processing in the amplitude direction such as a fade processing is selected by the user, the multiplier 4 has, for example, a 16-bit multi-valued multiplication coefficient generated by the coefficient generator 7 for the 1-bit digital data. Multiplies the multi-bit multiplication factor. Further, when the user has not selected the signal processing in the amplitude direction, the multiplier 4 outputs (throughs) the 1-bit digital data as it is.
The coefficient generator 7 generates the 16-bit multi-bit multiplication coefficient according to the command signal for signal processing in the amplitude direction selected by the user and supplied to the control circuit 8. The command signal for executing signal processing in the amplitude direction selected by the user, for example, fade processing, is supplied to the control circuit 8 via a control signal input terminal (not shown). Then, the control circuit 8 causes the coefficient generator 7 to generate a multi-bit multiplication coefficient based on the command signal for executing the fade process. The multi-bit, for example, 16-bit digital data output from the multiplier 4 is supplied to an adder, which will be described later, that constitutes the ΣΔ modulation unit 5.

The .SIGMA..DELTA. Modulator 5 performs integration processing on the addition output of the adder, and quantizes the data from the integration unit into 1-bit digital data for each sample period. And the quantizer 15 shown. The quantized output of the quantizer 15 is given a negative sign and fed back to each adder of the integration unit, and added (resultingly subtracted) to the multiplication output of the multiplier 4. Then, the 1-bit digital data which is the quantized output output from the quantizer 15 is taken out from the output terminal 6.

The integrator is an n-th (n is 3 or more) -order filter, and the gain control unit 9 gradually changes the gain of each filter for each filter to operate the through state and the sigma-delta modulation. The state is gradually switched and controlled. In this embodiment, the integrating unit is divided into a third-order (three-stage) filter as shown in FIG. Then, the gain control unit 9 changes the gain of the variable gain amplifier forming each filter for each stage.

That is, the ΣΔ modulator 5 divides the integrator into a first stage 12, a second stage 13, and a third stage 14, and the signals passed through these stages 12, 13, 14 are quantized. Chemicalizer 1
5 is quantized and fed back to each stage, and is also derived from the output terminal 16.

Here, the multi-bit multiplication output or the through output supplied from the multiplier 4 via the input terminal 11 is the adder 1 which constitutes the first stage 12 of the integration block.
2a. The output of the adder 12a is the adder 12
It is supplied to the delay device 12c via b and is delayed by the delay device 12c. The delayed output of the delay device 12c is fed back to the adder 12b via the first variable gain amplifier 12d having the variable coefficient k ₃₁ . Also, the adder 12
In a, the quantized data from the quantizer 15 is a variable coefficient k.
_{The signal} is fed back as a negative sign via the second variable gain amplifier 12e having ₃₂ . The delay output of the delay device 12c is supplied to the next stage, that is, the second stage 13 via the third variable gain amplifier 12f having the variable coefficient k ₃₃ .

Here, the variable coefficients k ₃₁ , k ₃₂ , and k ₃₃ have a relationship of k ₃₁ = k ₃₃ (k ₃₂ −1) +1.

The output of the first stage 12 is supplied to the adder 13a which constitutes the second stage 13. The output of the adder 13a is supplied to the delay device 13c via the adder 13b,
It is delayed by the delay device 13c. The delay output of the delay unit 13c is the first variable gain amplifier 1 having the variable coefficient k _21.
It is fed back to the adder 13b via 3d.
The adder 13a has a second variable gain amplifier 13 in which the quantized data from the quantizer 15 has a variable coefficient k _22.
A negative sign is given via e and fed back. Also,
Delayed output of the delay device 13c is the next stage through a third variable gain amplifier 13f having a variable coefficient k _23, i.e. is supplied to the third stage 14.

Here, the variable coefficients k ₂₁ , k ₂₂ and k ₂₃ are also given the relationship of k ₂₁ = k ₂₃ (k ₂₂ −1) +1.

The output of the second stage 13 is supplied to the adder 14a which constitutes the third stage 14. The output of the adder 14a is supplied to the delay device 14c via the adder 14b,
It is delayed by the delay device 14c. The delay output of the delay device 14c is the first variable gain amplifier 1 having the variable coefficient k _11.
It is fed back to the adder 14b via 4d.
Further, the adder 14a has a second variable gain amplifier 14 in which the quantized data from the quantizer 15 has a variable coefficient k _12.
A negative sign is given via e and fed back. Also,
The delay output of the delay device 14c is supplied to the next stage, that is, the third stage 14 via the third variable gain amplifier 14f having the variable coefficient k ₁₃ .

Here, the variable coefficients k ₁₁ , k ₁₂ , and k ₁₃ are also given the relationship of k ₁₁ = k ₁₃ (k ₁₂ −1) +1.

That is, each filter of the ΣΔ modulator 5 is
First variable gain amplifiers 12d, 13d, 14d that are passed through when delaying a signal via delay devices 12c, 13c, 14c for delaying an input signal, and the above ΣΔ
Second variable gain amplifier 1 that passes when the quantized output of the quantizer 15 that constitutes the modulation process is fed back
2e, 13e, 14e and the delays 12c, 13c,
A third variable gain amplifier 12f, 13f, 14f that passes the signal via 14c to the next stage, and these first variable gain amplifier, second variable gain amplifier, and third variable gain Each variable coefficient k _n1 , k of the amplifier
_n2 and k _n3 are made to satisfy the relationship of k _n1 = k _n3 (k _n2 −1) +1 (1).

For example, the ΣΔ modulator 5 as shown in FIG.
, (K ₁₁ = k ₁₂ = k ₁₃ = 1), (k ₂₁ = k ₂₂ = 1, k)
₂₃ = 1/2), and a _{(k 31 = k 32 = 1} , k 33 = 1/4).

First, the gain control section 9 changes the variable coefficient k ₃₁ ,
By changing k ₃₂ and k ₃₃ , (k ₃₁ = k ₃₂ = 0, k ₃₃ = 1)
The gain is gradually changed so that Then, the ΣΔ modulator 5 has a second-order Σ that has one delay device 12c.
Becomes a Δ modulator.

Next, the gain controller 9 controls the variable coefficient k ₂₁ ,
The k _22, k ₂₃ is _{varied, (k 21 = k 22 =} 0, k 23 = 1)
The gain is gradually changed so that Then, the ΣΔ modulator 5 becomes a primary ΣΔ modulator having the two delay devices 12c and 13c.

Further, the gain control section 9 changes the variable coefficients k ₁₁ , k ₁₂ and k ₁₃ to obtain (k ₁₁ = k ₁₂ = 0, k ₁₃
The gain is gradually changed so that = 1). Then, the ΣΔ modulator 5 has three delay units 12c and 13c.
It becomes a single quantizer 15 having c and 14c.

That is, the variable coefficients of the three variable gain amplifiers in each one stage of the integration section divided into three stages of the ΣΔ modulation section 5 are controlled by the gain control section 9 so as to gradually change. It These three variable gain amplifiers are changed for each one stage.

In particular, in this example, the ΣΔ modulator 5 functions as a third-order filter, and each variable coefficient of each variable gain amplifier is (k ₁₁ = k ₁₂ = k ₁₃ = 1), (k ₂₁ = k ₂₂ = 1, k ₂₃
= 1/2) and (k ₃₁ = k ₃₂ = 1, k ₃₃ = 1/4), the original 1-bit digital data is finally output.

When switching from the original 1-bit digital data to the 1-bit digital data which has been subjected to the second ΣΔ modulation in the ΣΔ modulation section 5, the amplitude control block 3 is caused to perform the reverse operation of the above-described specific example. Good.

For example, provided that the relationship of the above equation (1) is satisfied, as shown in FIGS. 3, 4 and 5, the variable coefficients (k ₃₁ , k ₃₂ , k ₃₃ ) and (k ₂₁ , k) are changed. ₂₂ , k ₂₃ ) and (k
By gradually changing ( ₁₁ , k ₁₂ , k ₁₃ ), switching can be realized while suppressing noise generation.

It should be noted that, as shown in FIG. 6, the multiplier 4 determines whether the 1-bit digital data is in the binary state, that is, "1" or "-1". Is multiplied by a positive or negative 16-bit multi-bit multiplication coefficient. That is, the positive or negative multi-bit multiplication coefficient generated by the coefficient generator 7 in response to the command signal supplied to the control circuit 8 becomes the 1-bit digital data according to the binary state of the 1-bit digital data. Is multiplied.

The operation performed by the multiplier 4 on the 1-bit digital data is signal processing in the amplitude direction such as fade processing, equalization processing, which is a kind of attenuation processing as described above. The calculation performed by the multiplier 4 will be simplified and described as, for example, a calculation that reduces the amplitude of the input signal to 1/2.

For example, the amplitude of the input signal is set to 1 in the multiplier 4.
The processing result in the case of performing the calculation such as / 2 will be described with reference to FIG. FIG. 7A is a signal waveform diagram when 1-bit digital data supplied to the input terminal 2 of FIG. 1 is returned to an analog signal through an analog low-pass filter. FIG. 7B is a signal waveform diagram when the 1-bit digital data obtained by the calculation performed by the multiplier 4 is returned to an analog signal. That is, although the input and output bit lengths are the same 1 bit, the patterns are greatly different, and the amplitude of the analog audio signal obtained by passing through a simple analog filter is 1/2.

As described above, the digital signal processing apparatus 1 according to the present embodiment can suppress the generation of noise when switching between the original ΣΔ signal and the re-ΣΔ signal obtained by processing the original ΣΔ signal again by ΣΔ. it can. Therefore, when transmitting and recording ΣΔ-modulated 1-bit digital data, the high-quality original signal and the second ΣΔ-modulated signal that has undergone signal processing such as amplitude operation are suppressed in noise as necessary. You can switch.

Here, the digital audio recording / reproducing apparatus to which the digital signal processing apparatus 1 is applied performs ΣΔ modulation processing on the input audio signal to make 1-bit digital data, and the 1-bit digital data is set every predetermined number of units. FIG. 8 recording together with the synchronization signal and the error correction code.
And a magnetic tape 2 of the recording unit 20 as shown in FIG.
9 is used to reproduce 1-bit digital data for each predetermined number of units described above. The digital signal processing device 1 is provided in the reproducing unit 30, but for convenience of description, the recording unit 20 will be described first.

As shown in FIG. 8, in the recording section 20,
The input audio signal from the input terminal 21 is supplied to the integrator 23 through the adder 22. The signal from the integrator 23 is supplied to the comparator 24, is compared with, for example, the midpoint potential (“0V”) of the input audio signal, and is quantized by 1 bit for each sampling period. Here, the frequency of the sampling period (sampling frequency) is 48 kHz,
A frequency that is 64 times or 128 times that of 4.1 kHz is used.

This quantized data is a 1-sample delay unit 25.
And is delayed by one sample period. This delay data is supplied to the adder 22 through the 1-bit digital / analog (D / A) converter 26 and added to the input audio signal from the input terminal 21. As a result, the comparator 24 outputs quantized data obtained by ΣΔ-modulating the input audio signal. The quantized data output from the comparator 24 is the synchronization signal and the error correction code (E
The CC) is supplied to the addition circuit 27, and, for example, the synchronization signal and the error correction code are added to the quantized data for each predetermined number of samples.

In this recording format, 1-bit digital data, which is 1-bit quantized data, is divided into four pieces such as data D _{0 to} D ₃ as shown in FIG. Sync signals S ₀ and S ₁ and error correction codes P ₀ and P ₁ are added to each bit digital data. With this synchronization signal and the error correction codes P ₀ and P ₁ added by the ECC adding circuit 7, it is possible to detect and correct transmission errors that occur during recording and reproduction.

Next, in the reproducing section 30 shown in FIG. 10, the reproducing head 31 reproduces the 1-bit digital data recorded on the magnetic tape 29. Since this 1-bit digital data is recorded in a format to which the sync signal and the error correction code are added every four data,
When supplied to the sync separation and error correction circuit 32, the sync signal is separated and subjected to error correction processing to extract only 1-bit digital data in units of 4 in which the above-mentioned input audio signal is ΣΔ modulated. This 1-bit digital data is supplied to the digital signal processing device 1 whose detailed configuration is shown in FIG.

The 1-bit digital data is processed by the digital signal processing device 1 as described above. The 1-bit digital data signal-processed by the digital signal processing device 1 is returned to the analog audio signal by the analog filter 33. This analog audio signal is taken out from the monitor terminal 34.

The re-ΣΔ modulated 1-bit digital data output from the digital signal processing device 1 is converted into a signal format such as CD or DAT by a digital filter 35 which is a decimation (decimation) filter. The signal converted into the arbitrary format is used as the reproducing system 36 of the digital recorder of the arbitrary format, the reproducing system 37 of the CD or DAT, or the DCC.
It is supplied to the normal D / A converter 39 through the reproduction system 38 of FIG. Then, the analog audio signal is taken out from the output terminal 40.

Therefore, the digital audio recording / reproducing apparatus to which the digital signal processing apparatus 1 of the present embodiment is applied, when transmitting and recording the ΣΔ-modulated 1-bit digital data, the original signal of high quality and the amplitude operation etc. The second ΣΔ modulated signal that has undergone signal processing can be switched while suppressing noise.

The digital signal processing method and apparatus according to the present invention are not limited to the above embodiments, and for example, if the order of the nth order filter forming the ΣΔ modulator is 3 or more. Good.

[0058]

According to the digital signal processing method of the present invention, when the minority bit input signal obtained by the sigma delta modulation is subjected to the signal processing including the sigma delta modulation again, the minority bit input signal is processed. Switching between the state of outputting as it is and the state of performing sigma-delta modulation again and outputting is performed by gradually changing the through state and the operating state of the above-mentioned sigma-delta modulation processing again. , The original ΣΔ
Generation of noise can be suppressed when switching between the re-ΣΔ signal obtained by processing the signal again by ΣΔ.

Further, the digital signal processing apparatus according to the present invention is such that arithmetic means for performing arithmetic processing using a multi-bit signal on an input signal of a small number of bits obtained by sigma delta modulation, and an output from this arithmetic means are input. The sigma-delta modulation means capable of switching between the through state in which the input signal is output as it is and the operation state in which the sigma-delta modulation is performed again, and the through state and the operation state of the sigma-delta modulation means are gradually changed. Control means for controlling the original ΣΔ signal and the original ΣΔ signal.
It is possible to suppress the generation of noise when switching between the re-ΣΔ signal obtained by processing the signal again by ΣΔ.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital signal processing apparatus which is an embodiment of a digital signal processing method and apparatus according to the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a ΣΔ modulation section of the digital signal processing device of the above embodiment.

FIG. 3 is a characteristic diagram showing a specific example of a change over time of a variable coefficient of a variable gain amplifier which constitutes a first stage of an integration unit of the ΣΔ modulation unit.

FIG. 4 is a characteristic diagram showing a specific example of a change over time of a variable coefficient of a variable gain amplifier which constitutes a second stage of the integration unit of the ΣΔ modulation unit.

FIG. 5 is a characteristic diagram showing a specific example of a change over time of a variable coefficient of a variable gain amplifier which constitutes a third stage of the integration section of the ΣΔ modulation section.

FIG. 6 is a schematic diagram for explaining the operation of the multiplier of the amplitude control block that constitutes the digital signal processing device of the above embodiment.

FIG. 7 is an analog waveform diagram for explaining a specific result of the calculation performed by the multiplier.

FIG. 8 is a block diagram showing a schematic configuration of a recording section of a digital audio data recording / reproducing apparatus to which the digital signal processing apparatus of the above-mentioned embodiment can be applied.

FIG. 9 is a format diagram showing an example of a recording format used in the digital audio data recording / reproducing apparatus.

FIG. 10 is a block diagram showing a schematic configuration of a reproducing section of a digital audio data recording / reproducing apparatus to which the digital signal processing apparatus of the above embodiment can be applied.

FIG. 11 is a block diagram showing a schematic configuration of a ΣΔ modulation circuit.

FIG. 12 is a block diagram showing a schematic configuration of a multi-bit digital signal processing device.

FIG. 13 is a block diagram showing a schematic configuration of a conventional digital signal processing device that handles a small number of bits digital signal.

14 is a block diagram showing a schematic configuration of a digital signal processing device configured to switch between an original small number bit signal and a signal converted into a small number of bits again by using the digital signal processing device shown in FIG. .

[Explanation of symbols]

 1 Digital Signal Processing Device 3 Amplitude Control Block 4 Multiplier 5 ΣΔ Modulation Section 7 Coefficient Generator 8 Control Circuit 9 Gain Control Section

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[Procedure amendment]

[Submission date] December 1, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

By the way, in the digital audio transmission apparatus using the ΣΔ modulation circuit, a digital audio transmission apparatus (hereinafter, referred to as a multi-bit digital audio transmission apparatus) that handles a digital signal in a multi-bit format such as 16 bits described above. Amplitude processing such as fade processing, equalization processing, filter processing, cross-fade processing, and mixing processing, which are types of attenuation processing that can be realized in (. It was difficult to do that, and I couldn't take advantage of the features of wide bandwidth and high dynamic range.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

However, as described above, such processing cannot be performed on the ΣΔ-modulated digital audio signal. That is, since the ΣΔ-modulated 1-bit signal also has the amplitude information represented as a 1-bit pattern on the time axis, multiplication is performed by the multiplier 62 as in the conventional case, and the amplitude operation processing is realized with 1 bit as it is. It was difficult.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction content]

For example, the amplitude of the input signal is set to 1 in the multiplier 4.
The processing result in the case of performing the calculation such as / 2 will be described with reference to FIG. FIG. 7A is a signal waveform diagram when 1-bit digital data supplied to the input terminal 2 of FIG. 1 is returned to an analog signal through an analog low-pass filter. FIG. 7B is a signal waveform diagram when the multi-bit digital data obtained by the calculation performed by the multiplier 4 is returned to an analog signal.
In this way, the amplitude of the analog audio signal is halved by the calculation by the multiplier 4.

Claims (5)

[Claims] 1. A digital signal processing method for performing signal processing including sigma delta modulation again on an input signal of a small number of bits obtained by sigma delta modulation, which outputs the minority bit input signal as it is. A digital signal processing method, wherein switching between a state and a state in which sigma-delta modulation is performed again and output is performed by gradually changing a through state and an operating state of the sigma-delta modulation processing performed again. 2. The raw output of the minority bit input signal and the output after the sigma-delta modulation are performed again,
2. The digital signal processing method according to claim 1, wherein switching is performed by gradually changing a gain of an n-th (n is 3 or more) filter for each filter. 3. An arithmetic means for performing arithmetic processing on a minority bit input signal obtained by sigma-delta modulation using a multi-bit signal, and a through state in which an output from this arithmetic means is input and the input signal is output as it is. And a sigma-delta modulating means capable of switching between an operating state in which sigma-delta modulation is performed again and outputting, and a control means for gradually changing the through state and the operating state of the sigma-delta modulating means. Digital signal processing device. 4. The sigma-delta modulation means is composed of n-th (n is 3 or more) filters, and the gain of each of these filters is gradually changed for each filter by the control means to bring about the through state. 4. The digital signal processing apparatus according to claim 3, wherein the sigma-delta modulation operating state is gradually switched and controlled. 5. Each of the filters of the sigma-delta modulation means includes a first variable gain amplifier that feeds back a signal through a delay device that delays an input signal, and a quantum of a quantizer that constitutes the sigma-delta modulation process. A second variable gain amplifier that feeds back the converted output and a third variable gain amplifier that supplies the signal that has passed through the delay device to the next stage, and these first, second, and third variable gain amplifiers are provided. _5. The digital signal processing device according to claim 4, wherein each of the variable coefficients k _n1 , k _n2 and k _n3 is made to satisfy the relationship of k _n1 = k _n3 (k _n2 −1) +1.