JP3290873B2 - 1-bit D / A converter and D / A converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a 1-bit D / A (digital / analog) converter and a D / A using the same.
1-bit D / A conversion for converting a 1-bit digital signal into an analog signal by adding a fixed DC offset value to an input multi-bit digital signal and then converting the 1-bit digital signal into an analog signal The present invention relates to an analog mute circuit of a D / A converter for obtaining an analog output by a device.

[0002]

In recent years, in the field of the D / A converter, the sampling frequency by the oversampling is set sufficiently higher than f _s the signal frequency band f _B, oversampling type high conversion accuracy at low conversion bit number is obtained D
/ A converters have been developed and put into practical use. In particular,
A D / A converter using ΣΔ modulation (sigma delta modulation) has a sufficient S / N at a relatively low oversampling ratio.
(Signal-to-noise ratio), it has recently become the mainstream of audio D / A converters.

FIG. 7A shows a general configuration of a D / A converter using ΣΔ modulation. D shown in FIG.
The / A converter includes a digital filter 61 for oversampling a multi-bit (multi-bit) digital data input sampled at a sampling frequency fs at a frequency fs of n times (n is an integer of 2 or more); An offset adding circuit 62 for adding a DC offset value of a fixed digital amount to a multi-bit digital signal input from the, a 、 Δ modulator 63 for converting the output of the offset adding circuit 62 into a 1-bit digital signal having amplitude information, A 1-bit D / A converter 10 provided to convert a 1-bit digital signal output from the ΣΔ modulator into a predetermined pulse signal format, and a pulse signal output from the 1-bit D / A converter 10 An analog filter 20 for converting the signal into a signal.

FIG. 7 (b) shows an example of the system configuration of the ΣΔ modulator 63 in FIG. 7 (a). Here, 70 is an addition circuit, 71 is a 1-bit quantizer, 72 is a loop filter, and 73 is a subtraction circuit.

When the transfer function H (z) of the loop filter of this system is represented by H (z) = 1− (1−z ⁻¹ ) ^q (1), a q-order ΣΔ modulator (q is 1 or more) (Integer) is represented by the following equation (2).

Y (z) = X (z) + (1-z ⁻¹ ) ^q E (z) (2) In the above equation (2), E (z) represents a quantization error.
(1-z ^-1) coefficients ^q are at stake, it is very small at low frequencies, if the oversampling ratio is sufficient S / N degradation due to quantization in the low frequency region is negligible be able to.

Since the D / A conversion output by the 1-bit quantizer is a binary value having no intermediate value, it is free from conversion errors caused by the non-linear characteristics of the elements and the analog circuit is very simple. There are great benefits.

The 1-bit D / A converter 10
As a signal format of the output signal of the above, in addition to NRZ (non-return-to-zero) and RZ (return-to-zero) as shown in FIGS. (Polar return to zero), but a PRZ output that is not affected by waveform distortion and has no DC offset problem is optimal.

As an example of the PRZ signal, IEEE J. OF SOLI
D-STATE CIRCUITS JUNE 1987 Vol.-SC- 22-No3 PETER
JANAUS et.al. “A CMOS Stereo 16bit D / A Converter
forDigital Audio "P390 ~ p394 and IEEE J.OF S
OLID-STATE CIRCUITS DECEMBER 1991 Vol.-SC-26-No.12
Renee G. Lerch et.al. “A Monolithic ΣΔ A / D
and D / A Converter with Filter for Broad-Band Spe
ech Coding ”.

Here, the reason why a DC offset is added to a digital signal before entering the ΣΔ modulator 63 as shown in FIG. 7A will be described. Digital ΣΔ modulator 6
Since 3 is a feedback circuit having a finite number of states, as shown in FIG. 11, a large beat (idling pattern) tends to appear particularly near the "0" offset.

Since the ま た Δ modulator 63 has a larger beat as the order is smaller, a second-order or third-order ΣΔ modulator always requires a DC offset addition to prevent a beat.
On the other hand, the D / A converter may generate an abnormal waveform when the operating voltage deviates during a transition period such as turning on / off the power supply. May be required.

FIG. 12 shows an example of a 1-bit D / A converter having a conventional analog mute circuit. In this 1-bit D / A converter diagram, reference numeral 11 denotes a cycle of 1-bit digital data having amplitude information obtained by converting an output obtained by adding a DC offset value of a constant digital amount to a multi-bit digital signal input by a ΣΔ modulator. type in T, wherein when the 1-bit digital data input is "1", the constant voltage V _H becomes predetermined time T ₁ within the period T, the remaining time T ₂ = T-T ₁ is a constant voltage V _L When the 1-bit digital data input is “0”, the period T
RZ of the type in which the constant voltage V _L is maintained over the entire
An RZ signal generation circuit for generating a signal.

In this embodiment, the RZ signal generation circuit 11
The 1-bit digital data input is a data input terminal D
, A clock signal CK is input to a clock input terminal, a first D-type flip-flop circuit 111, data of a data output terminal Q of the first D-type flip-flop circuit are input, and the clock signal CK is First gate circuit 112 input as gate inhibition control signal
And a first inverting the output signal of the first gate circuit.
And an inverter circuit 113.

When the 1-bit digital data input is "1", the constant voltage V _{L is} attained for the time T ₁ within the period T, and the constant voltage V _H is attained for the remaining time T ₂ . wherein when the 1-bit input digital data input is "0" is an RZ inversion signal generation circuit for generating an RZ inverted signal of the type to be the constant voltage V _H over a total time of the period T.

In this embodiment, the RZ inversion signal generation circuit 12
A second D-type flip-flop circuit 121 in which data obtained by inverting the 1-bit digital data input by an inverter circuit 124 is input to a data input terminal D and a clock signal is input to a clock input terminal; D
A second gate circuit 122 to which the data at the data output terminal Q of the flip-flop circuit is input and the clock signal is input as a gate inhibition control signal;
And a second inverter circuit 123 for inverting the output signal of the gate circuit.

Reference numeral 13 is used to connect the output terminal of the RZ signal generation circuit 11 and the output terminal of the RZ inversion signal generation circuit 12 to one end of each of resistance elements R1 and R2 having a resistance value r.
The other ends of the two resistance elements R1 and R2 are commonly connected to the inverting input terminal (-) of the operational amplifier 131, and the operational amplifier 1
31 between the output terminal and the inverting input terminal (-).
And an analog adding circuit for generating the PRZ signal having both polarities by analog adding the RZ signal and the RZ inverted signal.

Reference numeral 14 denotes an analog filter for outputting the PRZ signal generated by the analog adding circuit 13 as a 1-bit digital / analog conversion signal. Reference numeral 15 denotes an analog mute circuit provided on the output side of the analog filter, which is composed of two large-capacity DC component cutting capacitors C1 and C2 inserted in series in a signal path, and a series connection of the capacitors C1 and C2. A mute switch NPN transistor 151 connected between the connection node and the ground potential node and switch-controlled by a mute signal input MUTE; a resistance element 152 connected between the series connection node and the ground potential node; , And a resistor 153 inserted in series in the mute signal input path.
The mute signal MUTE is activated (“H” level) when the mute is on, and is in a high impedance state when the mute is off.

However, the analog mute circuit 15
Is a large capacitor C to prevent pop noise.
1. Since C2 is used, the cost is high, and it is difficult to configure it inside an IC (integrated circuit).

Therefore, in order to easily configure the analog mute circuit inside the IC, a mute control circuit 16 as shown in FIG. 13 can be considered. The 1-bit D / A converter shown in FIG.
Compared with the A converter, (1) the analog mute circuit 15 using two large-capacity capacitors C1 and C2 for cutting DC components is omitted, and (2) the mute signal input MUTE is activated. it allows the RZ signal output of the RZ signal generating circuit 11 is fixed to the constant voltage V _H or V _L, to fix the RZ inverted signal output of the RZ inversion signal generation circuit 12 to the constant voltage V _L or V _H The difference is that a mute control circuit 16 for performing the control is provided, and the other components are the same.

The mute control circuit 16 includes a third D-type flip-flop circuit 161 in which a mute signal input MUTE is input to a data input terminal D and a clock signal is input to a clock input terminal, and the third D-type flip-flop circuit 161. And a third inverter circuit 162 for inverting the output signal of the gate circuit and inputting it as a gate control signal to the three-input first gate circuit 112a and the second gate circuit 122a.

In the above 1-bit D / A converter, when a mute operation is performed (when mute is turned on), the output potential becomes the midpoint potential (VDD / 2). As shown in FIG. 7 (a), since the output obtained by adding a fixed digital amount of DC offset value to the multi-bit digital signal input is converted by ΣΔ modulation, the average of the output voltage at the time of mute off is obtained. The value deviates from the midpoint potential (VDD / 2) by the voltage Vos corresponding to the DC offset. Therefore, at the moment when the mute operation is turned on / off, a pop noise is generated due to a shift of the DC value by Vos.

[0022]

As described above, an output obtained by adding a DC offset value of a fixed digital amount to a multi-bit digital signal input is converted into 1-bit digital data having amplitude information converted by .SIGMA..DELTA. In the conventional analog mute circuit provided in the 1-bit D / A converter for converting to mute, the average value of the output voltage at the time of mute off is shifted from the midpoint voltage by the DC offset voltage Vos. There is a problem that a pop noise is generated when the DC value is shifted by the voltage Vos of the DC offset value at the moment of ON / OFF of the power supply.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. An analog mute which can prevent pop noise even at the moment of ON / OFF of a mute operation, can be easily integrated into an IC, and can be realized at low cost. It is an object to provide a 1-bit D / A converter having a circuit.

[0024]

SUMMARY OF THE INVENTION 1-bit D / A of the present invention
The converter receives, at a period T, 1-bit digital data having amplitude information obtained by converting a multi-bit digital signal input and a DC offset value of a constant digital amount and converting the output by ΣΔ modulation, and receiving the 1-bit digital data. when the input is "1", the constant voltage V _H becomes predetermined time T ₁ within the period T, the remaining time T ₂ = T-T ₁ is a constant voltage V _L becomes, the 1-bit digital data input is " At the time of "0", an RZ signal generating circuit for generating an RZ signal of a type having the constant voltage _VL over the entire time of the period T, and the 1-bit digital data input is "1".
In this case, the constant voltage _{VL is} attained for the time T ₁ within the period T, and the constant voltage V _{L is} applied for the remaining time T _2.
H , and when the 1-bit input digital data input is “0”, an RZ inversion signal generation circuit for generating an RZ inversion signal of a format that becomes the constant voltage V _H for the entire time of the cycle T; An analog addition circuit that generates an PRZ signal having both polarities by analog addition of the RZ inversion signal, and a PZ signal generated by the analog addition circuit.
An RZ signal output of the RZ signal generation circuit is fixed at the constant voltage _VH or _VL by activating an analog filter that outputs the RZ signal as a 1-bit digital / analog conversion signal and a mute signal input; The R
The RZ inversion signal output for generating the Z inversion signal is output to the constant voltage V _L.
Or a control circuit for controlling the voltage to be fixed at V _H , wherein the analog addition circuit activates the average value of the output potential and the mute signal input when the multi-bit digital signal input is “0” data. It is characterized in that the output potentials at the time of performing are equalized.

Further, the D / A converter of the present invention comprises an offset adding circuit for adding a DC offset value of a fixed digital amount to a multi-bit digital signal input, and an output of the offset adding circuit is a 1-bit signal having amplitude information. A ΣΔ modulator for converting the signal to a digital signal; and a 1-bit D / A converter provided for converting a 1-bit digital signal output from the ΣΔ modulator to an analog signal. The 1-bit D / A converter of the present invention is used as the converter.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an example of a PRZ type 1-bit D / A converter according to the first embodiment of the present invention.

This PRZ type 1-bit D / A converter is used as a 1-bit D / A converter 10 in the D / A converter described above with reference to FIG. 1-bit digital data having amplitude information obtained by converting the output obtained by adding a DC offset value of a fixed digital amount to the input by ΣΔ modulation is input, and
The signal is converted into an analog signal of RZ type.

The 1-bit D / A converter shown in FIG.
The circuit includes a signal generation circuit 11, an RZ inversion signal generation circuit 12, an analog addition circuit 13a, and a mute control circuit 16. When the 1-bit digital data is input at "1", the RZ signal generation circuit 11 outputs a signal for a predetermined time T within the period T when the 1-bit digital data input is "1".
_The constant voltage V _H becomes 1 and the remaining time T ₂ = T−T ₁
Is a constant voltage V _L , and when the 1-bit digital data input is “0”, generates an RZ signal of a type having a constant voltage V _L over the entire period T.

The RZ inversion signal generation circuit 12
When the bit digital data input is “1”, the constant voltage _{VL is} maintained for the time T ₁ within the period T, and the constant voltage V _H is maintained for the remaining time T ₂ , and the 1-bit input digital data input is “0”. In the case of (1), an RZ inversion signal of a type in which the constant voltage V _H is maintained over the entire period of the cycle T is generated.

The analog addition circuit 13a is provided with the RZ
A signal and an RZ inverted signal are added in an analog manner to generate a PRZ signal having both polarities. When the multi-bit digital signal input is “0” data, the average value of the output potential and the mute signal input MUTE are The configuration is such that the output potentials when activated are equal.

When the mute signal input is activated, the mute control circuit 16 fixes the RZ signal output of the RZ signal generation circuit 11 to a constant voltage V _H (or V _L ), and sets the RZ inversion signal generation 12 Is controlled so as to fix the RZ inverted signal output to a constant voltage V _L (or V _H ).

The RZ signal generation circuit 11, the RZ inversion signal generation circuit 12, the analog addition circuit 13a, and the mute control circuit 16 are configured as described below in this embodiment, respectively. It is not limited.

That is, the RZ signal generating circuit 11 is configured to input the 1-bit digital data to the data input terminal D and to input the clock signal to the clock input terminal.
And a three-input first gate circuit 112a to which the data of the data output terminal Q of the first D-type flip-flop circuit is input and the clock signal is input as a gate inhibition control signal. ,
And a first inverter circuit 113 for inverting the output signal of the first gate circuit.

The RZ inversion signal generation circuit 12
The 1-bit digital data input is an inverter circuit 1
7, the second D-type flip-flop circuit 121 in which the data inverted by the data input terminal 7 is input to the data input terminal D and the clock signal is input to the clock input terminal, and the data output terminal Q of the second D-type flip-flop circuit It comprises a three-input second gate circuit 122a to which data is input and the clock signal is input as a gate inhibition control signal, and a second inverter circuit 123 for inverting the output signal of the second gate circuit.

The analog addition circuit 13a has a function of R
An output terminal of the Z signal generation circuit 11 and an output terminal of the RZ inversion signal generation circuit 12 correspond to the first resistance element R1 respectively.
And the other end of the second resistance element R2, and the other end of the two resistance elements R1 and R2 are commonly connected to the inverting input terminal (-) of the operation multiplier 131. A resistor r0 is connected between the terminal and the inverting input terminal (-). In this case, the two resistive elements R1 and R2 are set so that the average value of the output potential when the multi-bit digital signal input is "0" data is equal to the output potential when the mute signal input is activated. A value has been set.

Further, the mute control circuit 16 includes a third D-type flip-flop circuit 161 having the mute signal input MUTE input to the data input terminal D and a clock signal input to the clock input terminal, Signal MUT obtained by inverting the output signal of D-type flip-flop circuit
And a third inverter circuit 162 for inputting Edn to the first gate circuit 112a and the second gate circuit 122a as a gate control signal.

FIG. 2 shows a PRZ type 1-bit D / A in FIG.
FIG. 6 is a timing waveform chart showing an operation example of the converter. next,
An operation example of the PRZ type 1-bit D / A converter in FIG. 1 will be described with reference to FIG.

The PRZ type 1-bit D / A converter shown in FIG. 1 outputs an RZ signal and its complementary signal (RZ inversion signal; RZ signal).
After generating cn) when generating a PRZ signal by analog addition, the RZ signal output of the RZ signal generation circuit 11 is fixed to a constant voltage V _H by the mute signal input MUTE is activated (mute ON), Further, the output of the RZ inversion signal generation circuit 12 is set to a constant voltage V _L
To secure (or to fix the RZ signal output of the RZ signal generator 11 to a constant voltage V _L, and deformed to secure the RZ inverted signal output of the RZ inversion signal generation circuit 12 to the constant voltage V _H ) To put the PRZ signal output in a mute state.

In this case, as described above with reference to FIG. 7A, since the digital data before being input to the ΣΔ modulator 63 is added with a DC offset in order to prevent beat generation, the RZ signal and the RZ signal are output. When the PRZ signal is generated by adding the inversion signal by the resistance addition type analog addition circuit 13a, the DC offset at the time of signal generation and the DC offset at the time of mute are previously set to the same value according to the ratio of resistance addition. This is set so that a pop sound does not occur when mute is turned on / off.

That is, the conventional 1-bit D shown in FIG.
In the analog adding circuit of the / A converter, two resistance elements having the same resistance value r are used. In this example, the value of the first resistance element R1 on the RZ signal side is r + Δr,
The value of the second resistance element R2 on the RZ inversion signal side is shifted to r−Δr.

FIGS. 3A and 3B show equivalent circuits of the analog adding circuit 13a in FIG. Next, FIG.
With reference to the equivalent circuits (a) and (b), the reason why the analog adder circuit 13a does not generate pop noise when mute is turned on / off will be described. Here, the 1-bit output is a rectangular wave that can take only two values, _VH and _VL , and an averaged analog output is obtained by passing this rectangular wave through a low-pass filter. In the following description, in order to facilitate understanding, a 1-bit output is considered as an average value that has passed through this low-pass filter.

Normally, the constant voltages V _H and V _L are V _H = E (power supply voltage) and V _L = 0 (ground potential; GND, respectively).
Level), and will be considered using the above values for simplicity. Also, for simplicity, T ₁
= T ₂ = T / 2.

The D / A conversion output by the DC offset is V
os, the D / A conversion output of the original digital data input that does not include the DC offset is V _D , the output of the RZ signal generation circuit 11 is e ₁ , and the output of the RZ inversion signal generation circuit 12 is e _{2. 1} and e ₂ are represented by the following equations.

E ₁ = (1/4) E + V _D + Vos (3) e ₂ = (3/4) E + V _D + Vos (4) Here, V _D normally does not include a DC component. It can be set to 0.

On the other hand, FIG. 3 (b) shows a circuit in which the complementary RZ signal generating circuit of FIG. 3 (a) is added to an analog circuit and replaced with a PRZ signal generator. Is r, e and r are expressed by the following equation (5).

E = [(e ₁ + e ₂ ) r + (e ₂ −e ₁ ) Δr] / 2r (5) r = [r ² −Δr ² ] / 2r (6) Equation (5) Substituting the previous equations (3) and (4) into V _D = 0, e = E / 2 + Vos + EΔr / 4r (7), and when mute is on, e ₁ and e ₂ are as described above. Is represented by the following equation (8).

E ₁ = E e ₂ = 0 (8) When the above equation (8) is substituted into the previous equation (5), e = E / 2−EΔr / 2r (9), and the mute is turned on. In order to avoid popping noise due to DC offset at / off, the right sides of the above equations (7) and (9) need to be equal. From this, Δr becomes Δr = − (4Vos / 3E) r (10) Next, when mute is on and e ₁ = 0 e ₂ = E (11), Δr = (4 Vos / E) r (12)

That is, Δr is calculated by the equation (10) or (12)
By setting the value of the expression, the pop noise which has conventionally been a problem is eliminated, and a high-quality mute circuit can be realized in a form that can be easily integrated into an IC.

FIGS. 4A and 4B show the PRZ of FIG.
13 shows another example of a type 1-bit D / A converter. FIG.
The PRZ type 1-bit D / A converter shown in (a) differs from the PRZ type 1-bit D / A converter shown in FIG. 1 in the RZ signal generation circuit 11a and the RZ inversion signal generation circuit 12a. Are the same, and are denoted by the same reference numerals as in FIG.

The RZ signal generation circuit 11a is different from the RZ signal generation circuit 11 shown in FIG. 1 in that a two-input first gate circuit 112 is used instead of the first gate circuit 112a.
And a first OR circuit 114 for performing a logical OR of the output signal of the first gate circuit 112 and the output signal MUTEdn of the mute control circuit 16 and inputting the logical sum to the first inverter circuit 113 is added. And the other parts are the same.

The RZ inversion signal generation circuit 12a
Is different from the RZ inversion signal generating circuit 12 shown in FIG. 1 in that a two-input second
A second OR circuit which takes the logical sum of the output signal of the second gate circuit 122 and the output signal MUTEdn of the mute control circuit 16 and inputs the result to the second inverter circuit 123 The difference is that the reference numeral 124 is added, and the other components are the same.

In the PRZ type 1-bit D / A converter of FIG. 4A having the above-described configuration, the same effect is obtained by basically the same operation as that of the PRZ type 1-bit D / A converter shown in FIG. Is obtained.

FIG. 4B shows the PRZ type 1 bit D / D
An example is shown in which an analog filter (20 in FIG. 7) for converting a PRZ signal into an analog signal and outputting the analog signal is incorporated in the analog addition circuit 13a of the A converter.

In FIG. 4B, reference numeral 201 denotes a secondary filter comprising a group of CRs to which the PRZ signals generated by the resistance elements R1 and R2 for analog addition are input. Reference numeral 131 denotes an operational amplifier in which the output signal of the primary filter is input to an inverting input terminal (-), and the non-inverting input terminal (+) is grounded.
0 is a resistance element inserted between the output terminal of the operational amplifier and the inverting input terminal (-), 202 is a capacitance element connected in parallel to the resistance element, and these form a third-order filter. .

FIG. 5 shows an example of a modified PRZ type 1-bit D / A converter according to the second embodiment of the present invention, and FIG. 6 shows a timing waveform of the operation example.
The modified PRZ type 1-bit D / A converter shown in FIG.
The delay circuit 17 further delays one of the RZ signal and the RZ inverted signal by k times (k is an integer of 1 or more) of the period T, as compared with the PRZ type 1-bit D / A converter shown in FIG. The modified PRZ signal is generated by the analog addition circuit 13a.

In this embodiment, the third D-type flip-flop circuit 17 in which the clock signal is supplied to the clock input terminal is used as the delay circuit 17 and the second D-type flip-flop circuit 121 in the RZ inversion signal generation circuit 12. One of the second D-type flip-flop circuits 121
The bit digital data input is connected to the clock signal CK (D
/ A conversion clock).

In the modified PRZ type 1-bit D / A converter having the above configuration, the PRZ type 1-bit D / A converter shown in FIG.
Basically the same operation as that of the A converter provides the same effect.

[0058]

As described above, according to the present invention, there is provided an analog mute circuit which can prevent pop noise even at the moment of ON / OFF of the mute operation, can be easily integrated into an IC, and can be realized at low cost. A bit D / A converter can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a PRZ type 1-bit D / A converter according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation example of the PRZ type 1-bit D / A converter in FIG.

FIG. 3 is a circuit diagram showing an equivalent circuit of the analog adding circuit in FIG. 1;

FIG. 4 is a circuit diagram showing another example of the PRZ type 1-bit D / A converter in FIG. 1;

FIG. 5 is a circuit diagram showing an example of a modified PRZ type 1-bit D / A converter according to a second embodiment of the present invention.

6 is a waveform chart showing an operation example of the modified PRZ type 1-bit D / A converter in FIG.

FIG. 7 is a circuit diagram showing an example of a general configuration of a D / A converter using a ΣΔ modulator and an example of a system configuration of the ΣΔ modulator.

FIG. 8 is a waveform chart showing an example of an NRZ output waveform.

FIG. 9 is a waveform chart showing an example of an RZ output waveform.

FIG. 10 is a waveform chart showing an example of a PRZ output waveform.

FIG. 11 is a diagram showing a relationship between an input DC offset of the ΣΔ modulator and a beat (idling pattern).

FIG. 12 is a circuit diagram showing an example of a 1-bit D / A converter including a conventional analog mute circuit.

FIG. 13 is a circuit diagram showing a 1-bit D / A converter including an analog mute circuit that has been conventionally considered.

[Explanation of symbols]

 10 1-bit D / A converter 11, 11a RZ signal generation circuit 111 first D-type flip-flop circuit 112 first gate circuit 113 first inverter circuit 12, 12a RZ inversion signal generation circuit, 121: second D-type flip-flop circuit, 122: second gate circuit, 123: second inverter circuit, 13a: analog addition circuit, 131: operational amplifier, R1, R2: resistance element Reference numeral 16: Mute control circuit 161: Third D-type flip-flop circuit 162: Third inverter circuit 17: Inverter circuit 18: Fourth D-type flip-flop circuit (delay circuit) 20: Analog filter , 61: Digital filter, 62: DC offset addition circuit, 63: ΣΔ modulator.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 3/02

Claims (4)

(57) [Claims] An output obtained by adding a DC offset value of a fixed digital amount to a multi-bit digital signal input is input at a period T as 1-bit digital data having amplitude information converted by ΣΔ modulation. When the data input is “1”, a fixed time T ₁ within the cycle T
By a constant voltage V _H, and the remainder of the time T ₂ = T-T ₁ is a constant voltage V _L becomes, when said 1-bit digital data input is "0", and the constant voltage V _L over the entire period of the period T An RZ signal generating circuit for generating an RZ signal of the form: when the 1-bit digital data input is "1",
The constant voltage V _L becomes only the time T ₁ within the period T, the rest of the time T ₂ are the constant voltage V _H, and the
Wherein 1 when the bit input digital data input is "0", and RZ inversion signal generation circuit for generating an RZ inverted signal of the type to be the constant voltage V _H over a total time of the period T, the RZ signal and RZ inverted signal An analog adding circuit for generating a PRZ signal having both polarities by analog adding, an analog filter for outputting the PRZ signal generated by the analog adding circuit as a 1-bit digital / analog conversion signal, and a mute signal input being activated By converting the RZ signal output of the RZ signal generation circuit to the constant voltage V _H or V
Is fixed to _L, and RZ inverted signal output of the RZ inversion signal generating circuit includes a mute control circuit for controlling so as to fix to the constant voltage V _L or V _H, the analog adder circuit, multi-bit digital signal A 1-bit D / A converter characterized in that the average value of the output potential when the input is "0" data is equal to the output potential when the mute signal input is activated. 2. The 1-bit D / A converter according to claim 1, wherein one of the RZ signal and the RZ inversion signal is k of the period T (k is an integer of 1 or more).
A 1-bit D / A converter comprising a delay circuit for delaying by a factor of two, wherein the analog adder circuit generates a modified PRZ signal. 3. The 1-bit D / A according to claim 1, wherein:
In the converter, the analog addition circuit connects an output terminal of the RZ signal generation circuit and an output terminal of the RZ inversion signal generation circuit to respective one ends of a first resistance element and a second resistance element, respectively, The other ends of the two resistance elements are connected in common, and the average value of the output potential when the multi-bit digital signal input is "0" data and the output potential when the mute signal input is activated Wherein the values of the two resistive elements are set so that the values are equal to each other. 4. An offset addition circuit for adding a DC offset value of a fixed digital amount to a multi-bit digital signal input, a ΣΔ modulator for converting an output of the offset addition circuit into a 1-bit digital signal having amplitude information, 2. The apparatus according to claim 1, which is provided for converting a 1-bit digital signal output from the 変 調 Δ modulator into a predetermined analog signal.
A D / A converter comprising: the 1-bit D / A converter according to any one of claims 1 to 3.