SU1524067A1 - Device for median filtering of two-dimensional arrays - Google Patents

Abstract

The invention relates to computing and can be used in the processing of two-dimensional data arrays. The aim of the invention is to improve the speed of performance. The device contains 1-3 memory blocks, counters 4-8, adders 9.10, registers 11-16, comparison block 17, decoder 18, switches 19.20 clock generator 21, frequency divider 22, shift register 23, triggers 24 -26, one-shot 27.28 group of elements AND 29, elements AND 30-33, elements OR 34-37, element NOT 38, delay element 39. 1 ill.

Description

ff

ate

The invention relates to computing and is intended for use in specialized computing devices when processing two-dimensional data arrays, for example, in image processing.

The aim of the invention is to improve the speed,

The drawing shows the functional diagram of the device

The device contains memory blocks 1–3, counters 4–8, adders 9 and 10, registers 11–16, block 17 as compared with NIN, decoder 18, switches 19 and 20, generator 21 clock pulses, frequency divider 22, shift register 23 , triggers 24-26, one-shot 27 and 28, group-elements AND 29, elements AND 30-33, element OR 34-37, element KE 38, delay element 39, v input 40 of the initial installation, start input 41, output 42 terminating operation of the device, output 43 of the indication of the results of the first sampling, information output 44 of the device.

The initial installation input 40 is connected to the reset inputs of counters 4-8, register 13 and to the first inputs of the OR 34, 36 elements. The output of the pulse generator 21 is connected to the synchronization input of the shift register 23 and the input of the frequency divider 22, the output of which is connected to the trigger synchronous input - pa 24 and the first input of the element I 30, the second input of which is connected to the output of the trigger 24. The information outputs of the counter 5 are connected to the address inputs of memory blocks 1 and 2, the outputs of which are connected respectively to the first groups of inputs of adders 9 and 10, the second groups in the moves of which are connected respectively with the information outputs of counters 7 and 8. The outputs of the sums of adders 9 and 10 are connected via registers 11 and 12, respectively, with the groups of high and low bits of the address input of the memory block 3.

The outputs of the sign bits of the adders 9 and 10 are connected from the first to the fourth inputs of the OR element 35. The output of the OR element 35 is connected via triggers 25 and 26 to the first input of the OR element 37, the output of which is connected to the control input of the switch 19. The output of the switch 20 is connected to the second input element OR 37. Block outputs

3 memory through a register 16 is connected to the first group of inputs of the switch 19, the second group of inputs of which is connected to the log level "O. The outputs of the switch 19 are connected to the first group of inputs of the comparison block 17 and the information inputs of the register 15, the outputs of which are the outputs 44 of the device and connected to the second rfiyn unit of the block 17 of the comparison; the transfer output of the counter 5 is connected via the one-shot 27 to the counting input of the counter 4 and through the element NOT 38 to the third input of the element 30, the output of which is connected to the information input of the register 23 sd Wig, trigger recording inputs 25, registers 1 1 and 12 and counting input of counter 5. Transfer output of counter 4 is connected to counting input of counter 8 and first inputs of elements 32 and 33 “Transfer output of counter 8 is connected to counting input of counter 7. Transfer output the counter 7 is the output 42 of the operation of the device and is connected to the reset input of the trigger 24, the information input of which is connected to the start input 41. The information outputs of the counter 6 are connected to the information inputs of the register 13 and the control inputs of the switch 20, the information inputs of which are connected to the outputs of the register 14. The outputs of the register 13 are connected to the inputs of the decoder 18, the outputs of which are connected to the first inputs of elements And group 29, the outputs of which are connected to information inputs of the register 14. The transfer output of the counter 6 through the one-shot 28 is connected to the second inputs of the elements And group 29, the second input element And 32 and through the element 39 of the delay with the second inputs of the element in OR 34 and AND 33, the output of which is connected to the second input of the element

OR 36. The output of the comparator block 17 is connected to the first input of the element AND 31, the output of which is connected to the write inputs of registers 13 and 15. The reset input of the register 15 is connected to the output of the OR element 34. The second output of the shift register 23 is connected to the write inputs of the trigger 26 and the register 16. The fourth output of the shift register 23 is connected to the counting input of the counter 6 and the second input of the And 31 element. The output of the And 32 element is the output 43 of the device.

The device is intended for median filtering of two-dimensional data arrays of size mxn, m is the number of rows, n is the number of columns, where m 2, P, S are positive integers. The filter aperture can be arbitrary. The number of points entering the aperture is K (K is odd).

The algorithm of the device operation is as follows:

Among the elements of the array, the entrance to the aperture is the median and it replaces the center point of the aperture. Thereafter, the aperture shifts and the new central point is replaced with a median. Aperture shift direction: from left to right and from top to bottom.

Counters 5 and 6 are counters with recalculation K, counter 4 - from 20

K-t-l

scaling ---, counter 7 is a binary counter of size P, counter 8 is a binary counter of size S.

The size of memory blocks 1 and 2 is determined by the number K and the shape of the aperture. The size of block 3 of memory, block 17 of comparison, switch 19 and registers 15 and 16 is determined by the width of the data being processed. The register width 13 is equal to the counter 6 counter. The number of outputs of the decoder 18, the elements of AND group 29, the register resolution 14 and the number of inputs of the switch 20 are equal to K.

The initial array is stored in block 3 of memory. We number the points included in the aperture from O to K. Then in block I of memory at the i-th address of the store

thirty

35

SRI or negative result, i.e. the output of the aperture for the size of the original array.

The device works as follows.

On a signal from the initial installation, the AOs are reset to O counters 4-8 and registers 13-15,

A pulse generator 21 forms a pulse train whose frequency is divided into two by a divider 22 frequencies. According to the start signal at the input 41, the trigger 24 is set to one state by the leading edge of the pulse coming from the divider 22. The single state of the trigger 24 permits the passage of synchronization pulses to the output of the And 30 element.

The pulses arriving at the information input of the shift register 23 are shifted therein by signals from the pulse generator 21. To synchronize device nodes, clock pulses are used that are taken from the second and fourth outputs of the register 23

The device has a conveyor mode of operation.

In the first clock cycle, by the first clock pulse, one is added to the contents of counter 5, the upper and lower bits of the zero point address of the aperture, which are obtained by adding the address of the central point, which is stored in counters 7 and 8, and offsets The offset of the i-th point of the aperture from 40 blocks 1 and 2 of memory (offset

by rows and offset by columns). If the current point in the aperture goes beyond the bounds of the original array, then at least in one significant digit of de dg adders 9 or 10 there will be a signal

relative to the center point of the aperture in rows, and in block 2 of memory in columns. The offset is a signed number in the additional code, with two digits for the sign.

Counters 7 and 8 contain the current address of the center point of the aperture (row number and column number, respectively). Summation of the current address of the center point with offset in adders 9 and 10 allows one to obtain absolute addresses of points entering the aperture for different values of the address of the center point. At the same time, the presence of at least one 1 at the output of the sign bits of the adders 9 and 10 (the sign is represented by two bits) indicates the overflow

five

0

five

0

five

SRI or negative result, i.e. the output of the aperture of the size of the original array.

The device works as follows.

The signal from the initial installation of an AO is reset to O, counters 4-8 and registers 13-15,

A pulse generator 21 forms a pulse train whose frequency is divided into two by a divider 22 frequencies. According to the start signal at the input 41, the trigger 24 is set to one state by the leading edge of the pulse coming from the divider 22. The single state of the trigger 24 permits the passage of synchronization pulses to the output element I 30.

The pulses arriving at the information input of the shift register 23 are shifted therein by signals from the pulse generator 21. To synchronize device nodes, clock pulses taken from the second and fourth outputs of shift register 23 are used.

The device has a conveyor mode of operation.

In the first clock cycle, by the first clock pulse, one is added to the contents of counter 5, the upper and lower bits of the zero point address of the aperture, which are obtained by adding the address of the central point, which is stored in counters 7 and 8, and offsets read blocks 1 and 2 of memory (offset

by rows and offset by columns). If the current point in the aperture goes beyond the bounds of the original array, then at least one significant digit of adders 9 or 10 will be a signal

log 1, which, having passed through the element OR 35, is brought into the trigger 25 by the first clock pulse. At the generated address from block 3 of memory, the corresponding number is counted and entered into register 16 by the first clock pulse from the second output of shift register 23, and the trigger 26 is overwritten with the contents of trigger 25 °. In the same clock cycle, the address of the first aperture point is entered into registers 11 and 12 second impulse. The first number passes through the switch 19 and is compared with the contents (well

/ 1524067

left) of the register 15. (If the zero point of the aperture extends beyond the rpaHHi ii of the original array, then the trigger 26 will be assigned a log. M, which will switch the commu

so that its outputs will receive a log from the second inputs, and this - excludes points from the analysis when the aperture goes beyond the boundaries of the original array). If the first Q number on the output of the switch 19 is greater than the content of the 1st register 15, the comparison unit 17 will form at its output a unit level that will allow

Single-shot 28 4 is output short nMnyjifjC. The number of the largest number from register 13 is fed to the inputs of the decoder 18, at the iM output of which a log level appears, provided that i is the number} of the loop has the largest value that permits the pulse from the one-shot 28 output through the i-th element of group 29 and ensures that the i-ro trigger of register 14 is set to one, In the next passes of the aperture, the 1st element in the definition

passing through the element AND 31 first (the maximum number 5 will not be

pulse from the fourth shift register 23, which, arriving at the input of the record of register 15, will provide a record of a larger number in register 15. If the number is less than or equal to the register 15, the output of block 17 cpaBiieHiin is low and in register 15 will remain the previous number .

15 of the same tick, the address of the second aperture point is entered in registers 11 and 12, and the value of the first aperture point is recorded in register 16

Simultaneously with entering the current maximum number into the register 15, its number in the aperture is entered into the register 13 by the pulse from the output of the AND 31 element. In the subsequent clock cycles, the oficTBo works in a similar way. On the Kth pulse, the address of the last (Kth) point of the aperture is entered into registers 11 and 12, and a transfer pulse is generated at the transfer output of counter 5. A single-vibrator 27 generates a pulse, the duration of which is chosen so as to ensure reliable elimination of one clock pulse. The signal from the output of one-vibrator 27 goes through the element NO 38 to the third input of the element 30 and provides the exception of the next clock pulse about

On the Kth pulse from the second output of the shift register 23, the value of the () th point of the aperture is entered into the register 16. On the leading edge of the K-th pulse from the fourth output of the shift register 23, the (K-1) -th number is entered in register 45 (provided that it is greater than the current value of register 15).

Thus, in register 15 there is the largest number in the aperture, and in register 13 its order number in the aperture. At the transfer output of counter 6, a transfer pulse is formed, on the leading edge of which

five

0

five

d

0

five

0

five

because when the counter 6 has the value of i, the switch 20 will skip output 1 of the i-ro trigger register 14 and through the element OR 37 switch the switch 19 to the inputs to which zeros are sent,

The pulse from the output of the one-shot 28 passes the delay element 39 and the OR element 34 and resets the register 15. In the second pick, the second largest number is determined,

K + 1 In the i-th cycle ü: a}, the output of the counter of counter 4, a signal is generated that enters the first inputs of the elements 32 and 33.

In register 15, the median is selected. The impulse from the output of the 28 detector passes through the element AND 32 and output 43 and enables the sampling of the first result "After the delay by the delay element 39 for a time sufficient to clear the result from the device outputs 44. the register 15 is reset, the pulse delayed by the delay element 39 passes also through the element AND 33 {the second input of which receives the permission from the transfer output of the counter 4) and the element OR 36 and resets the register 15. The pulse from the output of the counter 4 is added to the content of the counter 8, that is, The address of the next center point and similarly determined nto median, etc.

After testing the last point of the array at the output of the transfer of the counter 7, a signal is generated that resets the trigger 24 and arrives at the output 42 of the operation of the device.

Formula n

9 o b

15

rete n i

A device for median filtering of two-dimensional arrays, containing four counters, two one-vibrators, three memory blocks, a delay element, three registers, a NOT element, two adders, a first trigger, two switches, a comparison block, a group of AND elements, a decoder, four AND elements, three the SHS element, the clock pulse generator, the transfer output of the first counter through the first one-oscillator is connected to the first inputs of the AND elements of the group, to the first input of the first element AND, and through the delay element to the first input of the first element OR, you the first and second memory blocks are connected to the first inputs of the first and second adders, respectively, the outputs of the sign bits of which are connected to the inputs of the second OR element, the output of the first

the switch is connected to the info-input 25 of the initial installation of which

The first input of the first register and the first input of the comparison unit, the Output More of which is connected to the first input of the second element I, the output of which is connected to the control inputs of the record-30, reading the second and first registers, the output of the first register is connected to the second input of the comparison unit and is informational the output of the device, the output of the second register through the right element And the outputs of the fourth

45

the decoder is connected to the second inputs of elements AND groups, the outputs of which are connected to the information inputs of the third register, the output of which is connected to the information input of the second-40 switch, the output of the second counter is connected to the input of the second single-vibrator, the information outputs of the third and fourth counters are connected to the second inputs, the transfer output of the fourth counter is connected to the counting input of the third counter, the output of the element is NOT connected to the first input of the third element, And the input of the setup of the third register is connected with the output of the second OR element, the first input of which is connected to the installation inputs of the second register, from the first to the fourth counters, to the second input of the first OR element and is the input of the initial installation of the device, characterized by that.

and the fifth registers are connected to the address inputs of the third memory block, the output of which is connected to the information input of the PiecToro register, the output of which is connected to the information input of the first switch, the output of the second digit of the shift register is connected to the synchronization input of the sixth register and with the zero input of the third trigger, the direct output of which is connected to the first input of the third OR element, the output of which is connected to the control input of the first switch, the output of the last bit is 50 and the shift register is connected to the second input the second element And the counting input of the first counter, the output of which is connected to the information input of the second register and the control input of the second switch, the output of which is connected to the second input of the third element OR, the transfer output of the third counter is connected to the zero input of the first trigger, and b5

that, in order to increase speed, a fifth counter was inserted in it.

152DP67

ten

three registers, a shift register, two triggers, the fourth element OR, and a frequency divider whose input is connected to the shift control input of the shift register and connected to the output of the clock generator, and the output connected to the second input of the third And element and to the synchronization input of the first trigger, input set to 1 which is the start input of the device, the direct output of the first trigger is connected to the third input of the third element AND, the output of which is connected to the information input of the shift register, with zero input of the second trigger a, with the synchronization inputs of the fourth and fifth registers and with the counting input of the second counter, the output of which is connected to the address inputs of the first and second memory blocks, the output of the second one-oscillator is connected to the input of the NOT element and with the counting input of the fifth counter,

connected to the input of the initial installation of the device, and the output is connected to the counting input of the fourth counter, to the second input of the first element AND and to the first input of the fourth element AND, the output of which is connected to the second input of the second OR element, the output of the first one-vibrator through the delay element connected to the second input even

and the fifth registers are connected to the address inputs of the third memory block, the output of which is connected to the information input of the PiecToro register, the output of which is connected to the information input of the first switch, the output of the second digit of the shift register is connected to the synchronization input of the sixth register and with the zero input of the third trigger, the direct output of which is connected to the first input of the third OR element, the output of which is connected to the control input of the first switch, the output of the last bit of the shift register is connected to the second input the second AND gate and to the counting input of the first counter, whose output is connected to the data input of the second register and a control input of the second switch, whose output is connected to the second input of the third OR gate, the third transfer counter output is connected to the zero input of the first flip-flop, and

1 152406712

The output of the end of the first sample is the output of the transform, the output of the indication of the result element I.

Claims (1)

Claim A device for median filtering of two-dimensional arrays containing four counters, two one-shots, three memory blocks, a delay element, three registers, a NOT element, two adders, a first trigger, two switches, a comparison unit, an element group And, a decoder, four elements And, three an OR element, a clock pulse generator, the transfer output of the first counter through the first one-shot being connected to the first inputs of the 15 elements of the And group, with the first input of the first And element and through the delay element with the first input of the first OR element, output The first and second memory blocks are connected to the first 20 inputs of the first and second adders, respectively, the outputs of the sign bits of which are connected to the inputs of the second OR element, the output of the first switch is connected to the information-25th input of the first register and to the first input of the comparison unit, the output of which is larger connected to the first input of the second AND element, the output of which is connected to the recording control inputs by reading the second and first registers, the output of the first register is connected to the second input of the comparison unit and is in device output, the second register output through 35 decoder is connected to the second inputs of elements And groups, the outputs of which are connected to the information inputs of the third register, the output of which is connected to the information input of the second 40th switch, the output of the second counter is connected to the input of the second one-shot, information outputs the third and fourth counters are connected to the second inputs, the output of the nose of the fourth counter is connected to the counting input of the third counter, the output of the element is NOT connected to the first input of the third AND element, the input of the third register is connected to the 50 output of the second OR element, the first input of which is connected to the inputs of the second register, from the first to the fourth counters, with the second input of the first OR element and is the 55 input of the initial installation of the device, characterized in that , in order to improve performance, it introduced a fifth counter, three registers, a shift register, two triggers, a fourth OR element and a frequency divider, the input of which is connected to the shift control input of the shift register and connected to the output clock generator, and the output is connected to the second input of the third AND element and to the synchronization input of the first trigger, the installation input of which is the device start input, the direct output of the first trigger is connected to the third input of the third AND element, the output of which is connected to the register information input shift, with a zero input of the second trigger, with synchronization inputs of the fourth and fifth registers and with a counting input of the second counter, the output of which is connected to the address inputs of the first and second memory blocks, the output the second one-shot is connected to the input of the element NOT and to the counting input of the fifth counter, the input of the initial setting of which is connected to the input of the initial installation of the device, and the output is connected to the counting input of the fourth counter, with the second input of the first element And and the first input of the fourth element And, the output of which connected to the second input of the second OR element, the output of the first one-shot through the delay element is connected to the second input of the fourth AND element, the outputs of the fourth and fifth registers are connected to the address inputs of the third memory block, the output of which is connected to the information input of the sixth register, the output of which is connected to the information input of the first switch, the output of the second digit of the shift register is connected to the synchronization input of the sixth register and with the zero input of the third trigger, the direct output of which is connected to the first input of the third element OR the output of which is connected to the control input of the first switch, the output of the last digit of the shift register is connected to the second input of the second element And to the counting input of the first counter, turn is connected to the data input of the second register and a control input of the second switch, the output of which is connected to the second input of the third OR gate, transfer output of the third counter is connected to the zero input of the first flip-flop, and YaV ¹¹ 1524067 12 wish to set up the output operation Device for closure is the first sample is the output of the device, the output of the indication of the result element I.