JPH02206864A - Program debugging system - Google Patents

Abstract

PURPOSE:To execute the program debugging of a controller specified in an early stage by providing a register for storing so that the controller where writing violation to a common memory is occurred can be read out with a CPU. CONSTITUTION:When the state of a signal on a signal line 212 is '1', the state '1' of the signal is outputted to the signal line 216 to close an AND gate 217, and the passing of WE signal is obstructed on the signal line 222, and write-in to the common memory 205 is prevented. Simultaneously with this, the state '1' of the signal on the signal line 216 becomes a trigger signal to store the input information of a protect register 224, and the state of signal input information is stored. The storage information of the register 224 is read out by an abnormality processing program, and read in the CPU 201 by the signal line 225. Thus, it can be known in which controller the writing violation due to the program debugging is occurred, and accordingly, the debugging of the program of the controller specified in the early stage can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to debugging a program for a microprocessor, and more particularly to a program debugging method for a processing device that operates a plurality of control devices via a common memory.

(Prior art) Conventionally, when a control device writes to a memory address where writing is prohibited, this write violation is detected and the
Although it is possible to report the occurrence of an interrupt violation to the CPU,
No further action was taken.

(Problem to be Solved by the Invention) In the conventional write violation detection method described above, the occurrence of a write violation within the processing device can be recognized by the CPU, which plays a central role in the processing device. However, since it is not possible to specify a device consisting of a control device that operates according to a program with a large number of microprocessors at its core, this method has the disadvantage that it requires an extremely long debugging time.

An object of the present invention is to provide a processing device in which a plurality of control devices operated by a program using a microprocessor as the core are operated via a common memory, in which a writing violation is committed to the common memory and the control device is stored as write identity information. ,and,
It is an object of the present invention to provide a program debugging system configured to eliminate the above-mentioned drawbacks by reading out the above-mentioned stored contents by a CPU using a register circuit, and to easily identify write violations.

(Means for Solving Problem 111) A program debugging method according to the present invention is configured to include a common memory, a write protect memory, a conflict prevention means, and a register circuit.

The common memory is for exchanging information between devices.

The write protect memory is for storing write prohibition information in block units of the common memory for each control device based on instructions from the CPU.

The contention prevention means is for executing memory accesses in an orderly manner so that the common memory is not accessed simultaneously by each control device.

The register circuit is for storing a controller in which a write violation to the common memory has occurred so that it can be read by the CPUK.

(Example) Next, one embodiment of the present invention will be explained with reference to the drawings.

For ease of explanation, the present invention is configured with a CPU, a disk controller, and a common memory with a capacity of 1M words, and has a write inhibit function for each IK word memory block of the common memory. be.

FIG. 1 is a block diagram showing the principle of a memory write prevention circuit using the program debugging method of the present invention.

In FIG. 1, 101 is a CPU, 102 is a 1M word common memory, and 105 is a protect memory for storing 1 bit of write-inhibited information for each IK word of the common memory 102. In FIG. In this embodiment, the protect memory 10δ has a capacity of 1-bit XIK word.

CPolol stores important system information that application programs must not write at the beginning of processing. Common memo! Corresponding to each memory block 7102, when writing to the memory address of the protect memory 103 is prohibited, K sends information s11 to the protect memory 105 via the write control signal line 104, and when it is permitted, the write control signal line 104 Information via %OI
is sent to the protected memory 103.

When the information on the signal line 104 is %OI, data can be stored in the protect memory 103. At this time, in order to indicate the address in the IK word of the protect memory 105, the address 21@-2 on the signal line 105 is
II (hereinafter referred to as A) is used to specify the address.

When the CPU 101 starts a processing operation and causes the common memory 102 to perform a write operation, the address signal line 10°7
When outputting address information to (All -A18),
Among the signals @106, the upper one (A 10 A11l)
An address indicating this is input to the protect memory 10B via the signal line 105. Information in the protect memory 10fS stored at the address indicated by the signal line 105 is output onto the signal line 107 as signal line protect information.

As a result, if the state on the signal line 107 is strange βOI, it indicates a write-in permission state, and the write gate 108 is involved. Thereafter, a write signal output from the CPU 101 via the signal line 109 is input onto the common memory 102, and
The write information sent via the signal line 110 is stored at the address indicated by 6, and the normal operation ends.

Further, when the state on the signal line 107 is %11, writing is prohibited, the write gate 108 prohibits the output of the signal on the signal line 109, and the write instruction does not reach the common memory 102, and at the same time, the signal line 107 CPUl0I via
A memory write violation is reported.

FIG. 2 is a block diagram showing an embodiment of the program debugging method shown in FIG. 1.

In FIG. 2, 201 is a CPU, 203' to 204 are each protected memory, 205 is a common memory, and 20
6 is a competition circuit, 208 is a disk control circuit, 21! ,2
17 and 231 are AND gates, 216 and 218 respectively
, 221 are OR gates, 215, 218, 22
1 is an OR gate and a 224-digit protect register, respectively.

In FIG. 2, the CPU 201 uses the protect memory control signal line 202 to start the processing operation. 17.CP
A write permission or prohibition signal is sent to the protect memory 203 of U201 and the protect memory 204 of the disk control device 208.

If writing is permitted, the state %QI is written to an address corresponding to a memory block of IK words in the common memory 205. On the other hand, if writing is prohibited, the state tl is applied to the address.
Write I. The addressing of data written to the protect memories 203 and 209 was explained in FIG.
It is omitted here.

Next button, the processing device is in operation,! 7. When the CPU 201 writes to the common memory 205, when it issues a memory access request signal to the competition circuit 20B via the signal 1 gland 207, the competition circuit 20B detects that another control device is using the common memory 205. If there is, an access permission signal is returned to the CPU 201 via the signal line 209 after waiting for the end of use, and if it is not in use, the access permission signal is immediately sent to the CPU 201 via the signal line 209.
A memory access permission signal is returned to U 201.

Upon receiving the access permission signal, the CPU 201 outputs address information AI At- to the signal line 201. Among the address information on the signal line 210, upper address information AI
OA! is input to the protect memory 205 from the signal line 211, and the information in the protect memory 20B stored at the address indicated by the address information on the signal line 211 is transferred to the protect memory 20! of the CPU 201. It is output to the output signal line 212 of i.

The state of the signal on the signal line 212 is determined by the signal on the signal line 2 through the AND gate 213 according to the permission state %1# of the signal line 20B.
14. The output of the AND gate 21s is further passed through the OR gate 215 to an output signal +1lI2f
6 is output.

Therefore, when the state of the signal on the signal line 212 is 101, it indicates write permission, so in this case, the signal on the signal line 216 is also in the state %Ol, and the AND gate 217 for writing is opened.

The address information on signal line 210 is output through OR gate 218 onto OR gate 216, and the address information on signal line 2
19 is input. After this, from the CPU 201, the signal line 2
Memory write signal (hereinafter referred to as WE) output on 2G
It is called. ) is the OR gate 221 and signal line 2 in the WE diagram.
This is the WE large input that is input to the AND gate 217 through 22 and 22. Since the AND gate 217 is open depending on the state of the signal on the signal line 216, the W of the common memory 206 is
It is transmitted to the E input signal line 225.

Although not shown in FIG. 1, the information on the data signal line is written to the designated address of the common memory 205, and the operation ends normally.

Conversely, when the state of the signal on the signal line 212 is %11, it indicates that writing is prohibited.
The state 11# of the signal on 2 is output on the signal line 21B,
AND gate 217 is closed to prevent the WE multiplication signal on signal lI 222 from passing and prevent writing to common memory 205. Along with this, the state of the signal on the signal line 21B is %1
# is a trigger signal for storing input information of the protect register 224, and is sent onto the signal line 209. This causes the state of the signal input information to be stored internally.

The state of the signal on the signal line 216 is reported to the CPU I O1 by means such as an interrupt, and the abnormality handling program of the CPU 201 is activated. The abnormality processing program reads out the information stored in the flip-flop 224 and reads it into the CPU 201 via the read signal line 225, and outputs this content to an output device such as a printer, so that it is possible to know in which control device a write violation has occurred due to a program bug. can.

The same applies when the disk control device 2021 writes to the common memory 205. When a memory access request is output on the signal line 226, the contention circuit 208 outputs a memory access request on the signal line 227.
Wait until the access permission signal is returned to MI2, and then send the signal MI2.
2 Output address signal Al-A18 on S. Upper address information A on signal line 228! -All is input to the protect memory 204 from the signal line 229 and outputs the stored information in the protect memory 206 onto the output signal line 250. The state of the signal on signal line '150 is routed through AND gate 231 to signal line 218.

Thereafter, memory control operations are performed in the same manner as the above operations.

(Effects of the Invention) As described above, the present invention provides a processing device that operates a plurality of control devices that operate according to a program using a microprocessor as a core, through a common memory, in which a control device that commits a write violation to the common memory. and CPUK
If the above memory contents are read out using a register circuit,
This has the advantage that a control device that has committed a write violation within a processing device can be easily identified, and the program of the identified control device can be debugged at an early stage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of a memory write prevention circuit using a program debugging method. FIG. 2 is a block diagram showing an embodiment of the program debugging method according to the present invention. 101,! Of・φ・CPU 102.205---Common memory 103.205.2G4・・Protect memory 103・
...WE gate 206...Memory access contention circuit 208--φ disk controller 213, 217, 251-φ-AND gate 2115.
218, 221 φ・・OR gate 224・φ・protect register 104 to 107, 109, 202. LoT. 209～212,214,216,219゜220.2
22.22i5.225~230... No./Signal line

Claims (1)

[Claims] a common memory for exchanging information between devices; a write protect memory for storing write-protected information in block units of the common memory for each control device according to instructions from the CPU; contention prevention means for executing memory accesses in an orderly manner so that the memory accesses are not simultaneously accessed; and a means for storing a control device in which a writing violation has occurred in the common memory so that it can be read by the CPU. A program debugging method characterized by comprising a register circuit.