JPS58159167A - Multi-processor system - Google Patents

Abstract

PURPOSE:To avoid the breakdown of a memory exclusively used by each processor by another processor, by providing a protecting memory having a memory area corresponding to each processor. CONSTITUTION:Processors 12-1-12-N are connected to a multi-bus 11. In addition, a selecting circuit 13 which decides the using right of the bus 11 for each processor and a memory 14 are connected to the bus 11. The bus 11 consists of an address bus 11A, a data bus 11D, a control bus 11C, and a selection bus 11S which shows NO of processors 12-1-12-N which monopolize presently the bus with the signal delivered from the circuit 13. Furthermore, an interruption line 15 is connected the processors 12-1-12-N from the memory 14 to inform the abnormal of the memory 14 to those processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiprocessor system in which a memory device is shared by a plurality of processors.

[Purpose of the invention]

An object of the present invention is to provide a multiprocessor system that can reliably prevent destruction of memory owned by other processors as a memory device that is shared by multiple processors, and that facilitates maintenance, inspection, and troubleshooting. Our goal is to provide the following.

[Summary of the invention]

The present invention is provided with a protect memory having a memory area corresponding to each process, and when data is written to the main memory by the processor, when the protect information written in advance in the protect memory is read and determined to be protected. This is a multipath system that attempts to achieve the above objective by notifying the processor that has given the data write command of an abnormality.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. First, FIG. 1 is a diagram showing a schematic configuration of a multiprocessor system in which a plurality of processors and a memory device shared by these processors are connected through paths. That is, in the system shown in FIG. 1, 11 is a multipath, and this multipath 11
A plurality of derosés 12-1 to 11-N are connected to the terminal, and a selection circuit 13 and a memory device 14 are further connected to determine the multipath usage rights of the respective grosses 12-1 to 12-N.

The multipath 11 includes an address bus 11 for address signals, a data bus 11D for data exchange, a control IC and a selection circuit 13 for controlling the memory device 14 and peripheral devices (not shown).
A selection path 11 for indicating NO of the processors 12-1 to 12-N currently occupying the path with a signal output from the
It is composed of B. Further, from the memory device 14 to each of the processes 12-1 to 12-N, the memory device 1
4 becomes abnormal and an interrupt 1115 is connected that notifies Grosse 12-1 to 12-N at 9.

Next, FIG. 2 is a diagram showing a specific example of the memory device 14 shown in FIG. 1. In the figure, the address bus JJA includes a decode circuit 11 for decoding signals on the address bus.
21 and address r-) IJ are connected. This decoding circuit 21! It has a function of reading protect information from the protect memory 24 or writing protect information. In other words, these 11 decoding circuits decode the signal on the address bus 11A and write it.
21 and read f-) 26 is r-) controlled to set j4 to read or write, and
Address switching of the address switching circuit 21 is performed.

2# is a decoding circuit that decodes the address input from the address bus JJA via the address switching circuit 21 by address switching, and a signal output from this circuit 28 selects a memory area of the protect memory 24.

The decoding circuit 22 is an address parse IIA.
The above signal is decoded to control the write gate 29 and read gate 10 to set the main memory element 31 to read or write and the protect memory 24 to write. Select memory element 31. In addition, each decoding circuit 21.
22 outputs data y-tsz, s by its decoded output.
s and inputs the data on the %r-1/4 slot 11D to the main memory element 3 or the protect memory 24. 3
Reference numeral 4 is an interrupt generation circuit, which is used when setting the main memory element 31 to write, and if the contents of the protect memory 24 mean protection, the interrupt generation circuit outputs an interrupt signal. ~
This is to interrupt a signal indicating that the l2-NK is abnormal.

Next, the operation of the multi-layer system configured as described above will be explained. When the power is turned on to the device shown in FIG.
A signal is sent to write Zorotect information into the protect memory 24.

Therefore, first of all, writing of Zolotect information will be described. When the decode circuit 21 decodes the signal on the address bus 11 and determines that protection information is to be written, it switches the address switching circuit 21, opens the write f-) 25, and enables the data dart 33. Here, the address signal on the address bus 11m is input to the decode circuit 21 and the protect memory 24 via the address switching circuit 21. This decoding circuit 2g sends its decoded output as a select signal to the protect memory 24, and outputs it to the protection memory 24, which has requested writing of the protection information, to the gross register 12-1 or 12-2, . . .
Select the memory area corresponding to . At this time, the data signal on the data bus 11D is input to the protect memory 24 via data r-)xs. In this state, write from the control path 11B r −) j j
When a write signal is input via the data gate 33, the data signal from the data gate 33 is used to write protect information into the protect memory 24.

Next, an example of writing data into one main memory element 31 will be described. The signal on the address bus 11 is sent to the decoding circuit 2.
1'fC, the decoding circuit 22 decodes the signal and sends the decoded signal to the address r -) J J
Yohi f-fi? '-) 32 and enter these y-t a
Enable s and sx, and also write y-
Let J m be open. At this time, the decode output of the decode circuit 22 selects the memory area of the main memory element s1 via the chip select (C8).

In the above state, the address signal on the address bus 11M and the data signal on the data bus 11D enter the main memory element 31, and data is written into the main memory element 31 by the write signal from the control path IIC.

Therefore, before writing data to the main memory element 31, the signal on the control path JJC is set to write r-)7.
1 to the R terminal of the protect memory 24, and is set on the protect information read side. Furthermore, the address signal of the address bus JJA and the selection signal of the selection path 11B are input to the address switching circuit 27, and the address signal generated as a result is input to the decoding circuit 28 and the protect memory 24. Here, the decoding circuit 28 decodes the address signal and ! Select CB!
A select signal is sent to select a memory area of the protect memory 24. Then, the protection information of the memory area is read out and written to the AND/DART 35 along with the output of r-) 2 #. If the read information is protected, a process is executed to change it from the interrupt generation circuit S4. 1 or 12-2, . . . to input an interrupt signal indicating an abnormality.

[Effect of the invention] 4. Therefore, according to the multiprocessor system as described above, the memory area of the protect memory selected for each processor is used, and the protect memory written in advance is used when writing data to the main memory. Since the presence or absence of groping is determined from memory information, the memory owned by each processor is not destroyed by other processors, and the reliability of the memory device can be increased.

First, it is easy to see the protected state in which all processors can read and write protected memory, and! You can easily change the protection letter. Furthermore, even if one processor is not protected in advance, another processor's processor may not be protected in advance. When a processor is protected, an interrupt signal is returned by a write operation, so communication between processors is possible, and maintenance and inspection and troubleshooting are facilitated. Processor system can be provided.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a multiprocessor system according to the present invention, and FIG. 2 is a configuration diagram showing a specific example of the memory device shown in FIG. 1. 11...Multipath, 11 people...Address bus, 1
1D...Data bus, 11C...Control path, IIB-selection bus, 12-1 to 1j-N...Processor, 14-...Memory device, 21.22...Decoding circuit, 2S...・Address f-), j4...Protect memory, 21...Address switching circuit, 18...
Decode circuit, 31...main memory element, sx, s
s...data y-), 34... interrupt generation circuit.

Claims (1)

[Scope of Claims] In a multiprocessor system in which a plurality of processors are connected to a memory device via multipaths, the memory device includes a protected memory having a memory area corresponding to the processor, and a protect memory having a memory area corresponding to the processor; Means for writing data on a multipath data bus as protection information into a corresponding memory area according to a protection write address; Rose. a main memory into which data on the data bus is written in accordance with a data write address from scratch; and a tie-building signal which writes data into the main memory when or before writing data to this main memory. means for reading the protect information of the protect memory using the means; and when it is determined that the protect information read by the means is protected, an interrupt is generated for writing the data and sending an interrupt signal to notify the user of an abnormality. A multiprocessor system characterized by comprising a circuit.