JPS59108937U

JPS59108937U - data transfer device

Info

Publication number: JPS59108937U
Application number: JP403783U
Authority: JP
Inventors: 山根　信吾
Original assignee: 三菱電機株式会社
Priority date: 1983-01-13
Filing date: 1983-01-13
Publication date: 1984-07-23

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のデータ転送装置のブロック図、第２図は
第１図に示す装置のタイムチャート、第３図はこの考案
の一実施例によるデータ転送装置のブロック図、第４図
は第３図のタイムチャート、第５図はこの考案の他の実
施例を示すデータ転送装置のブロック図である。１・・・処理装置、２・・・中継装置、３．３ｎ・・・
入力器、６・・・レシーバ、７．３１・・・ドライバ、
８・・・デコーダ、９，１０．３０・・・ラッチ、１５
．１６・・・インバータ、１７・・・一致回路、１８．
１９・・・ゲート。なお、図中、同一符号は同一、又は
相当部分を示す。FIG. 1 is a block diagram of a conventional data transfer device, FIG. 2 is a time chart of the device shown in FIG. 1, FIG. 3 is a block diagram of a data transfer device according to an embodiment of this invention, and FIG. FIG. 3 is a time chart, and FIG. 5 is a block diagram of a data transfer device showing another embodiment of this invention. 1... Processing device, 2... Relay device, 3.3n...
Input device, 6... Receiver, 7.31... Driver,
8...Decoder, 9,10.30...Latch, 15
．． 16... Inverter, 17... Matching circuit, 18.
19...Gate. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

a processing device for outputting an address signal for an input device having data to be transferred and a data read and write command signal; 1 latch,
a second latch that latches a reply signal received from the input device in response to reception of the read command and then sends it to the processing device; and a second latch that latches data received from the input device in response to reception of the read command. a relay device having a third latch for transmitting data to the first processing device;
A matching circuit generates a matching signal when the address signal of the latch matches an address uniquely given in advance, and the matching signal and a read command of the processing device received via the relay device are outputted. A data transfer device comprising: the input device having a gate circuit that sometimes sends the reply signal and the data.