JPS58147051U - Devices that share the same memory - Google Patents
Devices that share the same memoryInfo
- Publication number
- JPS58147051U JPS58147051U JP4264982U JP4264982U JPS58147051U JP S58147051 U JPS58147051 U JP S58147051U JP 4264982 U JP4264982 U JP 4264982U JP 4264982 U JP4264982 U JP 4264982U JP S58147051 U JPS58147051 U JP S58147051U
- Authority
- JP
- Japan
- Prior art keywords
- same memory
- control systems
- share
- devices
- read operation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例を示す回路のブロック図、第
2図は第1図の信号作成回路5の詳細回路図、第3図は
第2図信号作成回路5の動作を説明するタイムチャート
である。
1はROM、2はマルチプレクサ、3.4はゲ、−ト、
5は信号作成回路、13,14.18はフリップフロッ
プである。
篭み止り櫨)^
一鏝り嶽り信号 B −
ゲートデーツバZA
ゲートデーツバス B
−一一一一一一一一」FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the signal generation circuit 5 of FIG. 1, and FIG. 3 explains the operation of the signal generation circuit 5 of FIG. 2. This is a time chart. 1 is ROM, 2 is multiplexer, 3.4 is gate,
5 is a signal generation circuit; 13, 14, and 18 are flip-flops. 1111111”
Claims (1)
のメモリに前記2系統の制御系が同時に読み出し動作を
行なった場合優先度を与えて選択し、待たされる制御系
には読み出し持ち信号を返偏し、2系統の制御系より別
個に読み出し動作が行なわれた場合既に他系統の制御系
が使用中であれば読み出し持ち信号を返信し、時分割で
2系統の制御系より1個のメモリを利用することを特徴
とする同一メモリを共用する装置。When the two control systems perform a read operation at the same time on one memory that stores data commonly used by the two control systems, priority is given and selected, and the control system that has to wait is given a read hold signal. If a read operation is performed separately from two control systems, if another control system is already in use, a read-out signal is returned, and one read operation is performed from two control systems in a time-sharing manner. A device that shares the same memory, characterized in that it uses the same memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4264982U JPS58147051U (en) | 1982-03-26 | 1982-03-26 | Devices that share the same memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4264982U JPS58147051U (en) | 1982-03-26 | 1982-03-26 | Devices that share the same memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58147051U true JPS58147051U (en) | 1983-10-03 |
Family
ID=30053764
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4264982U Pending JPS58147051U (en) | 1982-03-26 | 1982-03-26 | Devices that share the same memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58147051U (en) |
-
1982
- 1982-03-26 JP JP4264982U patent/JPS58147051U/en active Pending
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