JPS5417643A - Central processor - Google Patents

Central processor

Info

Publication number
JPS5417643A
JPS5417643A JP8239377A JP8239377A JPS5417643A JP S5417643 A JPS5417643 A JP S5417643A JP 8239377 A JP8239377 A JP 8239377A JP 8239377 A JP8239377 A JP 8239377A JP S5417643 A JPS5417643 A JP S5417643A
Authority
JP
Japan
Prior art keywords
central processor
plural number
latency
allowing
reduce
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8239377A
Other languages
Japanese (ja)
Inventor
Tsuneo Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8239377A priority Critical patent/JPS5417643A/en
Publication of JPS5417643A publication Critical patent/JPS5417643A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To reduce a latency-time loss, by allowing a plural number of logic devices simultaneous access to a plural number of common memories selectively.
COPYRIGHT: (C)1979,JPO&Japio
JP8239377A 1977-07-08 1977-07-08 Central processor Pending JPS5417643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8239377A JPS5417643A (en) 1977-07-08 1977-07-08 Central processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8239377A JPS5417643A (en) 1977-07-08 1977-07-08 Central processor

Publications (1)

Publication Number Publication Date
JPS5417643A true JPS5417643A (en) 1979-02-09

Family

ID=13773330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8239377A Pending JPS5417643A (en) 1977-07-08 1977-07-08 Central processor

Country Status (1)

Country Link
JP (1) JPS5417643A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142049A (en) * 1984-07-31 1986-02-28 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Data processing system
JPS63304344A (en) * 1987-06-05 1988-12-12 Mitsubishi Electric Corp Multi-port memory circuit
JPH06161874A (en) * 1992-11-25 1994-06-10 Nec Corp Hared memory control system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS526032A (en) * 1975-07-04 1977-01-18 Hitachi Ltd Main storage control unit
JPS5264838A (en) * 1975-11-26 1977-05-28 Toshiba Corp Memory control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS526032A (en) * 1975-07-04 1977-01-18 Hitachi Ltd Main storage control unit
JPS5264838A (en) * 1975-11-26 1977-05-28 Toshiba Corp Memory control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142049A (en) * 1984-07-31 1986-02-28 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Data processing system
JPH0449144B2 (en) * 1984-07-31 1992-08-10 Intaanashonaru Bijinesu Mashiinzu Corp
JPS63304344A (en) * 1987-06-05 1988-12-12 Mitsubishi Electric Corp Multi-port memory circuit
JPH06161874A (en) * 1992-11-25 1994-06-10 Nec Corp Hared memory control system

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