JPS6486261A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS6486261A JPS6486261A JP24283887A JP24283887A JPS6486261A JP S6486261 A JPS6486261 A JP S6486261A JP 24283887 A JP24283887 A JP 24283887A JP 24283887 A JP24283887 A JP 24283887A JP S6486261 A JPS6486261 A JP S6486261A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- bus line
- circuit
- memory
- memory block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To individually divide a memory block from a bus line by connecting the memory block with a power source control circuit to the bus line connected to a microprocessor and a decoder circuit through a bus line dividing circuit. CONSTITUTION:A MPU 17 and a decoder circuit 27 connected to a CMOS memory 19 are connected to a bus line 20, memory block circuits 21-23 are connected to power source control circuits 28-30 respectively, and the circuits 21-23 are connected to the line 20 respectively through bus line dividing circuits 24-26. Thereafter, the bit of the memory 19 is read by the processor 17, the corresponding circuits 24-26, the circuits 28-30, and the circuit 27 are controlled, and necessary memory blocks are divided from the line 20.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24283887A JPS6486261A (en) | 1987-09-29 | 1987-09-29 | Memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24283887A JPS6486261A (en) | 1987-09-29 | 1987-09-29 | Memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6486261A true JPS6486261A (en) | 1989-03-30 |
Family
ID=17095045
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24283887A Pending JPS6486261A (en) | 1987-09-29 | 1987-09-29 | Memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6486261A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007006336A (en) * | 2005-06-27 | 2007-01-11 | Nec Corp | Reception data storage circuit |
US8242373B2 (en) | 2006-08-29 | 2012-08-14 | Nippon Mektron, Ltd. | Flexible wiring board with characteristic impedance control circuit |
-
1987
- 1987-09-29 JP JP24283887A patent/JPS6486261A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007006336A (en) * | 2005-06-27 | 2007-01-11 | Nec Corp | Reception data storage circuit |
US8242373B2 (en) | 2006-08-29 | 2012-08-14 | Nippon Mektron, Ltd. | Flexible wiring board with characteristic impedance control circuit |
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