JP2007006336A - Reception data storage circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress influences upon signal processing to a minimum by automatically recovering trouble in a reception data storage section comprising a plurality of SRAMs. <P>SOLUTION: A memory supervisory and control section 31 monitors currents supplied from a power source section 40 to SRAMs 11-13 using current detection sections 21-23. If an SRAM to which an abnormal current flows is detected, a bus connected to the relevant SRAM is temporarily made into high impedance and disconnected in a disable state, and a power source supplying said current is turned off. After the lapse of a fixed time, the relevant SRAM is reset into enable state, and power supply is started again. The current detection sections monitor the operating current of the relevant SRAM and if it is a normal state for a fixed time, the bus connected to the relevant SRAM is connected again. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a configuration of a baseband signal processing unit in a radio base station apparatus such as a cellular phone, and more particularly to a received data storage format in a buffer memory that temporarily stores received data before baseband processing.

  In a radio base station of a cellular phone, a sector configuration is generally employed in order to increase spatial frequency utilization efficiency, increase the number of lines, and increase antenna gain. A method of dividing a cell into six sectors of 60 degrees is employed (see Patent Document 1).

  FIG. 8 is a block diagram excerpting a receiving unit in a conventional mobile phone radio base station apparatus. In the case of reception, six (0 to 5) antennas receive respective frequencies, and the radio unit (70) After the signal from the antenna is detected and converted to a digital signal by an A / D converter or the like, 6 systems of received data (8 bits × 6 + synchronization signal + parity) are multiplexed so that they can be easily processed in the baseband unit. Are collectively transmitted to the baseband signal processing unit (80).

  The baseband signal processing unit (80) sequentially processes the input received data. However, it may be necessary to compare the data before and after in time or to process the data afterward. After the data is temporarily stored in the storage unit (10) functioning as a buffer circuit, the data is read from the storage unit (10) and output to the signal processing unit 60 to perform predetermined processing, and the wireless transmission path interface unit (90 ) To the host device.

  FIG. 9 is a block diagram showing a conventional data storage format in the baseband signal processing unit of the radio base station apparatus. This conventional data storage configuration includes a storage unit (10), a data processing unit (30), a power supply unit (40), a received data input unit (50), and a signal processing unit (60). 10) is composed of an 18-bit wide SRAM, and is used for temporary storage of received data. Address setting, data reading / writing, synchronization signal input, and enable control are performed under the control of the data processing unit (30).

  In the example of FIG. 9, the storage unit (10) is composed of three SRAM1 (11), SRAM2 (12) and SRAM3 (13) having an 18-bit width, and the address specified by the data processing unit (30). In addition, two sets of 8-bit data and a synchronization signal are stored per SRAM. Therefore, the received data is stored in association with a total of 6 systems of data of 2 systems each of SRAM 1 (11), SRAM 2 (12) and SRAM 3 (13).

  The data processing unit (30) includes a data conversion unit (32), a memory access unit (34), an input processing unit (36), and an output processing unit (37). The data conversion unit (32) transmits the data from the reception data input unit (50) to the memory access unit (34), and transmits the data received from the memory access unit (34) to the output processing unit (37). To do. The memory access unit (34) has an interface function with the storage unit (10), and performs address setting, data transmission / reception, and synchronization signal transmission / reception to the storage unit (10).

  The input processing unit (36) receives the reception data from the reception data input unit (50) and transmits it to the data conversion unit (32). The output processing unit (37) receives the data from the data conversion unit (32) and transmits it to the signal processing unit (60). The power supply unit (40) supplies power necessary for the operation of each block. The reception data input unit (50) transmits data to the input processing unit (36). The signal processing unit (60) receives the data transmitted from the output processing unit (37), and performs baseband signal processing such as peak detection using a DSP or the like.

JP 2001-094490 A JP-A-7-234799

  In the conventional data storage circuit shown in FIG. 9, when a hardware failure such as latch-up occurs in the SRAM, the failure cannot be detected, so that erroneous data is transmitted to the signal processing unit (60). There is a problem that the baseband signal processing is adversely affected.

  When a latch-up phenomenon occurs in a device including a semiconductor circuit, it is possible to automatically release the latch-up of the device and return to normal operation by temporarily turning off the power supplied to the device and resetting the device ( For example, see Patent Document 2), when a hardware malfunction such as latch-up occurs in the SRAM in the configuration shown in FIG. 9, if the power supply unit (40) is turned off and reset, the operation of the entire circuit is affected. There is a problem of giving.

  Furthermore, even if only one of the three SRAMs in the configuration shown in FIG. 9 has a hardware problem, the entire hardware used is affected and the memory storage pattern is fixed. For this reason, there is a problem that data at a location corresponding to the SRAM in which the malfunction has occurred becomes unusable.

  For this reason, in the received data storage method using the SRAM, a method of performing error detection by adding a parity bit or interleaving at the time of data storage is also considered. In this case, the data is protected. However, when a soft error or hard error occurs, an error can be detected by the error detection function, but the error state cannot be recovered.

  In addition, there is a problem that data assigned to the SRAM in which the hard error has occurred cannot be read correctly, and even in the SRAM in which no hard error has occurred, the data cannot be read and the data continues to be lost.

  In view of the above-described problems, an object of the present invention is to provide data that can minimize the influence of a failure on a signal processing unit when a failure occurs in the received data storage unit including a plurality of SRAMs. To provide a storage format.

  According to the present invention, in the circuit for temporarily storing and reading the received data in the SRAM, each of the SRAMs of the received data storage circuit having a plurality of SRAMs for storing the received data is provided with a latch-up automatic release unit, respectively. If one of the SRAMs fails due to an external factor and causes a software error or latch-up, resulting in a data error, data processing can continue using the remaining SRAM. In addition, in the case of occurrence of latch-up, a large-scale data loss can be avoided by controlling only power supply to the SRAM and automatically restoring it.

  That is, according to the present invention, when a failure occurs in any of the plurality of SRAMs in the received data storage method in which a plurality of received data are allocated to a plurality of SRAMs, temporarily stored, read out and transmitted to the signal processing unit. Then, the current data supplied to the SRAM is temporarily cut off and then restarted to automatically restore the failure of the SRAM. The received data stored in the remaining normal SRAM is restored until the SRAM is restored. Then, the signal processing is continued.

  At that time, when a failure occurs in any of the plurality of SRAMs, reallocation for storing the received data of the system allocated to the SRAM in another normal SRAM until the failure of the SRAM is recovered. By doing this, it is possible to avoid large-scale data loss in a specific system.

  The received data storage circuit of the present invention comprises a plurality of SRAMs, has a storage unit for temporarily storing received data of a plurality of systems input from a received data input unit, and an interface function between the storage unit and a reception unit. The SRAM for temporarily storing the data of the plurality of systems is allocated for each system, the received data for each system is written to a predetermined address of the allocated SRAM, and the written received data is read to the signal processing unit. A memory access unit that performs output control, an enable control unit that controls operation start / stop of the plurality of SRAMs for each SRAM, and an operating current supplied from the power supply unit to each SRAM are monitored and set in advance. A plurality of current detectors that transmit a signal indicating abnormality of the SRAM when an operating current exceeding the threshold value is detected. And receiving a signal indicating an abnormality of the SRAM transmitted from the current detection unit and a storage unit power control unit that controls on / off of an operating current supplied from the power supply unit to each of the plurality of SRAMs. Control to disconnect the bus connected to the SRAM of the memory access unit with a high impedance, control to stop the operation of the SRAM by the enable control unit, and the SRAM by the storage unit power control unit Instructing execution of control to turn off the power supply to the SRAM, and starting the operation of the SRAM by the enable control unit after a predetermined time and control of restarting the power supply to the SRAM by the storage unit power control unit When instructing execution and receiving a signal indicating that the SRAM has recovered normally from the current detection unit, Characterized by comprising a memory monitoring control unit for instructing the execution of the control for releasing the high impedance of the bus connected to the SRAM Mori access unit.

  The received data storage circuit of the present invention includes a parity addition detector that adds parity to data to be written to the SRAM, performs a parity check of data read from the SRAM, and detects an error for each SRAM, and the SRAM A counter unit that counts the number of errors detected every fixed time and transmits a count signal to the memory monitoring control unit, and the memory monitoring control unit monitors the count signal of the counter unit for each SRAM. When the SRAM having the count value equal to or greater than a predetermined value exists, it is determined that an abnormality has occurred in the SRAM, and the bus connected to the SRAM by the memory access unit is disconnected with high impedance, and the enable control Control to stop the operation of the SRAM by the unit, and the storage unit power control unit Instructs execution of control to turn off the power supply to the SRAM, and starts the operation of the SRAM by the enable control unit after a predetermined time, and resumes power supply to the SRAM by the storage unit power control unit And monitoring the count signal for the SRAM transmitted from the counter unit, and instructing execution of control for releasing the high impedance of the bus connected to the SRAM by the memory access unit. When the value is lower than a predetermined value, it has a function of executing control to continue the use of the SRAM.

  The received data storage circuit according to the present invention includes an error correction unit that adds an error correction bit to data to be written to the SRAM, performs error check on the data read from the SRAM, and corrects the error, and the error correction unit. A counter unit that receives the checked error information, counts the number of errors per fixed time detected for each SRAM, and transmits a count signal to the memory monitoring control unit, the memory monitoring control unit, The count signal of the counter unit is monitored for each SRAM, and when there is an SRAM whose count value is equal to or greater than a predetermined value, it is determined that an abnormality has occurred in the SRAM, and the bus connected to the SRAM by the memory access unit is determined. Control to isolate with high impedance, the operation of the SRAM by the enable control unit Control to stop and control to turn off the power supply to the SRAM by the storage unit power control unit, and control to start the operation of the SRAM by the enable control unit after a predetermined time, the storage unit power Instructed by the control unit to resume power supply to the SRAM and the memory access unit to execute control for releasing the high impedance of the bus connected to the SRAM, and transmitted from the counter unit It has a function of monitoring a count signal for the SRAM and executing a control to continue using the SRAM when the count value is lower than a predetermined value.

  When the memory access unit receives control from the memory monitoring control unit to disconnect the abnormal SRAM, the memory access unit reallocates the received data of the plurality of systems by the SRAM excluding the abnormal SRAM until the abnormal SRAM returns to normal. It can be set as the structure which has the function to perform.

  Further, the memory monitoring control unit has a function of setting the SRAM to a non-use state thereafter when the abnormality of the SRAM is not resolved even if the recovery control operation of the abnormal SRAM is repeated a predetermined number of times. And

  The present invention has an overcurrent detection function, and even if a malfunction occurs in the SRAM and a latch-up phenomenon occurs in which overcurrent flows, the power of the SRAM is temporarily turned off. The impact can be minimized.

  In addition, since it has an error detection function, it is possible to detect the state and restore the power even if the data corruption is not restored unless the power is turned on again. Automatic recovery is possible.

  Furthermore, even if one of the three SRAMs is damaged, the data storage format changing function is provided, so that a fatal loss of data necessary for signal processing can be avoided.

  FIG. 1 is a block diagram of a received data storage circuit showing an embodiment of the present invention, and a storage unit (10) that functions as a buffer memory that temporarily stores data of a plurality of systems input from a received data input unit (50). A data processing unit (30) that stores the data of the plurality of systems in the storage unit (10), reads out the data from the storage unit and outputs the data to the signal processing unit (60), and a storage unit (10 ) And a storage unit power supply control unit (20) that controls the power supply to the storage unit (10).

  In this embodiment, the storage unit (10) used for temporary storage of received data is composed of three SRAMs (11), SRAM2 (12), and SRAM3 (13) having an 18-bit width. Address setting, data reading / writing, synchronization signal input, and enable control are performed under the control of the data processing unit (30), and two sets of 8-bit data per SRAM and a synchronization signal are stored at a designated address.

  The storage unit power supply control unit (20) monitors the operating current of the storage unit (10), monitors the current of the SRAM1 (11) with the current detection unit 1 (21), and the current of the SRAM2 (12) as the current. Monitoring is performed by the detection unit 2 (22), and the current of the SRAM 3 (13) is monitored by the current detection unit 3 (23). The current detection unit 1 (21), the current detection unit 2 (22), and the current detection unit 3 (23) are mainly configured by a MOSFET and a comparator, and have a function of outputting a control signal when an overcurrent flows. The threshold value for determining the overcurrent can be set individually. When an overcurrent is detected, the information is transmitted to the data processing unit (30). Further, on / off control of power supply to the storage unit (10) is performed by a power on / off control signal from the data processing unit (30).

  The data processing unit (30) can be configured by an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array), and includes a memory monitoring control unit (31), a data conversion unit (32), It comprises a parity addition detection unit (33), a memory access unit (34), an enable control unit (35), an input processing unit (36), an output processing unit (37), and a counter unit (38). The memory monitoring control unit (31) monitors the output signal from the current detection unit 1 (21), the current detection unit 2 (22), the current detection unit 3 (23), and the signal from the counter unit (38). The state is transmitted to the data conversion unit (32), and the control signal is transmitted to the storage unit power supply control unit (20), the memory access unit 34, and the enable control unit 35 according to the state.

  The data conversion unit (32) receives a signal from the memory monitoring control unit (31), transmits data from the received data input unit (50) to the parity addition detection unit (33), and also adds a parity addition detection unit ( 33) is received and transmitted to the output processing unit (37). The parity addition detection unit (33) adds a parity bit to the data received from the data conversion unit (32) and transmits the data to the memory access unit (34). Also, the parity addition is detected from the data received from the memory access unit (34). Calculation is performed, the received data is collated, and the collation result is transmitted to the counter unit (38).

  The memory access unit (34) has an interface function with the storage unit (10), and performs address setting, data transmission / reception, and synchronization signal transmission / reception to the storage unit (10). The enable control unit (35) receives a signal from the memory monitoring control unit (31), and performs start / stop control of the SRAM1 (11), SRAM2 (12), and SRAM3 (13).

  The input processing unit (36) receives the reception data from the reception data input unit (50) and transmits it to the data conversion unit (32). The output processing unit (37) receives the data from the data conversion unit (32) and transmits it to the signal processing unit (60). The power supply unit (40) supplies power necessary for the operation of each block. The reception data input unit (50) transmits data to the input processing unit (36). The signal processing unit (60) receives the data transmitted from the output processing unit (37), and performs baseband signal processing such as peak detection using a DSP or the like.

  FIG. 2 is a time chart showing an operation when latch-up occurs in the SRAM 1 (11) in the present embodiment. The operation when latch-up occurs in the SRAM 1 (11) will be described below with reference to FIGS.

  When the latch-up occurs in the SRAM 1 (11), the operating current increases from the normal time, and the operating current supplied to the SRAM 1 (11) is detected as an abnormal current by the current detector 1 (21) exceeding the threshold. (S01). A signal indicating that an overcurrent flows in the SRAM 1 (11) is transmitted to the memory monitoring control unit (31) (S02). The memory monitoring control unit (31) that has received this abnormal signal from the current detection unit 1 (21) determines that latch-up has occurred in the SRAM 1 (11), and sends it to the memory access unit (34) and the enable control unit (35). On the other hand, a control signal for once disconnecting the SRAM 1 (11) is sent, and a control signal for temporarily shutting off the power supply to the SRAM 1 (11) is sent to the current detection unit 1 (21).

  In response to this control signal, the memory access unit (34) disconnects the bus connected to the SRAM 1 (11) with high impedance in order to avoid the influence on the data processing unit (30) (S03), and enables control. The unit (35) transmits a disable signal to the SRAM1 (11) to disable the SRAM1 (11) (S04), and the current detection unit 1 (21) is transferred from the power supply unit (40) to the SRAM1 (11). The supplied power is turned off (S05).

  Thereafter, the enable control unit (35) resets the SRAM1 (11) to the enable state (S06) by the control signal output from the memory monitoring control unit (31) after a certain time, and the current detection unit 1 (21). Resumes power supply to the SRAM 1 (11) (S07). Then, the operating current of the SRAM 1 (11) detected by the current detector 1 (21) is monitored, and if it is in a normal state for a certain time, a control signal is sent to the memory access unit (34) and connected to the SRAM 1 (11). The connected buses are reconnected (S08).

  According to the present embodiment, the SRAM2 (12) and the SRAM3 (13) other than the SRAM1 (11) in which the latch-up has occurred operate even while the SRAM1 (11) is latched up. The system data stored in (13) is processed as usual. In addition, since SRAM 1 (11) can also be quickly restored after the occurrence of latch-up, the influence of the system data stored in SRAM 1 (11) on the baseband signal processing associated with the occurrence of latch-up is minimized. Can do.

  In the above embodiment, the data processing of the system stored in the SRAM 1 (11) where the latch-up has occurred is suspended until the latch-up of the SRAM 1 (11) is released. Therefore, when a failure occurs in one of the three SRAMs, the system data stored in the failed SRAM can be supplemented with the remaining two SRAMs.

  FIGS. 3 to 4 show the cases where, when a failure occurs in one of the three SRAMs, the system data stored in the failed SRAM is shared by the remaining two SRAMs. It is a figure explaining the data writing and data reading to SRAM. Hereinafter, a method for temporarily storing data stored in the SRAM 1 (11) in the SRAM 2 (12) and the SRAM (13) will be described with reference to FIGS.

  FIG. 3 shows a normal data flow in which all three SRAMs are normal. SRAM 1 (11), SRAM 2 (12), and SRAM 3 (13) receive two sets of 8-bit data, and data 01 to 08 and data 11 to 18 are input to SRAM 1 (11), and data 21 to 28 and Data 31 to 38 are written to the SRAM 2 (12), and data 41 to 48 and 51 to 58 are written to the SRAM 3 (13). When reading, the data is read without conversion.

  FIG. 4 shows a data flow when a failure occurs in the SRAM 1 (11) and the SRAM 1 (11) is partly allocated to the SRAM 2 (12) and the SRAM 3 (13). In this case, the data 01 and 02 to the SRAM 1 (11) are placed in the locations of the data 27 and 28 in the SRAM 2 (12), and the data 03 and 04 to the SRAM 1 (11) are placed in the locations of the data 37 and 38 in the SRAM 2 (12). A total of 4 bits are allocated. Similarly, the data 11 and 12 to the SRAM 1 (11) are in the locations of the data 47 and 48 in the SRAM 3 (13), and the data 13 and 14 to the SRAM 1 (11) are in the locations of the data 57 and 58 in the SRAM 3 (13). Assign and save.

  When reading, the reverse procedure is used, but the data 21 to 26 and data 31 to 36 of the data read from the SRAM 2 (12) are padded to the upper part and the lower 2 bits are padded with zeros to form 8-bit data. Convert. A total of 4 bits, 2 bits of data 27 and 28 and 2 bits of data 37 and 38, are assigned to the locations of data 01 to 04 from the upper side, and the lower 4 bits are padded with zeros and converted to 8-bit data. Similarly to the case of the SRAM 2 (12), the data read from the SRAM 3 (13) is packed up with 6 bits of the data 41 to 46 and the data 51 to 56 among the data read from the SRAM 3 (13), and the lower 2 bits. Is padded with zeros and converted to 8-bit data. A total of 4 bits, 2 bits of data 47 and 48 and 2 bits of data 57 and 58, are assigned from the upper part to the locations of data 11 to 14, and the lower 4 bits are padded with zeros. To 8-bit data.

  Thereafter, when the trouble is eliminated in the SRAM 1 (11), the normal data flow shown in FIG. 3 is restored. According to the present embodiment, while the malfunction occurs in the SRAM 1 (11), the signal processing of the system in which the data is stored in the normal SRAM is somewhat affected, but the data is stored in the malfunctioned SRAM. The influence on the signal processing of the system in which is stored can be minimized.

  FIG. 5 is an operation explanatory diagram in the case where the failure of the SRAM 1 (11) is not solved and the SRAM 1 (11) is unusable after the overcurrent continues to flow even after the power is turned on again.

  In FIG. 5, the consumption current of the SRAM 1 (11) increases (S11). When an abnormal current is detected by the current detection unit 1 (21) and the fact that the abnormal current is flowing to the SRAM 1 (11) is transmitted to the memory monitoring control unit (31) (S11), the memory monitoring control unit (31) Under the control, the memory access unit (34) disconnects the bus connected to the SRAM 1 (11) with high impedance in order to avoid the influence on the data processing unit (30) (S13), and the enable control unit (35). Disables SRAM1 (11) (S14), and current detector 1 (21) turns off the power of SRAM1 (11) (S15).

  After a certain period of time, when SRAM1 (11) is enabled and power supply to SRAM1 (11) is resumed, if overcurrent flows again to SRAM1 (11), SRAM1 (11) is disabled again. Then, the power of the SRAM 1 (11) is turned off. If the malfunction of the SRAM 1 (11) is not solved even after repeating this operation a certain number of times, the SRAM 1 (11) is subsequently set to a disabled state and the power to the SRAM 1 (11) is turned off and fixed to an unused state. To do. As a data storage method after the SRAM 1 (11) is not in use, the method shown in FIG. 4 can be used. A similar method is also used when a failure occurs in each of the SRAM 2 (12) and the SRAM 3 (13).

  FIG. 6 is an explanatory diagram showing an operation when data corruption occurs in the data read from the SRAM 1 (11).

  In the case of bit corruption, the current consumption of the SRAM 1 (11) does not increase, so the abnormality detection of the SRAM 1 (11) cannot be performed by the current detection unit 1 (21). Therefore, the parity addition detection unit (33) adds parity to the data to be written to the storage unit (10), performs parity check on the data read from the storage unit (10), detects an error, and displays the error detection result as a counter unit ( 38) (S21). The counter unit (38) counts, for example, the number of errors that have occurred in a predetermined time for each SRAM, and transmits a count signal to the memory monitoring control unit (31).

  The memory monitoring control unit (31) monitors the count signal of the counter unit (38) for each SRAM. For example, the count signal of the SRAM 1 (11) is equal to or greater than a predetermined value, and error conditions are continuously generated. In this case, it is determined that data corruption has occurred in the SRAM 1 (11), and control signals are sent to the memory access unit (34), the enable control unit (35), and the storage power source control unit (20), and the SRAM 1 The bus connected to (11) is disconnected with high impedance (S22), SRAM1 (11) is disabled (S23), and the power of SRAM1 (11) is turned off (S24).

  After a certain period of time, the memory monitoring control unit (31) sends control signals to the memory access unit (34), the enable control unit (35), and the storage power supply control unit (20) to enable the SRAM 1 (11). (S25) The SRAM1 (11) is powered on (S26), and the bus is returned to the active state (S27). Thereafter, if error conditions do not occur continuously in the parity check, the use is continued as it is. The data storage method when the SRAM 1 (11) is powered off uses the method of FIG. 4 as described above.

  FIG. 7 is a block diagram of a received data storage circuit showing another embodiment of the present invention. The basic configuration is the same as that of the above embodiment, but the parity addition detection unit (33) in the above embodiment. By using the error correction unit (39), the error correctable data is corrected and output to reduce the influence of the SRAM soft error.

  In this embodiment, the number of bits of the SRAM is increased, and the error correction unit (39) adds an error correction bit to the received data to be written to the storage unit (10), and the data read from the storage unit (10) is garbled. When the error occurs, the error correction unit (39) performs error correction as well as detection of bit corruption, and outputs the error-corrected data to the signal processing unit 60.

  The counter unit (38) counts the errors detected by the error correction unit (39) for each SRAM, and transmits the count result to the memory monitoring control unit (31). The memory monitoring control unit (31) performs monitoring control of each SRAM based on the count result transmitted from the counter unit (38). The operation is the same as the operation described with reference to FIG. Omitted.

It is a block diagram of a received data storage circuit showing an embodiment of the present invention. It is a time chart which shows the operation | movement at the time of abnormal condition generation | occurrence | production in this embodiment. It is a figure which shows the example of the data preservation | save form at the time of normal of this embodiment. It is a figure which shows the example of the data preservation | save form at the time of abnormality of this embodiment. It is a time chart which shows operation | movement when an abnormal state continues in this embodiment. It is a time chart which shows operation | movement when abnormality arises in read-out data in this embodiment. It is a block diagram of the received data preservation | save circuit which shows other embodiment of this invention. It is a block diagram which shows the structural example of the receiving part in a wireless base station apparatus. It is a block diagram which shows the example of the conventional reception data storage circuit.

Explanation of symbols

0 to 5 Antenna 10 Storage unit 11 to 13 SRAM
20 Storage Unit Power Supply Control Unit 21-23 Current Detection Unit 30 Data Processing Unit 31 Memory Monitoring Control Unit 32 Data Conversion Unit 33 Parity Addition Detection Unit 34 Memory Access Unit 35 Enable Control Unit 36 Input Processing Unit 37 Output Processing Unit 38 Counter 39 Error Correction unit 40 Power supply unit 50 Received data input unit 60 Signal processing unit 70 Wireless unit 80 Baseband signal processing unit 90 Wireless transmission path interface unit 100 Control unit

Claims (7)

In a received data storage method of allocating received data of a plurality of systems to a plurality of SRAMs for temporary storage, reading and transmitting to a signal processing unit,
When a failure occurs in any of the plurality of SRAMs, only the current supply to the SRAM is temporarily interrupted and then restarted to automatically recover the failure of the SRAM, and until the SRAM recovers The signal processing is continued using the received data stored in the remaining normal SRAM.   When a failure occurs in any of the plurality of SRAMs, reallocation of the received data of the system allocated to the SRAM to be stored in another normal SRAM until the failure of the SRAM is recovered The received data storage method according to claim 1. A storage unit configured by a plurality of SRAMs and temporarily storing received data of a plurality of systems input from the received data input unit;
An SRAM having an interface function with the storage unit and temporarily storing the received data of the plurality of systems is allocated to each system, and the received data of each system is written to the designated address of the allocated SRAM, and the writing is performed. A memory access unit that performs control to read out received data and output the received data to the signal processing unit;
An enable control unit that controls operation start / stop of the plurality of SRAMs for each SRAM;
It has a plurality of current detectors that monitor the operating current supplied from the power supply unit for each of the SRAMs and transmit a signal indicating an abnormal operating current of the SRAM when an operating current equal to or higher than a preset threshold is detected. And a storage unit power supply control unit for controlling on / off of an operating current supplied from the power supply unit to each of the plurality of SRAMs;
When the signal indicating the abnormal operation current of the SRAM transmitted from the current detection unit is received, the memory access unit controls to disconnect the bus connected to the SRAM with high impedance, and the enable control unit Control for stopping the operation of the SRAM and instructing execution of control for turning off power supplied to the SRAM by the storage unit power control unit, and control for starting the operation of the SRAM by the enable control unit after a predetermined time When the memory access unit instructs the execution of control to resume power supply to the SRAM and receives a signal indicating that the SRAM has recovered normally from the current detection unit, the memory access unit Instructs execution of control to release the high impedance of the bus connected to the SRAM. By the memory monitoring control unit that executes a recovery control of abnormal SRAM,
A received data storage circuit comprising: Parity is added to the data to be written to the SRAM, a parity addition detection unit for performing error check by performing a parity check of the data read from the SRAM, and counting the number of errors per fixed time detected for each SRAM, A counter unit for transmitting a count signal to the memory monitoring control unit;
The memory monitoring control unit monitors the count signal of the counter unit for each SRAM, and when there is an SRAM having a count value equal to or larger than a predetermined value, the memory monitoring control unit determines that an abnormality has occurred in the SRAM, and the memory access unit Control for disconnecting the bus connected to the SRAM with high impedance, control for stopping the operation of the SRAM by the enable control unit, and control for turning off the power supply to the SRAM by the storage unit power control unit Execution is instructed, control for starting the operation of the SRAM by the enable control unit after a predetermined time, control for resuming power supply to the SRAM by the storage unit power control unit, and connection to the SRAM by the memory access unit Instructs execution of control to release the high impedance of the connected bus. The function of resuming data storage in the SRAM, monitoring the count signal for the SRAM transmitted from the counter unit, and performing control to continue the use of the SRAM when the count value falls below a predetermined value 4. The received data storage circuit according to claim 3, further comprising: An error correction bit is added to the data to be written to the SRAM, an error check of the data read from the SRAM is performed to correct the error, and error information checked by the error correction unit is received, and the SRAM A counter unit that counts the number of errors per fixed time detected each time and transmits a count signal to the memory monitoring control unit;
The memory monitoring control unit monitors the count signal of the counter unit for each SRAM, and when there is an SRAM having a count value equal to or larger than a predetermined value, the memory monitoring control unit determines that an abnormality has occurred in the SRAM, and the memory access unit Control for disconnecting the bus connected to the SRAM with high impedance, control for stopping the operation of the SRAM by the enable control unit, and control for turning off the power supply to the SRAM by the storage unit power control unit Execution is instructed, control for starting the operation of the SRAM by the enable control unit after a predetermined time, control for resuming power supply to the SRAM by the storage unit power control unit, and connection to the SRAM by the memory access unit Instructs execution of control to release the high impedance of the connected bus. The function of resuming data storage in the SRAM, monitoring the count signal for the SRAM transmitted from the counter unit, and performing control to continue using the SRAM when the count value falls below a predetermined value 4. The received data storage circuit according to claim 3, further comprising:   When the memory access unit receives a control signal for disconnecting the abnormal SRAM from the memory monitoring control unit, the memory access unit performs reallocation for storing the received data of the system allocated to the abnormal SRAM in another normal SRAM The received data storage circuit according to claim 3, wherein the received data storage circuit is provided. The memory monitoring control unit has a function of setting the SRAM to a non-use state thereafter when the abnormality of the SRAM is not eliminated even after repeating the recovery control operation of the abnormal SRAM a predetermined number of times. The received data storage circuit according to any one of claims 3 to 6.

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