JPS62166455A - Memory device - Google Patents

Abstract

PURPOSE:To perform operation with only effective memory arrays without shutting down the system by making a memory array in trouble insignificant with an enable flag when the memory array is put in trouble. CONSTITUTION:The enable flag 7 of an address base register 7 is normally in an enable state and the data set in an internal memory is compared with the high-order (n) bits 2 at this time, so that an enable signal 6a is outputted to a memory array 5 when they are coincident. If trouble occurs to an array 5 in system operation, the flag 7 in a register 6 which is assigned to the array 5 is disabled. Therefore, the signal 6a is not outputted and the array 5 where the trouble occurs is not accessed. Then, the memory in the register 6 which is assigned to another effective array 5 is rewritten to reallocate an address space.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device in which memory arrays can be reallocated without bringing down the system.

[Prior Art] FIG. 2 is a block diagram showing a conventional storage device. In the figure, (1) is a CPU, m connected to (not shown)
A bit address bus, (2) is the upper n bits of the address bus (1), and (3) is a dip switch in which predetermined n-bit data is set. (4) is the upper n bits (2) of the address bus (1) and the dip switch 3)
from! This is a comparison circuit that compares the 1-bit output signal (3a) and outputs an enable signal (4a) if they match. (5) is a memory array to which a specific address space is allocated, and although not shown in the figure, there are multiple memory arrays, and when the enable signal (4a) is input to each, the address specified by the lower In-n bits is It is now possible to access it.

A conventional storage device is configured as described above, and a dip switch is used to output a predetermined output signal (3a).
3) is set, and when this output signal (3a) matches the upper n bits (2), the comparison circuit (4) outputs an enable signal (4a).

The memory array (5) to which the enable signal (4a) is input becomes capable of accessing the address specified by the lower m-n bits of the address bus (1).

[Problems to be Solved by the Invention] As described above, conventional storage devices are equipped with dip switches (3
) to obtain the enable signal (4a) for the memory array (5). Therefore, if a failure occurs in a particular address space, that is, the memory array, this address space must be allocated to another memory array. If this happens, there is a problem in that the computer must be turned off in order to change the setting of the DIP switch (3).

This invention was made to solve the above-mentioned problems, and the purpose is to obtain a storage device that can disable a faulty memory array and operate only with a valid memory array without system down. shall be.

[Means for solving the problem] A storage device according to the present invention is connected to an address bus,
a plurality of memory arrays assigned to specific address spaces; and an address base register connected to an address bus, containing a built-in memory for assigning the address space of the memory arrays, and outputting an enable signal to the memory arrays. , and an enable flag built into this address base register to indicate the validity of the memory array.

[Operation] In this invention, when a fault occurs in a memory array, the enable flag disables the faulty memory array through dynamic operation by software, and the address space of this memory array is set in the address base register. memory and reallocate it to other available memory arrays.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of this invention, (1)
, (2) and (5) are similar to the conventional device described above. (6) is the upper n bits (2) of address bus (1)
and the lower m−n bits are input, and the memory array (5)
This is an address base register for allocating a specific address space. The address base register (6) has a built-in memory, and n-bit data is set therein. Also, although not shown, a plurality of memory arrays (5)
are provided corresponding to each. (7) is built in the address base register (6), and the memory array (5) is built in the address base register (6).
), and when this enable flag (7) is enabled and the data in the address base register (6) matches the upper n bits (2), the enable signal (6a) is activated. Memory array (
5).

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be explained.

Address base register (6) is for each memory array (5)
Therefore, each address base register (6) is assigned a specific address corresponding to the memory array (5).

First, when the system boots, all address base registers (6) are accessed sequentially, and each memory array (5
) is assigned a specific address space, the memory in each address base register (6) is initialized to contain n bits of data.

Normally, the enable flag (7) of the address base register (6) is enabled, and at this time, the data set in the internal memory and the upper n bits (2) are compared and if they match. For example, an enable signal (6a) is output to the memory array (5). Enable signal (6a
) is input memory array (5)? Imaginary, lower m −I
The access to the address of t bits is performed once.

If a failure occurs in a certain memory array (5) during system operation, the enable flag (7) in the address base register (6) assigned to this memory array (5) is disabled.

Therefore, the enable signal (6a) is not output, and the failed memory array (5) is not accessed), that is, access to the memory array (5) is avoided. Then, the memory in the address base register (6) allocated to another valid memory array (5) is rewritten to reallocate the address space.

The above operations are dynamically performed by software of the CPU (not shown).

In the above embodiment, one memory array (5) has one
A program (not shown) is included in the address base register (6), and this program causes each memory array (5
), and when a failure occurs, the memory array is invalidated and the address space is reallocated, one address base register (6)
It is possible to manage all memory arrays (5) with only one person.

In this case, the program stored in the address base register (6) is loaded when the system is booted and can be reloaded even while the system is running, and is used to allocate the address space to the memory array (5) and when a failure occurs. Needless to say, it is possible to dynamically and easily change how to deal with the situation.

[Effects of the Invention] As described above, according to the present invention, there is provided an address base register which is connected to an address bus, has a built-in memory for allocating the address space of the memory array, and outputs an enable signal to the memory array. and an enable flag built into this address base register to indicate the validity of the memory array. When a failure occurs in the memory array, the enable flag is set to the memory where the failure occurred by dynamic operation by software. In addition to invalidating the array, the address space of this memory array is reallocated to other valid memory arrays by rewriting the memory in the address base register, which has the effect of providing a storage device that will not cause the system to go down. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional storage device. (1) Address bus (5) Memory array (6) Address base register (6a) Enable signal (7) Enable flag 6o: Enable signal 7: Ikeya几 frage

Claims (3)

[Claims] (1) An address bus, a plurality of memory arrays connected to the address bus and assigned to a specific address space, and a built-in memory connected to the address bus for assigning the address space of the memory array; The address base register includes an address base register that outputs an enable signal to the memory array, and an enable flag built into the address base register to indicate the validity of the memory array. A storage device characterized in that the memory array in which the fault has occurred is disabled by an enable flag, and the address space of the memory array is reallocated to another valid memory array by the memory in the address base register. (2) The storage device according to claim 1, wherein a plurality of address base registers are provided corresponding to each memory array. (3) The address base register has a built-in program that allocates address space to the memory array, invalidates the memory array when a failure occurs, and reallocates the address space, and Claim 1, which is characterized by managing all
Storage device described in section.