JP3020356B2 - Memory mapper circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory mapper circuit for allocating a user memory space to an emulation memory in an emulation system or the like.

[0002]

2. Description of the Related Art Conventionally, an in-circuit emulator is connected to a target system instead of a microprocessor, thereby enabling arbitrary execution / stop of a program,
It is known as a microprocessor development support device having a trace function of reading / writing and execution of resources such as a memory.

FIG. 8 is a block diagram of a mapper circuit of an emulation memory in a conventional emulation system.

In FIG. 1, a conventional mapper circuit has a 64K byte emulation memory 1 which can be allocated in units of 4K bytes in a CPU emulation system having a memory space of 16M bytes.
Is a mapper circuit using the emulation CPU 2
Is switched to the host address bus 3 and the host data bus 4 at the time of a stop (break), and the allocation data is written in the mapper memory 5 from the host side.

Next, when the emulation CPU 2 operates (executes a user program), the multiplexer (hereinafter referred to as MPX) 6 switches the input to the upper side (A23 to A12) of the emulation address, and the emulation address (A23 to A12). ) Is used as an S / U-signal for accessing the emulation memory 1 or the target memory (user memory) 7, and the emulation memory address is used as a page address. (PA3 to PA0).

As shown in FIG. 9, for example, in the memory map of the emulation CPU 2, "1000 to 1000"
"1FFF" address and "700000 to 705FFF"
The addresses correspond to addresses “1” or “700 to 705”, respectively, in the mapper memory map, and the addresses “10” and “11 to 11” from the host side.
16 ", the top 1 of this written value
The bit is the S / U- signal, and the lower 4 bits are the page address as the upper side of the emulation memory 1 (the lower side is the lower side A11 of the emulation address bus 8).
~ A0), the memory space of 16M bytes is 4K
It can be allocated to the emulation memory 1 of 64 Kbytes in units.

[0007]

However, in the conventional mapper circuit, if the emulation CPU 2 is operated at a high speed, the emulation CPU 2 does not have to wait and the access memory of the emulation memory 1 or the target memory can be used. Since the judgment has to be made, a high-speed mapper memory is required. Further, as the emulation bus width increases, a large-capacity memory is required, and the emulation memory 1 is also increased. As a result, a plurality of memories are required to obtain an emulation address. Such a high-speed and large-capacity memory is expensive, and when a plurality of memories are used, there is a problem in that the area dedicated to the substrate of the mapper memory increases.

Accordingly, an object of the present invention is to provide a high-speed, small-sized and low-cost memory mapper circuit.

[0009]

In order to achieve the above object, a memory mapper circuit according to the present invention comprises: an allocation start address register for externally setting an allocation start address for an emulation memory; and the allocation start address register. A mask address register that externally sets a mask bit to a corresponding bit of the emulation memory, and a page address that is an upper address of the emulation memory.
A page address register for externally setting an address, an attribute register for externally setting an attribute for selecting between target memory access and emulation memory access, and a mask set in the mask address register. No comparison is made between each bit of the emulation address and the start address corresponding to the bit, and the start address and the emulation address corresponding to the mask bit that is not set in the mask are set.
A comparison circuit that compares each bit of the address and outputs a match signal only when all of these bits match; based on the match signal output from the comparison circuit, the page address register and the attribute It outputs register data.

In the embodiment of the present invention, the comparison circuit includes a plurality of channels, determines the priority of the coincidence signal output from each channel, and outputs the data of the page address register and the attribute register. Things.

[0011]

According to the above arrangement, the comparison circuit has a mask
The mask set in the address register
No comparison is made between each bit of the emulation address and the start address corresponding to the bit, and each bit of the start address and each bit of the emulation address corresponding to only the mask bits not set in the mask address register are compared. A match signal is output only when all bits match, and the page address of the page address register and the attribute data of the attribute register are output based on the match signal. This allows
By converting the address of the emulation CPU to a page address, the emulation CPU space can be allocated to an arbitrary space of the emulation memory.

Further, if a plurality of comparison circuits are provided, the priority of the coincidence signal outputted from each channel is determined, and the data of the page address register and the attribute register are outputted, a plurality of assignments can be made. .

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention; FIG. 1 is an overall block diagram of a mapper circuit of a memory according to an embodiment of the present invention.

The mapper circuit of this embodiment emulates a CPU having a memory space of 4 Gbytes, for example.
In the system, a mapper circuit of a 1-Mbyte emulation memory which can be allocated in units of 4 Kbytes or more is shown.

Referring to FIG. 1, the mapper circuit includes a host
Eight first to eighth channel circuits CH connected to the bus 11 and the emulation address bus 12, respectively.
1 to CH8 and a channel determination circuit 13 for determining these channels. The host bus 11
An allocation start address, an address mask, a page address, and attributes, which will be described later, which are externally set from a host computer (not shown), are respectively assigned to the first to eighth channel circuits CH1
To the CH8. The emulation address bus 12 is a bus for supplying the emulation address data from the emulation CPU to each of the first to eighth channel circuits CH1 to CH8. is there. Further, the channel determination circuit 13
Determines the output of any of the first to eighth channel circuits CH1 to CH8 and supplies the page address PA to the upper side of the address of the emulation memory (not shown).
And an S / U- signal for accessing either the emulation memory or the target memory.

The first channel circuit CH1 holds, for example, 20-bit allocation start address data for allocating the emulation address of the emulation CPU (equal to the address of the target memory) to the emulation memory. An allocation start address register 14, for example, an address mask register 15 for holding the same 20-bit mask data, for example, a page address register 16 for holding 8-bit page data, and, for example, 1
And an attribute register 17 for storing bit attribute data. The first channel circuit CH1 includes an emulation address, a start address of the allocation start address register 14, and an address mask register 1.
5, a comparator 18 for inputting the mask data and outputting a match signal, and an MPX for inputting an emulation address, mask data and the page address of the address mask register 16 and outputting a page address for each channel. And a page address output circuit 19 comprising:

Further, each of the second to eighth channel circuits CH2 to CH2
CH8 is configured similarly to the above-described first channel circuit CH1. Match signals CH1EQ to CH8EQ output from the comparison circuit 18 of each channel, and channel page address C output from each page address output circuit 19
H1PA to CH8PA and the attribute signals CH1S / U- to CH8S / U- output from the attribute registers 17 are supplied to the channel determination circuit 13, respectively.

FIG. 2 is a circuit diagram showing the internal configuration of the comparison circuit of the embodiment of the present invention. In FIG. 2, for example, the comparison circuit 18 of the first channel circuit CH1 is an emulation circuit.
The address and the allocation start address are 2 for each bit.
This is a circuit for comparing 0 bits, and 20 1-bit comparison circuits 18-12 to 18-31 are provided corresponding to the emulation addresses (A12 to A31). For example, the one-bit comparison circuit 18-12 includes a two-input exclusive NOR gate 18-12a and a two-input OR gate 1
8-12b. The upper bit A12 of the emulation address is input to one input side of the two-input exclusive NOR gate 18-12a, and the other input side has a corresponding allocation. The bits CH1A12 of the start address are input. One input side of the OR gate 18-12b is connected to a two-input exclusive NOR gate 18-12a.
And the other input side has the corresponding bit CH1M set in the address mask register 15.
A12 is input.

Similarly, each of the other 1-bit comparison circuits 18-1
3 to 18-31 are composed of a two-input exclusive NOR gate and a two-input OR gate in the same manner as described above. The addresses of the upper bits A13 to A31 of the corresponding emulation address and the allocation start address register 14 Set bit CH1A13
~ CH1A31 and mask bits CH1MA13 ~
CH1MA31 is input in the same manner as the one-bit comparison circuit 18-12.

The outputs of the two-input OR gates of these 20 one-bit comparison circuits 18-12 to 18-31 are input to the input side of a 20-input NAND gate 18-40, and the logics of those inputs are all " In the case of "1", the coincidence signal CH of "0" is output from the output of the NAND gate 18-40.
1EQ- is output. Similarly, match signals CH2EQ- to CH8EQ- are output from the respective comparison circuits 18 of the second to eighth channel circuits CH2 to CH8 to the channel determination circuit 13, respectively.

FIG. 3 is a block diagram showing the internal configuration of the channel determination circuit according to the embodiment of the present invention. In FIG. 3, a channel determination circuit 13 outputs a coincidence signal CHEQ- (CH1EQ) output from a comparison circuit 18 for each channel. -~ CH8E
A priority circuit 20 for determining a priority based on Q-);
A page address determination circuit 21 for outputting the page address CHPA of the determined channel;
And an attribute determination circuit 22 that outputs / U-.

FIG. 4 is a block diagram for explaining a priority order circuit according to the embodiment of the present invention.
0 inputs the match signals CH1EQ- to CH8EQ- output from the first to eighth channel comparison circuits 18;
A circuit for determining an effective channel;
Of the outputs CH1ON to CH8ON corresponding to the channel, the one corresponding to the enabled channel outputs active high. That is, the coincidence signal C of the first channel
When H1EQ- becomes valid, the output CH1ON becomes "1", and the coincidence signal C of the second to eighth channels is similarly output.
When H2EQ-〜CH8EQ- becomes effective, CH2ON〜CH8ON becomes “1” corresponding to each. At this time, if two or more of the outputs CH1ON to CH8ON become “1”, the priority is C
H1ON is the highest, followed by CH2ON to CH8ON.

FIG. 5 is a diagram showing the internal configuration of the page address determination circuit according to the embodiment of the present invention. The page address determination circuit 21 is provided with the outputs CH1ON to CH8ON of the first to eighth channels of the priority order circuit 20. The address of the channel that has become valid (active high) is indicated by the page address P
A (PA0 to PA7) and outputs the page address PA in the emulation memory
Used as the upper side of the address. In the figure, the page address determination circuit 21 includes a page address CH1PA to CH8PA of each channel which is an output from each page address output circuit 19, and outputs of the first to eighth channels of the priority order circuit 20. CH1ON ~ CH
8 gate circuits 21- to which 8ON is input respectively.
1 to 21-8. Here, the page address CH1PA is composed of eight bits CH1PA0 to CH1PA7. Similarly, the page address CH2PA to CH1PA7 is
8PA is composed of 8 bits each. Each of the gate circuits 21-1 to 21-8 has eight 2-input AND gates corresponding to 8 bits. For example, the gate circuit 21-1 includes eight AND gates 21-
10 to 21-17. Bits CH1PA0 to CH1PA7 of the first channel are respectively connected to one input sides of these AND gates 21-10 to 21-17.
And the other input side thereof receives the output CH1ON of the first channel of the priority order circuit 20.
In the gate circuits 21-2 to 21-8 of the other channels, the outputs CH2ON to CH8 of the second to eighth channels are also provided.
ON and page address CH2PA of 8-bit configuration
CH8PA is input similarly to the gate circuit 21-1. Further, the outputs of the AND gates 21-10 to 21-17 of the gate circuit 21-1 are input to the input sides of the 8-input OR gates 21-20 to 21-27, respectively. ~ 21-
The output of each AND gate 8 is OR gate 21
-20 to 21-27. Then, each output PA0 of these OR gates 21-20 to 21-27.
PA7 are used as the 8-bit page address PA on the upper side of the emulation memory address.

FIG. 6 is a diagram showing the internal configuration of the attribute determining circuit according to the embodiment of the present invention.
Is the attribute signal CH1S / from the first to eighth channel circuits.
U- to CH8S / U, the output C of the priority circuit 20
This is a circuit which outputs an attribute signal corresponding to a channel in which H1ON to CH8ON is valid (active high) as an S / U- signal, and includes eight 2-input AND gates 22-1 to 22-8 corresponding to 8 bits. Have. On one input side of each of these AND gates 22-1 to 22-8,
Outputs CH1ON to CH1 of priority of the first to eighth channels
8ON are input, and the other input side is provided with the respective attribute signals CH1S / U- from the respective attribute registers 17.
To CH8S / U are input. Also,
The output of each of the AND gates 22-1 to 22-8 is input to the input side of an 8-input OR gate 22-10, and the output is S
It is supplied to the emulation memory and the target memory as a / U- signal.

Next, the operation of the mapper circuit configured as described above will be described. In advance, the channel circuits CH1 to CH8
Each allocation start address register 14, address
Mask register 15, Page address register 1
6 and the attribute register 17 from the host via the host bus 11 with a 20-bit start address (CH1
A12 to CH1A31), 20-bit mask data (CH1MA12 to CH1MA31), 8-bit page address, and 1-bit attribute data are externally set and held.

First, in the comparison circuit 18, for example,
The start address (CH1A12 to CH1A3) of the allocation start address register 14 of the first channel circuit CH1
1) are 1-bit comparison circuits 18-12 to 18-18, respectively.
Exclusive NOR gate 18-12a in -31
Of each of the exclusive NOR gates 18-12a.
The corresponding upper bits A12 to A31 of the emulation address are input from the emulation CPU via the emulation address bus 12. As a result, the output of the exclusive NOR gate 18-12a of each channel becomes "1" when the logic of the start address matches the logic of the emulation address, and becomes "0" when they do not match. The output of each exclusive NOR gate 18-12a is input to one input side of each OR gate 18-12b, and the mask data (CH1M) input to the other input side.
A12 to CH1MA31) and a logical sum is obtained for each bit. The output of each OR gate 18-12b is input to the input side of the NAND gate 18-40.

That is, when the bit of the mask data is "1" (in a mask state), the matching / mismatch between the corresponding start address and the emulation address is not performed, and the bit of the mask data is not compared. Is "0", the output of each exclusive NOR gate 18-12a is output from the OR gate 18-12b.
And the comparison of the match / mismatch is performed. The mask data is set sequentially from the lower bit side. As a result, if the allocation start address matches the emulation address, "1" is input to the input side of the NAND gate 18-40. Then, when all the outputs of the respective OR gates 18-12b become "1", the coincidence signal CH1EQ- of "0" is outputted from the output side of the NAND gate 58-40. The same operation as described above is performed in the comparison circuits 18 of the second to eighth channel circuits CH2 to CH8.

Next, the operation of the page address output circuit will be described with reference to FIG. FIG. 7 is a diagram for explaining the operation of the page address output circuit 19. In the figure, for example, an emulation CPU is provided in a page address output circuit 19 of a first channel circuit CH1.
The upper 8 bits (A12 to A12) of the emulation address via the emulation address bus 12 from the side.
A19), 8 bits of mask data in the address mask register 15, and 8-bit page data and attribute data in the page address register 16 are input. First, a logical product is obtained between the ration address and the mask data. For example, when the emulation address is “1010 1010” and the mask data is “0000 1111”, the logical product result is “0000 1010”. Further, the logical product result is ORed with the page data of “1100 0000”, for example, and the logical sum result is “1100 0000”.
1010 ", which is output as the channel page address CH1PA. In other words, a bit whose mask data is "1" sets the bit of the emulation address corresponding to the bit to the page address CH1PA.
The bit data of the mask data “0” sets the corresponding page data bit as the bit data of the page address CH1PA.

The same operation as described above is performed in the page address output circuits 19 of the second to eighth channel circuits CH2 to CH8. Thus, by setting the value of the page data on the host side, the page address CH
The upper bits of 1PA to CH8PA (when the mask data is "0" and not in the mask state) can be freely changed.

Next, in the channel determination circuit 13, as described above, each of the first to eighth channel circuits CH1 to CH8
Signal CH1E of each channel output from
Q- to CH8EQ- and channel page address C
H1PA to CH8PA and attribute signals CH1S / U- to C
H8S / U- is input to the priority ordering circuit 20, the page address determining circuit 21, and the attribute determining circuit 22 of the channel determining circuit 13.

In the priority order circuit 20, as described above,
Among the coincidence signals CH1EQ-CH8EQ- of each channel, a valid signal is decoded, and among the outputs CH1ON-CH8ON of the priority of each channel, a signal corresponding to the signal is set to "1". And this output CH1O
N to CH8ON are supplied to the page address determination circuit 21 and the attribute determination circuit 22. For example, when only the output CH1ON of the first channel becomes valid (“1”),
In the gate circuit 21-1 of the page address determination circuit 21, the bit CH1PA0 of the channel page address is set.
The outputs of the AND gates 21-10 to 21-17 corresponding to "1" of the signals CH1PA7 become "1".

Accordingly, the OR gates 21-20 to 21-2
7 are output from bits CH1PA0 to CH7.
The one corresponding to “1” in 1PA7 is “1”, and the others are “0”. That is, bit CH1PA0 of channel page address CH1PA
ＣＨCH1PA7 is output as it is. As described above, the channel page address corresponding to the valid channel among the outputs CH1ON to CH8ON is determined as the page address PA, and the emulation memory address is determined.
Used as the upper side of the address.

On the other hand, in the attribute determination circuit 22, outputs CH1ON to CH8 are output by AND gates 22-1 to 22-8.
The logical product of ON and the attribute signals CH1S / U- to CH8S / U- is respectively obtained, and the result of the logical product is OR gate 2
The logical sum is obtained in 2-10, and the result is output as the S / U- signal. That is, the attribute signal corresponding to the valid channel among the outputs CH1ON to CH8ON is S / U
-Determined as a signal.

As described above, in this embodiment, the page
The emulation address can be arbitrarily set by the page address by changing the upper bits of the page address PA by externally setting the data value on the host side. Thereby, the emulation CPU memory space (user memory space) can be allocated to an arbitrary space of the emulation memory. Accordingly, the emulation CPU memory space can be allocated to the emulation memory space as shown in FIG. 9 without using a mapper memory as in the related art. Further, since a register and a gate circuit which hold data to be set from the outside are used without using a mapper memory as in the related art, access can be performed at high speed even if the emulation CPU is operated at high speed. Further, even if the width of the emulation bus is widened, it can be dealt with by increasing the number of comparison bits, can be inexpensive, and the area occupied by the substrate can be reduced by configuring these circuits with a gate array.

In the above embodiment, a mapper circuit of a 1 Mbyte emulation memory which can be allocated in units of 4 Kbytes or more in a CPU emulation system having a memory space of 4 Gbytes has been described. The present invention is not limited to this, and can be applied to an emulation memory having an arbitrary capacity that is allocated in a predetermined unit for a CPU having an arbitrary memory space. .

[0036]

As described above in detail, according to the present invention, each bit of the start address and the emulation address corresponding to the corresponding start address and emulation address is determined by the mask bit set in the mask address register in the comparison circuit. The emulation CPU controls the comparison, outputs a match signal only when all bits match, and outputs a page address of a page address register and attribute data of an attribute register based on the match signal.
Can be converted to a page address, and the emulation CPU space can be allocated to an arbitrary space of the emulation memory, which has the effect of increasing the speed, size, and cost of the mapper circuit.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of a mapper circuit of a memory according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a comparison circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram showing an internal configuration of a channel determination circuit according to the embodiment of the present invention.

FIG. 4 is a block diagram illustrating a priority order circuit according to an embodiment of the present invention.

FIG. 5 is a diagram showing an internal configuration of a page address determination circuit according to the embodiment of the present invention.

FIG. 6 is a diagram showing an internal configuration of an attribute determination circuit according to the embodiment of the present invention.

FIG. 7 is a diagram for explaining the operation of the page address output circuit according to the embodiment of the present invention.

FIG. 8 is a block diagram of a mapper circuit of an emulation memory in a conventional emulation system.

FIG. 9 is a diagram illustrating a conventional memory space allocation state.

[Explanation of symbols]

 11 Host Bus 12 Emulation Address Bus 13 Channel Determination Circuit 14 Allocation Start Address Register 15 Address Mask Register 16 Page Address Register 17 Attribute Register 18 Comparison Circuit 19 Page Address Output Circuit 20 Priority Circuit 21 Page .Address determination circuit 22 Attribute determination circuit

Continuation of front page (56) References JP-A-2-150929 (JP, A) JP-A-63-269237 (JP, A) JP-A-4-80833 (JP, A) JP-A-4-15833 (JP) , A) Hikaru 1-135546 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/22-11/34 G06F 12/00-12/06

Claims (2)

(57) [Claims] 1. An allocation start address register for externally setting an allocation start address for an emulation memory; a mask address register for externally setting a mask bit in a corresponding bit of the allocation start address register; A page address register for externally setting a page address which is an upper address of the memory; an attribute register for externally setting an attribute for selecting whether to access a target memory or an emulation memory; The start address corresponding to the mask bit set in the register and the emulation address are not compared with each other, and the start address corresponding to the mask bit not set and the emulator address are not compared. A comparison circuit that compares each bit of the translation address and outputs a match signal only when all of these bits match, based on the match signal output from the comparison circuit, And a data mapper circuit for outputting data of the attribute register. 2. The comparison circuit has a plurality of channels,
2. The memory mapper circuit according to claim 1, wherein the priority of the coincidence signal output from each channel is determined and the data of the page address register and the attribute register are output.