JPS58172751A - Program storing system - Google Patents

Abstract

PURPOSE:To debug a program only in an RAM part, by allotting two memories, i.e. ROM and RAM in a double structure for the same address, and performing the batch processing of a program stored in the ROM at a machine word level even under operation of a machine. CONSTITUTION:A central controller 100 and a main storage device 300 are connected together by a main storage bus 210 and a main storage data bus 220, and the device 300 is provided with the ROM310, RAM320, decoder circuit 330, and switch circuit 340. In this ROM310, an initial program is stored and batch images in the same addresses as addresses to be batch-processed in the stored initial program are stored in the RAM320. When the controller 100 generates an address request, the batch processing of a program stored in the ROM310 is carried out at the machine word level by the decoder circuit 330 and switch circuit 340 to debug the program only in the RAM320.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a 10-gram storage method in a program storage control method, and particularly to an AGO program storage method that requires program modification at the machine language level.

Conventionally, programs for devices that require program modification at the machine theory level have been stored in RAMK. This rounding causes memory rotation at the initial startup of the program.
Time is weak to destruction caused by out-of-control programs,
Another drawback is that the management of the correction section becomes complicated.

The present invention was made in view of these drawbacks, and eliminates the above drawbacks by accommodating only the program information of the part that has been patched at the machine level in the RAM11 of the dual memory section. However, when the program is loaded, only the corrected part is stored in the tRM MIB to shorten the low V time. 4. In addition, the KL & program storage method is used so that the information in the RAM section can also be managed. This is what we provide.

That is, the present invention can accommodate a 4K ROMIIK that does not require loading, even for device programs that require program modification at the 177-word level.

In order to modify the program while the system is running, the memory section has a dual configuration of ROM and RAM, and both
Two memories, ROM and RAM, are allocated to the same address, and the initially hidden program is stored in the ROM section of the dual memory section, and the program can be modified by Nokutsuchi etc.
Because of the need to add additional memory to the JRAM section at any time, R
The characteristics of OM-accommodated programs, such as no need for memory loading and resistance to destruction due to program runaway, can be applied to most areas of the program, and if only the RAM section is managed (K), changes made by batting the program can be achieved. 4, which has the feature of easy management, and also allows program modification at the machine level even while the machine is in operation.

The present invention will be described below based on an embodiment shown in FIG. 1iiFK.

@1lli! 3Fi is a configuration diagram showing an example of the present invention, and is a configuration diagram showing an example of the central control system of the program storage control method device.
This corresponds to the device and main memory portion.

The central control unit 100 and the main memory device 3 are connected to each other by an address bus 210 and a main memory data bus 220.
00, and the main storage device 300 includes R.
OM circuit 310, RAM circuit 320, decoder circuit 33
0 and a switch circuit 340.

The ROM circuit 310 and RAM circuit 320 Fi are connected to the central controller 100 via the main memory address bus 210 t-, respectively. On the other hand, the switch circuit 340 connects the central controller 100 via the main storage data bus 220.
is connected to. The skeleton switch circuit 340 and the ROM circuit 310 and RAM circuit 320 are connected via data paths 311 and 321, respectively. The switch circuit 340 and the decoder circuit 330 and the RAM circuit 320 and the decoder circuit 330 are connected via connections 1331 and 322, respectively.

Next, the operation of the program storage force type according to the present invention will be explained.

The initial programmer is already stored in the ROM circuit 310, and among the initial programs stored in the ROM 310K, the RAM circuit 320KFi at the same address as the address to be patched, and the patch image stored in 9B. shall be. In addition, the RAM circuit 320 is used to store the K patch image, and the soft switch father removes the memory 10 chip using the hard switch.
Just do a normal memory write. Here, when the central control unit 100 requests the main memory 9300K for a certain address value via the address bus 2101, the ROM circuit 310 and the RAM circuit 320
communicate the corresponding memory values to switch circuit 340 via data buses 311 and 321, respectively.

On the other hand, the decoder circuit 330 determines whether or not a patch image is stored in the RAM circuit 320, and only when the patch image is stored, the switch circuit 340
The main storage data bus 220 and the data bus 321 are connected when the patch image is stored, and the switch circuit is connected via the connection @ 331 so that the main storage data bus 220 and the data bus 311 are connected when no patch image is stored. 340K
Give instructions. Whether a patch image by the data circuit 330K is stored is determined by a specific bit of the RAM circuit 320, or by whether the memory value stored in the RAM circuit 320 is other than a specific value, such as allo.

The present invention has been described above, and as follows, one memory section t-ROM and R
Dual AM configuration, machine language level patches are stored in RAM
By doing this once, there is an effect that it is possible to input the patch even while the system is running while maintaining the characteristics of storing the program in the storage program tROM. In addition, since all programs can be patched and in good condition, it is possible to depack programs only in the RAM section even if the initial program accommodated in the ROM 5K has not been created at the time of system development.

[Brief Description of the Drawings] Figure 1 is a block diagram showing an embodiment of the program storage tank system of the present invention. 100... Central control unit fi 210... Main storage address bus 220... Raw 11: Memory data path 3
00...Main attachment 310...ROM circuit 32
0...RAM circuit 330...Decoder circuit 34
0...Switch circuit 311.321...Data bus 322, 331...Connection applicant NEC Corporation

Claims (1)

[Claims] The memory section that stores programs has a dual structure of ROM and RAM, and ROM and RAM are connected to the same address.
A program storage method characterized in that it is configured such that a program stored in %ROMK can be patched in one line at the machine language level while the machine is running by allocating two M memories.