JPS59117651A - Memory extension circuit of single-chip microcomputer - Google Patents

Abstract

PURPOSE:To use a general-purpose ROM efficiently as an external ROM independently of the instruction word length of a microcomputer, by adding an external extension memory address generating part and an external ROM data latch. CONSTITUTION:An instruction address designated by a program counter (PC)1 is applied to an internal ROM2 in the internal ROM instruction cycle, and read data 5 is inputted to an instruction register (IR) 8 through a multiplexer (MPX) 7 in the last of the instruction fetch cycle. In the external ROM instruction cycle, an external ROM address is generated by the PC1 and an external memory extension address generating part 11 and is applied to an external ROM3A. An extension address signal 12 becomes the least significant address bit, and upper bits become an address signal 4. In the first half of the instruction fetch cycle, the extension address signal is controlled to (0) by an internal/external ROM selecting control part 9, and lower instruction address data is latched in a latch 13A.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a single-chip microcomputer with built-in instruction memory.

Conventional configurations and their problems In recent years, one LSI (Large Scale In
Single-temperature microcomputers, which have all the computer functions built-in on the computer (integration), are widely used as controllers for various devices.

In general, the program of a single-chip microcomputer is stored in the built-in instruction memory (ROM in most cases). However, the built-in ROM is limited in memory capacity due to restrictions on the chip size of the LSI, and therefore may require an external expansion memory. or,
When developing a program, the external memory as the instruction memory must be made accessible by some method.

A memory expansion circuit in a conventional single-chip microcomputer will be explained below.

FIG. 1 shows a block diagram of a UOM expansion circuit in a conventional single-chip microcomputer. 1 is the program counter (
pc), 2 is an internal ROM that stores the program, 3 is an external ROM that stores the program, 4 is an address signal of the external ROM 3, 6 is the data of the internal ROM 2, 6 is an external ROM
M3 data, 7 is internal ROM2 data and external ROM
Multiplexer (MPX) that selectively outputs the data of 3.
, 8 is an instruction register (IR
), 9 is an internal/external ROM selection/creation section, 10 is an output control signal of the internal/external ROM selection/creation section 9, and MPX7
Make input selections.

The operation of the conventional memory expansion circuit configured as described above will be explained below.

The internal/external ROM selection control section 9 generally generates a selection signal based on an LSI terminal input, but may also generate a selection signal based on a selection control command.

In the MPX, internal ROM data 6 or external ROM data 6 is selectively inputted to IRs by a selection output signal 10, and the output of IR8 is inputted to an instruction decoder to control instruction execution.

However, in the above configuration, the external ROM3 must have the same two-word length as the internal ROM2. That is,
Internal ROM data 6 and external ROM data 6 have the same number of bits. This gives rise to the problems described below.

Generally, external ROM is not dedicated to a specific single-chip microcomputer due to cost constraints.
Preferably, a general purpose ROM is used. However, general-purpose R
Since most OMs have a specific word length such as 8 bits, they may be limited by the instruction word length of a single-chip microcomputer. For example, if the instruction word length is 12 bits, if a general-purpose ROM with 8-bit words is used,
Two must be connected in parallel.

Regarding the instruction word length of a microcomputer, in order to enable high-speed execution of instructions, it is desirable that most of the instructions be composed of one word. Therefore, if one instruction word is, for example, 10 bits or 12 bits, there will be no problem if only the internal ROM is used, but if the external ROM is
The above-mentioned problem arises during expansion.

Purpose of the Invention The present invention solves the above-mentioned conventional problems, and provides an external ROM expansion circuit in a single-chip microcomputer that can efficiently use a general-purpose ROM as an external ROM, regardless of the instruction word length of the microcomputer. The purpose is to

Structure of the Invention The present invention provides an external extended memory address generation unit and an external RO
It is a single-chip microcomputer that can be expanded with an external ROM and has a newly added M data latch.
Regardless of the bit width of OM, it is possible to have a degree of freedom in the structure of instruction words.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows a block diagram of a memory access section of a single-chip microcomputer in an embodiment of the present invention.

In FIG. 2, PCl, internal ROM2. ROM address signal 4. Internal ROM data 6, multiplexer 7, I
R8 and internal/external ROM selection unit 9 have the same structure as the conventional one shown in FIG.

The key point of this embodiment is that the external extended address generation section 11.
and extended address signal 12. The point is that a register 13 is provided to hold data 6A read from three external ROMs and input data to the single-chip microcomputer. M
PX7, external extended address generation unit 11. Each latch 13 receives a control signal 10A from the internal/external ROM selection control section 9.

Controlled by 10B and 10C.

FIGS. 3(a) and 3(b) show the data structure of the internal ROM and the external ROM, respectively. In the following description, the minimum instruction word length is assumed to be 12 bits.

Most general-purpose ROMs are composed of 8 bits per word, but in this embodiment, the internal R□M2 and external R
The purpose is to enable the memory storage state of OM3A to be converted as shown in FIG.

FIG. 4 shows the operation of this embodiment when the internal ROM 2 and external ROM are accessed by three people.

An instruction execution cycle generally consists of instruction fetch, decode,
Although this is divided into execution, the present implementation relates, of course, to the instruction fetch section. FIG. 4(IL) shows an instruction cycle using the internal ROM, and FIG. 4(b) shows an instruction cycle B using the external ROM.

The instruction execution cycle shown in FIG. 4 will be explained below according to the embodiment shown in FIG.

(1) In the case of an internal ROM instruction cycle, the instruction address designated by PC1 is applied to the internal ROM 2, and the read data 6 is input to In7 via MPX7 at the end of the instruction fetch cycle.

(2) In the case of external ROM command cycle The external ROM address is generated by PCl and the external memory expansion address generation section 11, and address signals 4 and 12 are applied to the external ROM 3A via the output terminal.

Extended address signal 12 is the lowest address bit,
The upper bit becomes address signal 4.

The instruction fetch cycle B is obtained by dividing the number of instruction fetch cycles into two. In a two-part instruction cycle, the external memory expansion address generation units 1 and 1 are controlled by the control signal IC1 of the internal/external ROM selection system part 9, and the expansion address signal becomes 0 in the first half and 1 in the second half. .

The instruction fetcher in the first half reads the lower instruction address data and latches the data into latch A13. In the latter half of the instruction fetch B, the upper instruction address data is read out, and the data is sent to the IRs via the MPX7 along with the lower instruction address data latched in the latch A13.
is input. The command input to In2 is stored in the internal ROM.
It is decoded and executed in the same way as the instruction from 2.

Note that in this embodiment, one word in the internal ROM is transferred to the external ROM2.
Although the method of storing words in words has been shown, the present invention is of course not limited to two words, and can be extended to three or more words. Also, in general, the internal ROM of a single-chip microcomputer
The access time is limited by chip size and power consumption.

However, general-purpose ROMs are limited in the data width of one word, but many have high-speed access signals, and internal ROM
It is easily possible to access the external ROM multiple times in one access time of M.

Furthermore, in the description of this embodiment, external expansion in the case of instruction memory has been explained, but it goes without saying that the idea of the present invention can also be applied to expansion of data memory.

Effects of the Invention As described above, the memory expansion circuit for a single-chip microcomputer of the present invention brings about the following effects,
Its practical value is that of a dog.

(1) A general-purpose ROM can be used as the external ROM regardless of the internal ROM width, that is, the length of the instruction word, and the degree of freedom in configuring the instruction word is large. Of course, any instruction word length can be achieved by connecting multiple ROMs in parallel, but increasing the capacity of the ROM,
Considering the technological trend toward lower prices and higher speeds, the address division method of the present invention, which allows external expansion using a single ROM in many cases, has the effect of reducing the mounting space.

For example, if one instruction word is 12 bits and the number of words is expanded to 4, the conventional method would require two ROMs each having 8 bits per word, but according to the present invention, the number of ROMs can be increased to 8, which is already in practical use today. It only requires one word ROM (aKxs bits).

(2) It is possible to reduce the increase in the number of bits/terminals when accessing external ROM. For example, if the instruction word has a 12-bit structure as shown in FIG.
Compared to the case of bits, the number of pin terminals increases by four, but according to the configuration of the present invention, even if a ROM with 8 bits per word is used, the number of pin terminals increases by only one as an address extension bit.

[Brief explanation of the drawing]

Fig. 1 is a block wiring diagram of a ROM expansion circuit in a conventional single-chip microcomputer, Fig. 2 is a block wiring diagram of a ROM expansion circuit in an embodiment of the present invention, and Fig. 3 shows the internal ROM and external ROM of the same circuit. FIG. 4 is a diagram showing the instruction execution cycle of the same circuit. 1...Program counter, 2...Internal ROM. 3 people: external ROM, 7: multiplexer, 9: internal/external ROM selection control section,
11...External extension address generation unit, 13...
···latch. Name of agent: Patent attorney Toshio Nakao and 1 other person
1511 rIA Fig. 3 Fig. 4 front page ff) i'ne cutch β

Claims (1)

[Scope of Claims] An internal memory that stores instruction words, a program counter that specifies the memory address, an external extended address generation unit that specifies an address of an external memory together with the program counter, and receives data from the external memory as input. Latches and internal memory data. 1. A memory expansion circuit for a single-chip microcomputer, characterized in that it is equipped with a memory expansion circuit for a single-chip microcomputer, and an internal/external memory control section for controlling at least the external expansion address generation section, an external memory data latch, and a multiplexer.