JPH02183331A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve flexibility and versatility by providing a mechanism which can transfer in-RAM data to a ROM data bus and a in-ROM data to a RAM data bus. CONSTITUTION:A first control circuit 30 transfers address information to a second control circuit 40 and decides whether the address information are transferred from a ROM address bus 1 or a RAM address bus 3. The second control circuit 40 transfers the address information to a ROM 5 and a RAM 6 and transfers read data to either a ROM data bus 2 or a RAM data bus 4. Thus, since the data in the RAM and ROM can be handled without any discrimination, program data can be stored in RAM as well as data for reference can be stored in the ROM as well. Then, the flexibility or function can be increased as a computer.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for storing RAM data stored in data areas such as a work area, a variable area, etc. during program execution.
Data that is executable as a program and stored in the ROM relates to a microcomputer that can be handled not only as a program but also as data such as variables.

2. Description of the Related Art Conventionally, microcomputers have been controlled by program data stored in a ROM.

The operation of the memory circuit of a conventional one-chip microcomputer will be explained below.

FIG. 4 shows the memory arrangement of a conventional one-chip microcomputer. In FIG. 4, 1 is a ROM address bus, 2 is a ROM data bus, 3 is a RAM address bus, 4 is a RAM data bus, 5 is a ROM, 6 is a RAM, and 7 is a RAM address bus.
8 is an instruction decoder, and 8 is a ROM address bus 1 information R.
Control line 9 transfers data from ROM5 to OM5.
10 is a control line that transfers information on RAM address bus 3 to RAM 6; 11 is R
This is a control line that transfers data from AM6 to RAM data bus 4.

FIG. 5 shows a ROM5. 5 is a timing diagram of reading and writing to the RAM 6. FIG.

In FIG. 5, a, b, c, and d are synchronization signals that serve as standards for reading and writing. First, the process from reading out the program in the ROM 5 to being executed will be described. Address information for reading data in the ROM 5 is output as a signal e in synchronization with the synchronizing signal C via the ROM address bus 1 and the control line 8. When the signal e is activated, the data in the ROM 5 corresponding to the address information is sent to the ROM data bus 2, or the control line 9, the ROM data bus 2, and the control line 12 are sent to the ROM data bus 2 in synchronization with the synchronization signal like the signal f. is transferred to the instruction decoder 7 via
After decoding, it is executed.

Next, the process until the data in the RAM 6 is read will be described. Address information for reading RAM6, RAM
The signal g is output via the address bus 3 and the control line 10 in synchronization with the synchronization signal a. When the signal g is activated, the data in the RAM 6 corresponding to the address information is transferred to the RAM data bus 4 via the control line 11 and the RAM data bus 4 in synchronization with the synchronization signal d. Ru.

Furthermore, the process until data is written into the RAM 6 is shown. Address information for writing data into the RAM 6 is output as a signal i via the RAM address bus 3 and control line 10 in synchronization with the synchronization signal a. When the above signal i is activated, if the data to be written is transferred to the RAM data bus 4 in synchronization with the synchronization signal S as in the signal j, it will be sent to the RAM 6 via the control 1i 111 and writing will be performed. .

Problem to be Solved by the Invention However, in the above conventional configuration, ROM data and RA
M data is clearly separated, and data in the ROM area is
Since the ROM data is used as a program and cannot be directly transferred to the RAM data bus, and the data in the RAM storage area cannot be transferred to the ROM data bus as ROM data like the ROM data, The RAM storage area has a problem in that programs cannot be stored therein.

The present invention solves the above-mentioned conventional problems.
Even when accessing data in the area, R is sent to the ROM data bus.
The purpose of the present invention is to provide a microcomputer that is capable of transferring AM data, and also allows ROM data to be transferred to the RAM data bus when accessing data in the ROM area, and has flexibility and versatility in data usage. .

Means for Solving the Problems In order to achieve this object, the microcomputer of the present invention allocates one data to one address for data in the ROM and RAM, and the same address is assigned to the ROM and RAM spaces. ROM or RA with the above address information.
A first control that can perform a first determination as to whether the address information is from the M address space and a second determination as to whether the address information is sent from the ROM address bus or the RAM address bus. a circuit is provided, the first control circuit transfers the first and second determination results to a second control circuit, and the second control circuit transfers the first and second determination results to a second control circuit; Based on the result, if address information is sent from the ROM address bus, data corresponding to the address information can be transferred to the ROM data bus in synchronization with a synchronization signal that is interpreted as ROM data. Yes, and when address information is sent from the RAM address bus above, the RAM
It has a configuration in which data can be transferred to the RAM data bus in synchronization with a synchronization signal that is meaningful as RAM data.

Effect: With this configuration, data in RAM and ROM can be treated separately, so data in RAM can be
It can be decoded and executed in the same way as the program in M, and the data in the ROM can also be read and referenced in the same way as RAM data in the prior art.

EXAMPLES Examples of the present invention will be described below with reference to the drawings.

1 and 2 show a memory circuit of a microcomputer according to an embodiment of the present invention, and FIG. 3 is a conceptual diagram showing an address space of the memory of the computer.

In Figures 1 and 2, 1 is a ROM address bus, 2
is the ROM data bus, 3 is the RAM address bus, and 4 is the R
AM data bus, 5 is ROM, and 6 is RAM. 7 is an instruction decoder, 30 is an instruction decoder, and 30 is a second control circuit 4 for transmitting address information.
0 and ROM address bus 1, or
A first control circuit 40 determines from which side of the RAM address bus 3 the address information is transferred.
5. Transfer the read data to the RAM 6 and the ROM data bus 2. 51 is a control line that transfers ROM address information to the control circuit 30; 52 is a control line that transfers RAM address information to the control circuit 30; 53 is a control circuit that transfers address information A control line 54 transfers the result determined by the control circuit 30 to the control circuit 40;
56 is a control line that transfers address information from the control circuit 40 to the RAM 6, and 56 is a control line that transfers RAM data to the RAM and the control circuit 40.
57 is a control line that transfers address information to ROM 5; 58 is a control line that transfers data in ROM 5 to control circuit 40; 59 is RAM data bus 4;
A control line 60 connects the ROM data bus 2 and the control circuit 40, and a control line 60 connects the ROM data bus 2 and the control circuit 40.

401 is a control circuit that changes the timing of transferring address information or read data; 402 is a circuit that stores address information and transfers it to ROM 5 or RAM 6 according to a control signal from control circuit 401; 403 temporarily stores data read from ROM 5 or RAM 6 and data written to RAM 6, and i! By the control signal of the J control circuit 401, the RO
This circuit transfers the above data to the M data bus 2 and the RAM data bus 4.

In FIG. 3, 501 is the ROM address space, 50
2 is a RAM space where conventional ROM data can be stored;
503 is a space that can be treated as a conventional RAM.

Next, the operation of the microcomputer of this embodiment will be explained.

First, the process up to reading data in the ROM 5 will be described.

When address information is transferred via the ROM address bus 1, the address information is transferred via the control line 51 to the control circuit 30, as shown in e in FIG. 5 of the prior art.
It is transferred in synchronization with the synchronization signal C. As shown in FIG.
1, and transfers the above determination result to the control circuit 401 via the control line 54. Control circuit 4
01 transfers the address information of the control circuit 402 directly to the ROM 5 via the control line 57. The ROM data corresponding to the address information is transferred to the control circuit 403 via the control line 58 in synchronization with the synchronization signal shown in FIG. The control circuit 401 causes the ROM data of the control circuit 403 to be passed through and transferred to the ROM data bus 2 via the control line 60, and is transferred as signal f in FIG. 5.

The ROM data is transferred to the instruction decoder 7 via the control line 61, then decoded and executed.

Further, when the address information is transferred via the RAM address bus 3, the address information is sent via the control line 52 to the control circuit 30 by a synchronization signal a like the signal g in FIG. will be transferred in sync with The control circuit 30 transfers the address information to the control circuit 402 via the control #153, determines whether the address information is the space shown in FIG. The data is transferred to the control circuit 401 via. The control circuit 402 temporarily stores the transferred address information, and the control circuit 401 transfers the data of the control circuit 402 to the control line 57 in synchronization with the synchronization signal C in FIG.
The data is transferred to the ROM 5 via the ROM 5. The ROM data corresponding to the address information is transferred to the control circuit 403 via the control line 58 in synchronization with the synchronization signal shown in FIG. The control circuit 403 temporarily stores the ROM data, and the control circuit 401 transfers the ROM data of the control circuit 403 to the RAM data bus 4 via the control line 59 in synchronization with the synchronization signal d in FIG. Transfer to.

Next, the process up to reading data in the RAM 6 will be described.

If the address information is transferred via the RAM address 3, the address information is transferred to the control circuit 30 via the control line 52 as shown in g in synchronization with the synchronization signal a in FIG. Ru. The control circuit 30 transfers the address information to the control circuit 402 via the control line 53, and also transfers the address information to the R shown in FIG. 3 at 502 and 503.
It is determined that it is an AM space, and the above determination result is applied to the control line 5.
4 to the control circuit 401. Control circuit 401
transfers the address information of the control circuit 402 to the RAM 6 via the control line 55. The RAM data corresponding to the address information is transferred to the control circuit 403 via the control line 56 in synchronization with the synchronization signal d in FIG. The control circuit 401 causes the RAM data of the control circuit 403 to be passed through and transferred to the RAM data bus 4 via the control line 60, and is transferred as shown in the signals in FIG.

In addition, if the address information is transferred via the ROM address bus 1, the address information is sent via the control line 51 to the control circuit 30 by a signal e in synchronization with the synchronization signal C in FIG. It is transferred as follows. The control circuit 30 is
The address information is sent to the control circuit 4 via the control line 53.
02 and the above address information or Figure 3-5.
It is determined that the RAM area can be stored as ROM data shown in 02, and the data is transferred to the control circuit 402. The control circuit 402 temporarily stores the address information, and the control circuit 401 transfers the data of the control circuit 402 to the RAM 6 via the control line 55 in synchronization with the synchronization signal a in FIG. R for the above address information
The AM data is transferred to the RAM in synchronization with the synchronization signal d in FIG.
6 to the control circuit 403 via the control line 56. The control circuit 403 temporarily stores the RAM data, and the control circuit 401 transmits the data of the control circuit 403 via the control line 60 in synchronization with the synchronization signal shown in FIG.
The data is transferred to the ROM data bus 2 as indicated by f in FIG. Then, it is decoded and executed via the control line 61 and the instruction decoder 7.

The process until data is written to RAM6 is shown.

The address information is transferred to the control circuit 30 via the RAM address bus 3 and the control line 52 in synchronization with the synchronization signal a shown in FIG. The control circuit 30 transfers the address information to the control circuit 402 via the control line 53, determines whether the address information is the RAM space shown in 502 and 503 in FIG. It is transferred to the control circuit 401 via the control line 54. Control circuit 40
1 causes the data of the control circuit 402, which is the address information, to be passed through and transferred to the RAM 6 via the control line 55. R
The data written in AM6 is transferred to the control circuit 403 via the RAM data bus 4 and the control line 59 in synchronization with the synchronization signal shown in FIG. 5, as shown in FIG. 5j. The control circuit 401 transfers the data of the control circuit 403 to the RAM 6 via the control line 56, and writes the data.

As described above, according to this embodiment, by making it possible to read data in RAM as ROM data in the prior art, or read out data in ROM as RAM data in the prior art, programs can also be read out in RAM. data, ROM
Reference data can also be stored within the computer, increasing the flexibility and functionality of the computer.

In this embodiment, the synchronization signal in FIG. 5 may be 4-phase, 3-phase, or 2-phase, and the timing at which address information is transferred to the ROM address bus or RAM address bus, or The timing at which the data corresponding to the address information is transferred does not have to be in the format shown in the conventional example, and the data in the ROM is transferred to the RAM data bus or to the RAM in synchronization with a synchronization signal that is interpreted as RAM data. Internal data or R to ROM data bus
As long as the data is transferred synchronously, which is meaningful as OM data, it does not matter what timing the data is transferred.

Effects of the Invention As described above, according to the present invention, data in RAM can be RO
By providing a mechanism that can transfer data in ROM to the M data bus to the RAM data bus, data in RAM can be executed as conventional ROM data, that is, a program, and the program can be edited, modified, added, etc. It is possible to realize an excellent microcomputer that can easily perform this process and also store reference data in a ROM.

3 is an address space layout diagram, FIG. 4 is a memory configuration diagram of a conventional technology, and FIG. 5 is a timing chart for reading and writing data in RAM and ROM.

1...ROM address bus, 2...R
OM data bus, 3...RAM address bus,
4...RAM data bus, 5...RO
M, 6...RAM,? ...Instruction decoder, 30.40 ...Control circuit, 8゜9, 10
, 11. 12,51.52.53,54゜55.56
,57.58,59,60.61...control line,
402.403...- Control circuit that can store time,
401... Control circuit that controls 402 and 403, 501... ROM address space, 502...
...RAM address space that can store ROM data of the prior art, 503... RAM address space that has the same purpose as the prior art.

Name of agent: Patent attorney Shigetaka Awano and one other person C’) Is (/’l scary figure Guq Q a] size

Claims (3)

[Claims] (1) Separated into a storage area for program data and a data area such as a work area and variable area during program execution,
and the instruction word length and data word length are equal, the instruction and data can be accessed in parallel at the same time, a part of the storage area for the program data is constituted by a ROM, and the storage area for the program data is a ROM. 1. A microcomputer characterized in that the remaining part and a data area are made up of a RAM, and the data stored in the RAM can be executed as program data. (2) A RAM address bus and a RAM data bus are connected to the RAM, and a ROM address bus and a ROM data bus are connected to the ROM, and the RAM can be accessed by the RAM address bus or the RAM data bus. R.O.
This is possible by transferring address information via the RAM address bus or the ROM address bus;
Regarding the data stored in the address space and the RAM address space, a single piece of data is assigned to one address, and this causes the address to be transferred from the RAM address bus or the ROM address bus. The three areas can be accessed by having a circuit that can determine, based on information, whether the ROM is the ROM, the RAM in which a program is stored, or the RAM is a data storage area. microcomputer. (3) When accessing data in the ROM address space via the RAM address bus and the ROM address bus, the ROM address bus or the RA
A first step for determining whether the address information of the M address bus is within the ROM address space or the RAM address space.
a control circuit, and based on the determination of the first control circuit, when the address information is transferred via the ROM address bus, it gives a meaning to the ROM data bus that it is ROM data. The address information is transferred in synchronization with a synchronization signal, or when the address information is transferred via the RAM address bus, it is transferred to the RAM data bus in synchronization with a synchronization signal that indicates that it is RAM data. has a second control circuit capable of
Further, when accessing data in the RAM address space, if address information is transferred via the ROM address bus, the second control circuit transfers the When RAM data corresponding to address information is transferred to the ROM data bus in synchronization with a synchronization signal that is interpreted as ROM data, and when the address information is transferred via the RAM address bus, Based on the determination of the first control circuit, the RAM data corresponding to the address information is sent from the second judgment circuit to the RAM data bus in synchronization with a synchronization signal that is interpreted as RAM data. A microcomputer equipped with an instruction decoder capable of decoding the data transferred and transferred to the ROM data bus as a program.