JPH0827714B2 - Microcomputer - Google Patents

Description

TECHNICAL FIELD The present invention is capable of executing RAM data stored in a work area at the time of executing a program and a data area such as a variable area as a program and storing the RAM data in a ROM. The stored data relates to a microcomputer that can be handled not only as a program but also as data such as variables.

2. Description of the Related Art Conventionally, microcomputers have been controlled by program data stored in ROM.

The operation of the memory circuit of the conventional one-chip microcomputer will be described below.

FIG. 4 shows a memory arrangement of a conventional one-chip microcomputer. In FIG. 4, 1 is a ROM address bus, 2 is a ROM data bus, 3 is a RAM address bus, and 4 is
RAM data bus, 5 ROM, 6 RAM, 7 instruction decoder, 8 control line for transferring information of ROM address bus 1 to ROM 5, 9 control line for transferring data of ROM 5 to ROM data bus 2, 10 Is a control line for transferring the information of the RAM address bus 3 to the RAM 6, and 11 is a control line for transferring the data of the RAM 6 to the RAM data bus 4.

FIG. 5 is a timing chart of reading and writing to the ROM5 and RAM6 according to the conventional technique.

In FIG. 5, a, b, c and d are respective sync signals which are the reference for reading and writing. First, the process in which the program in the ROM 5 is read and executed is shown. ROM5
The address information for reading the data in is output as a signal e in synchronization with the synchronization signal c via the ROM address bus 1 and the control line 8. ROM corresponding to the above address information on the ROM data bus 2 when the above signal e operates
The data of 5 is synchronized with the synchronization signal b like the signal f,
It is transferred to the instruction decoder 7 via the control line 9, the ROM data bus 2 and the control line 12, and is decoded and then executed.

Next, the process until the data in the RAM 6 is read will be shown. Address information for reading the RAM 6 is synchronized with the synchronization signal a via the RAM address bus 3 and the control line 10,
It is output like the signal g. RAM when the above signal g operates
The data of the RAM 6 corresponding to the above address information is synchronized with the synchronizing signal d like the signal h on the data bus 4 and the control line
11, and via the RAM data bus 4.

Furthermore, the process until the data is written in the RAM 6 is shown. Address information for writing data to RAM6,
The signal i is output via the RAM address bus 3 and the control line 10 in synchronization with the synchronizing signal a. When the signal i is operated, the data to be written to the RAM data bus 4 is transferred to the signal j.
If the transfer is performed in synchronization with the synchronization signal b as shown in
It is sent to the RAM 6 via 11 and writing is performed.

However, in the above conventional configuration, the ROM data and the RAM data are clearly separated, the data in the ROM area is used as a program, and the ROM data cannot be directly transferred to the RAM data bus. In addition, since the data in the RAM storage area cannot be transferred to the ROM data bus as ROM data like the above ROM data,
There was a problem that the program could not be stored.

The present invention solves the above-mentioned conventional problems, and
RAM data can be transferred to the ROM data bus even when accessing data in the area, and ROM data can be transferred to the RAM data bus even when accessing data in the ROM area, providing flexibility and versatility in data usage. The purpose is to provide a microcomputer having a.

Means for Solving the Problems To achieve this object, the microcomputer of the present invention assigns one data to one address for the data in the ROM and the RAM, and the same address is assigned to the ROM and RAM spaces. , And whether the ROM address space is the ROM address space or the RAM address space is determined by the first address.
From either M address bus or RAM address bus,
A first control circuit is provided which can make a second determination as to whether or not the address information has been sent, and the first control circuit comprises:
The first and second determination results are transferred to the second control circuit, and the second control circuit stores data corresponding to the address information based on the first and second determination results. When the address information is sent from the ROM address bus, it is transferred to the ROM data bus in synchronization with a synchronization signal that is meant as ROM data, and the address information is sent from the RAM address bus. In this case, the RAM data is transferred to the RAM data bus in synchronization with a synchronization signal that is meant as the RAM data.

Operation With this configuration, the data in RAM and ROM can be handled without distinction, so the data in RAM can be decoded and executed in the same way as the program in ROM, and the data in ROM can It can be read and referenced in the same manner as.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 show the memory circuit of the microcomputer of the embodiment of the present invention, and FIG. 3 is a conceptual diagram showing the address space of the memory of the computer.

1 and 2, 1 is a ROM address bus, 2
Is a ROM data bus, 3 is a RAM address bus, 4 is a RAM data bus, 5 is a ROM, and 6 is a RAM. 7 is an instruction decoder, 30
Transfers address information to the second control circuit 40, and
A first control circuit for determining whether the transfer is made from the ROM address bus 1 or the RAM address bus 3, 40
Transfers the address information from the first control circuit to ROM5, RAM6, and reads the read data from ROM data bus 2, R6.
A second control circuit that transfers to either of the AM data buses 4,
Reference numeral 51 is a control line for transferring the ROM address information to the first control circuit 30, 52 is a control line for transferring the RAM address information to the first control circuit 30, and 53 is a transfer line for the address information to the second control circuit 40. A control line, 54 is a control line for transferring the result determined by the first control circuit 30 to the second control circuit 40, 55 is a control line for transferring the address information from the second control circuit 40 to the RAM 6,
56 is a control line for transferring RAM data between the RAM and the second control circuit 40, 57 is a control line for transferring address information to the ROM 5, 58 is a control for transferring the data of the ROM 5 to the second control circuit 40 A line, 59 is a control line connecting the RAM data bus 4 and the second control circuit 40, and 60 is a ROM data bus 2 and the second control circuit 40.
Is a control line for connecting the.

Reference numeral 401 is a control circuit for changing the transfer timing of the address information or read data, 402 is a circuit for temporarily storing the address information and transferring it to the ROM5 or RAM6 by the control signal of the control circuit 401, and 403 is the ROM5 Alternatively, it is a circuit for temporarily storing the data read from the RAM 6 and the data to be written to the RAM 6 and transferring the above data to the ROM data bus 2 and the RAM data bus 4 by the control signal of the control circuit 401.

In FIG. 3, 501 is a ROM address space, 502 is a RAM space that can store ROM data of the related art, and 503 is a space that can be handled as RAM of the related art.

Next, regarding the microcomputer of the present embodiment,
The operation will be described.

 First, the process of reading the data in the ROM 5 will be described.

When the address information is transferred via the ROM address bus 1, the address information is transferred via the control line 51.
The signal is transferred to the first control circuit 30 in synchronism with the synchronizing signal c, like the signal e in FIG. 5 of the prior art. The first control circuit 30 sends the address information to the control circuit 402 via the control line 53.
At the same time, the address information is determined to be the space 501 as shown in FIG. 3, and the determination result is transferred to the control circuit 401 via the control line 54. Control circuit 4
01 transfers the address information of the control circuit 402 to the ROM 5 as it is via the control line 57. The ROM data corresponding to the above address information is transferred to the control circuit 403 via the control line 58 in synchronization with the synchronizing signal b shown in FIG. The ROM data of the control circuit 403 is transferred through the control line 60 to the ROM data bus 2 by the signal from the control circuit 401,
It is transferred as the signal f in FIG.

The ROM data is transferred to the instruction decoder 7 via the control line 61 and then decoded and executed.

When the address information is transferred via the RAM address bus 3, the address information is transferred to the first control circuit 30 via the control line 52 as shown by the signal g in FIG. It is transferred in synchronization with the synchronization signal a. The first control circuit 30 transfers the address information to the control circuit 402 via the control line 53, and the address information is transferred to the control circuit 402 shown in FIG.
It is determined that the space is indicated by 01, and the above determination result is transferred to the control circuit 401 via the control line 54. Control circuit 402
Temporarily stores the transferred address information, and the control circuit 401 synchronizes the data of the control circuit 402 with the ROM5 via the control line 57 in synchronization with the synchronization signal c in FIG.
Transfer to. The ROM data corresponding to the above address information is synchronized with the synchronization signal b in FIG.
It is transferred to the control circuit 403. The control circuit 403 temporarily stores the ROM data, and, in response to a signal from the control circuit 401, synchronizes the ROM data of the control circuit 403 with the RAM through the control line 59 in synchronization with the synchronization signal d of FIG. Transfer to the data bus 4.

 Next, a process of reading the data in the RAM 6 will be described.

When the address information is transferred via the RAM address bus 3, the address information is transferred to the first control circuit 30 via the control line 52 in synchronization with the synchronization signal a shown in FIG.
It is transferred as signal g. The first control circuit 30 transfers the address information to the control circuit 402 via the control line 53, and determines that the address information is the RAM space indicated by 502 and 503 in FIG. The determination result is transferred to the control circuit 401 via the control line 54. The control circuit 401 is
The address information of the control circuit 402 is transferred to R via the control line 55.
Transfer to AM6. The RAM data corresponding to the address information is transferred to the control circuit 403 via the control line 56 in synchronization with the synchronization signal d shown in FIG. A signal from the control circuit 401 causes the RAM data of the control circuit 403 to pass through the RAM data bus 4 via the control line 59, and is transferred as a signal h in FIG.

Further, when the address information is transferred via the ROM address bus 1, the address information is transferred to the first control circuit 30 via the control line 51 to the synchronization signal c in FIG.
Is transferred in synchronization with the signal e. First control circuit
30 transfers the address information to the control circuit 402 via the control line 53, and determines that the address information is a RAM area that can be stored as ROM data indicated by 502 in FIG. Transfer to the control circuit 402. Control circuit 4
02 temporarily stores the address information, and the control circuit 401 synchronizes with the synchronization signal a in FIG.
6, the data of the control circuit 402 is transferred via the control line 55. RAM data corresponding to the address information is transferred from the RAM 6 to the control circuit 403 via the control line 56 in synchronization with the synchronization signal d shown in FIG. The control circuit 403 temporarily stores the RAM data, and in accordance with the signal from the control circuit 401, synchronizes the data of the control circuit 403 with the ROM data bus via the control line 60 in synchronization with the synchronization signal b of FIG. 2 is transferred as shown in FIG. Then, the decoding is executed via the control line 61 and the instruction decoder 7.

Next, a process until data is written in the RAM 6 will be shown.

Address information is transferred to the first control circuit 30 via the RAM address bus 3 and the control line 52 in synchronization with the synchronization signal a shown in FIG. The first control circuit 30 transfers the address information to the control circuit 402 via the control line 53, and the address information is stored in the RAMs 502 and 503 shown in FIG.
It is determined that it is a space, and the determination result is transferred to the control circuit 401 via the control line 54. The control circuit 401 transfers the data of the control circuit 402, which is the address information, to the RAM 6 through the control line 55. The data written in the RAM 6 is transferred to the fifth via the RAM data bus 4 and the control line 59.
The signal is transferred to the control circuit 403 as a signal j in FIG. 5 in synchronization with the synchronizing signal b in the figure. In response to a signal from the control circuit 401, the data of the control circuit 403 is transferred to the RAM 6 via the control line 56.
And is written to.

As described above, according to the present embodiment, the data in the RAM can be read as the ROM data of the conventional technique, or the data in the ROM can be read as the RAM data of the conventional technique. The reference data can be stored in the data and the ROM, and the flexibility and function as a computer can be increased.

In this embodiment, the sync signal in FIG.
Although it is assumed that the phases are three phases or two phases, the timing at which the address information is transferred to the ROM address bus and the RAM address bus, or the timing at which the data corresponding to the address information is transferred is the same as in the conventional example. The data in the ROM does not have to be in the format shown, but the data in the ROM can be synchronized to the RAM data bus or the data in the RAM can be synchronized to the ROM data bus in synchronization with the synchronization signal that is defined as the RAM data. If it is transferred at any time, it does not matter what kind of timing is transferred.

As described above, according to the present invention, the mechanism for transferring the data in the RAM to the ROM data bus and the data in the ROM to the RAM data bus is provided.
Data, that is, it can be executed as a program, and
It is possible to realize an excellent microcomputer capable of easily editing, modifying, adding, etc. of the program and storing the reference data in the ROM.

[Brief description of drawings]

1 and 2 are memory block diagrams of the microcomputer in this embodiment, FIG. 3 is an address space layout diagram, and FIG.
FIG. 5 is a memory configuration diagram of a conventional technique, and FIG. 5 is a timing chart of reading and writing data in RAM and ROM. 1 ... ROM address bus, 2 ... ROM data bus, 3 ...
RAM address bus, 4 ... RAM data bus, 5 ... ROM,
6 ... RAM, 7 ... instruction decoder, 30 ... first control circuit, 40 ... second control circuit, 8,9,10,11,12,51,52,53,54,
55 ... RAM address space that can store ROM data, 503 ... RAM address space for the same purpose as the conventional technology.

Claims (1)

[Claims] 1. A RAM address bus and a ROM address bus are connected, and it is determined whether the RAM address bus or the address information obtained from the ROM address bus indicates a RAM address space or a ROM address space. A first control circuit outputting as a control signal, and the address information is transferred to either a RAM or a ROM based on the control signal output from the first control circuit, and the address in the RAM or the ROM is transferred. The data corresponding to the information is read out, and this data is transferred to the RAM data bus or the ROM.
By providing the second control circuit for transferring to the data bus, the data stored in the RAM can be transferred to either the RAM data bus or the ROM data bus, and the data stored in the ROM is also stored. A microcomputer capable of transferring data to either the RAM data bus or the ROM data bus.