JPH0659971A - Memory reader - Google Patents

Abstract

PURPOSE:To make it possible to directly read out a machine instruction and RAM data respectively by an instruction reading control device and a RAM data reading control device. CONSTITUTION:The machine instruction reading control device 5 sends transfer and reading requests to/from a control circuit 12 for controlling an address in which RAM data are written to a read/write control device 6. The device 6 sends a read permission signal, the control circuit 12 transfers the address to a RAM data address bus 3 and RAM data are read out to a machine instruction reading control device 5 through a RAM data bus 4. The device 6 sends transfer and reading requests to/from a control circuit 11 for controlling an address in which a machine instruction is written to the device 5. The device 5 sends a read permission signal, the circuit 11 transfers the address to a machine instruction address bus 1 and the machine instruction is read out to the device 6 through a machine instruction data bus 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory reading device of a one-chip microcomputer in which a machine instruction read control device can directly read RAM data and a RAM data read / write control device can directly read machine instructions. Is.

[0002]

2. Description of the Related Art A memory reading device in a conventional one-chip microcomputer will be described below.

FIG. 2 shows the configuration of a conventional memory reading device. FIG. 3 shows a memory reading device which is an improvement of FIG.

In FIG. 2, 5 is a machine instruction read control device, 6 is a RAM data read / write control device, 20 is a machine instruction storage device, 21 is a RAM data storage device, 2
2 is an address bus and 23 is a data bus.

In FIG. 3, 1 is a machine instruction address bus, 2 is a machine instruction data bus, 3 is a RAM data address bus, 4 is a RAM data data bus, 5 is a machine instruction read control device, and 6 is a RAM. A data read / write controller, 20 is a machine instruction storage device, and 21 is a RAM data storage device.

The operation of the memory reading device configured as described above will be described below.

In the conventional memory reading device as shown in FIG. 2, the machine instruction read control device 5 transfers the read address of the machine instruction to the address bus 22, and the data bus 23 stores the machine instruction in the storage device 20. Read the machine instructions. Further, the RAM data read / write control device 6
Transfers the address of the RAM data to the address bus 22 so that the RAM data storage device 2 is transferred from the data bus 23.
Read and write to 1.

In the above configuration, since the address bus 22 and the data bus 23 are shared, the machine instruction read control device 5 and the RAM data read / write control device 6 cannot simultaneously read from and write to the storage device. , Was inefficient.

Therefore, a memory reading device as shown in FIG. 3 which is an improvement of FIG. 2 has been proposed. As a result, the machine instruction read control device 5 and the RAM data read / write control device 6 can read and write in parallel to the machine instruction storage device 20 and the RAM data storage device 21 in parallel. Although the above problem is solved in this way, the machine instruction read control device 5 is connected only to the machine instruction address bus 1, and the RAM data read / write control device 6 is connected only to the RAM data address bus 3. ,
The machine instruction read control device 5 includes a machine instruction storage device 2
Only the machine instructions in 0 can be read out, and the RAM data read / write control device 6 operates in the RAM data storage device 21.
I was only able to read and write the RAM data inside.

Therefore, when the RAM data read / write control device 6 reads a machine instruction written in the machine instruction storage device 20, the machine instruction is once RAM-stored by using a special instruction provided in the one-chip microcomputer. A copy is made to the RAM data area in the data storage device 21, and the RAM data address bus 3 is used as RAM data.
The data was read through the RAM data data bus 4.

In addition, the machine instruction read control device 5 includes
It had no alternative means of reading RAM data.

[0012]

In such a conventional configuration as described above, the machine instruction read control device is directly connected to the RA.
The M data cannot be read, and the RAM data read / write control device has a problem that it cannot directly read the machine instruction.

The present invention improves the above inefficient part,
In addition, in order to solve the conventional problems, a machine instruction read control device and a RAM data read / write control device are provided with a memory read device capable of directly reading the contents of the respective storage devices connected to an address bus. The purpose is to do.

[0014]

In order to solve this problem, a memory reading device of the present invention has a RAM data read request signal line and a response signal line from a machine instruction read control device to a RAM data read / write control device. And RAM
From the data read / write control device to the machine command read control device, a machine command read request signal line and a response signal line are provided.

[0015]

With this configuration, the machine command read control device can directly read the RAM data, and the RAM data read / write control device can directly read the machine command.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a memory reading device in a microcomputer according to an embodiment of the present invention.

In FIG. 1, 1 is a machine instruction address bus, 2 is a machine instruction data bus, 3 is a RAM data address bus, 4 is a RAM data data bus, 5 is a machine instruction read control device, and 6 is a RAM. A data read / write controller, 7 is a machine command read request signal line from the RAM data read / write controller 6 to the machine command read controller 5, 8 is a response signal line to the request signal line 7, and 9 is a machine command read controller 5. From the RAM data read / write control device 6 to the machine command read request signal line 10, 10 is a response signal line to the request signal line 9, and 11 is an enable signal from the response signal line 8 to transfer the address from the RAM data read / write control device 6 to the machine. A control circuit for sending operation to the instruction address bus 1, 12 is a machine instruction read control by a permission signal of the request signal line 9 A control circuit for sending operating the address from location 5 to the RAM data address bus 3.

The operation of the memory reading device of this embodiment having the above-described structure will be described below.

The machine instruction read control device 5 transfers the address in which the machine instruction is written to the machine instruction address bus 1 and reads the machine instruction through the machine instruction data bus 2.

The RAM data read / write control device 6 uses R
The address in which the AM data is written is transferred to the work address bus 3 and the RAM data is read out through the work data bus 4.

When the machine instruction read control device 5 reads the RAM data as a machine instruction, the machine instruction read control device 5 transfers the address in which the RAM data is written to the control circuit 12 and sends a read request signal. It is sent to the RAM data read / write control device 6 through a line 9. In the RAM data read / write control device 6, the read permission is given to the response signal line 10 after the working address bus 3 becomes empty and the address can be transferred.
Through the machine instruction read control device 5 and the control circuit 12. The control circuit 12 transfers the address to the RAM data address bus 3 so that the RAM data is RA.
The data is read by the machine instruction read control device 5 through the M data data bus 4.

When the RAM data read / write control device 6 reads a machine instruction as RAM data, the RAM data read / write control device 6 transfers the address in which the machine instruction is written to the control circuit 11 and makes a read request. Through the signal line 7
Send to. The machine instruction read control device 5 gives a read permission to the RAM data read / write control device 6 and the control circuit 1 through the response signal line 8 after the machine instruction address bus 1 becomes empty and the address becomes transferable.
Send to 1. The control circuit 11 transfers the address to the machine instruction address bus 1, and the machine instruction is read out to the RAM data read / write control device 6 through the machine instruction data bus 2.

[0024]

As described above, according to this embodiment, the machine command read control device has the RAM data read request signal line and the response signal line to the RAM data read / write control device, and the RAM data read / write control. By having the machine command read request signal line and the response signal line from the device to the machine command read control device, the machine command read control device can directly read the RAM data, and the RAM
The data read / write controller can directly read machine instructions.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory reading device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional memory reading device.

FIG. 3 is a block diagram of a conventional memory reading device.

[Explanation of symbols]

 1 Machine instruction address bus 2 Machine instruction data bus 3 RAM data address bus 4 RAM data data bus 5 Machine instruction read control device 6 RAM data read / write control device 7, 9 Request signal line 8, 10 Response signal line 11 , 12 control circuit 20 storage device for machine instruction 21 storage device for RAM data 22 address bus 23 data bus

Claims (2)

[Claims] 1. A machine instruction read control device capable of reading the two memory devices simultaneously and in parallel by separating the two memory devices of the machine instruction and the RAM data in a one-chip microcomputer and the RAM data. A read / write control device, a machine instruction address bus for reading out a machine instruction to the two control devices, and R
A RAM data address bus for reading and writing AM data is connected, and the machine instruction read control device sends a read request signal through a first signal line provided between the machine command read control device and the RAM data read and write control device. R
The AM data read / write control device returns a response signal through a second signal line provided between the AM data read / write control device and the machine command read control device, whereby the machine command read control device sends an address to the RAM data address bus. The RAM data can be transferred and read out, and the RAM data read / write control device sends a read request signal through a third signal line provided between the RAM data read / write control device and the machine command read control device. The machine instruction read control device returns a response signal through a fourth signal line provided between the machine data read / write control device and the RAM data read / write control device so that the RAM data read / write control device transfers an address to the machine instruction address bus. In addition, the memory reading device is characterized by being capable of reading machine command data. 2. A four-signal line is provided between the RAM data control device and the machine command read control device, and the machine command read control device sends a request signal through the first signal line when reading the RAM data. The machine command read control device sends the RAM data address bus and the machine command read control device until the response signal from the RAM data read / write control device is returned via the second signal line. The control circuit provided in
The read address is sent to the AM data address bus on standby, and the RAM data read / write control device sends a request signal through the third signal line when reading a machine command to control the read / write of the RAM data. The device is controlled by a control circuit provided between the machine command address bus and the RAM data read / write control device until a response signal from the machine command read control device is returned through the fourth signal line. 2. The memory read device according to claim 1, wherein transmission of a read address is put on standby on the machine instruction address bus.