JPS61105674A - Image processing device - Google Patents

Abstract

PURPOSE:To realize efficient data transfer by transferring the data between the memory of image processing device and the memory of the host computer to which the device is connected without routing the image memory. CONSTITUTION:An image processor and image memory are connected to two buses, the image processing I/O bus and image memory bus, and a control CPU is connected by the 1st interface circuit. The 2nd interface, which forms interface between the host computer and the 2 buses, is connected to them. This 2nd interface is provided with a switch circuit and a buffer memory which temporarily stores transferred data. When the data transfer is done between the memory of the host computer and the memory of the image processing device, the buffer memory is connected to the image processing device I/O bus; and when the data transfer is done between the memory of the host computer and the image memory of the image processing device, the buffer memory is connected to image memory bus, and data is transferred by using image memory bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image processing apparatus having an interface function with a host computer.

[Technical Background of the Invention] As shown in the third factor, the image processing unit @10 includes an image processing unit 13 including an image processor 11 and an image memory 12, and a controller @CPU 14 that controls the image processing unit 13. . Image processor 11 and image memory 12 are interconnected by internal bus 15 . Control m+cpIJ14 is
It is connected to the internal bus 15 by an interface 19 via a selector channel 18 which is connected to an input/output bus 16 and a DMA bus 17 . An image input/output device (not shown) and various interfaces such as an interface 21 with a host computer 30 are connected to the image memory bus 20 of the image memory 12 . The interface 21 is
It is connected to the DMA bus 32 of the host computer 30 via an interface 31 on the host computer 30 side.

Thus, the image processing device 10 (the image memory 12) and the host computer 30 (the memory 33) are connected through the interface 21.31. Further, a communication interface 40 such as an EIA R8-232-C interface is provided between the DMA bus 32 of the host computer 30 and the input/output bus 16 of the image processing device 10, and the communication interface 40 is provided between the host computer 30 and the image processing device i10. This allows information to be exchanged between the two.

Now, in the system shown in FIG. 3 in which the image processing device 10 is connected to the host computer 30, the host computer 30 performs image processing using the image data in the image memory 2.
may be performed. In such a case, the image memory 12
The image data within is transferred to the memory 33 via the image memory bus 20, interface 21, interface 31, and DMA bus 32.

Host CPU 34 forming the center of host computer 30
is stored in memory 33 (from image memory 12)
Image processing is performed using the image data, and the results are stored in the memory 33. The image processing results in the memory 33 are transferred to the image memory 12 through a route opposite to the above-described data transfer from the image memory 12 to the memory 33. In addition,
When transferring the data described above, the host computer 3
A request to that effect is given from the host CPU 34 of No. 0 to the control CPU 14 in the image processing apparatus 10 via the communication interface 40.

In addition to the image data transfer described above, the system shown in FIG. 3 also performs data transfer between the memory 33 of the host computer 30 and the memory 22 of the image processing device 10, such as down-line loading of programs. It will be done. In this case, a request to that effect is sent from the tfiJmcPIJ 14 to the host CPU 34 via the communication interface 40. As a result, the host CPU 34 activates the interface 31. The interface 31 transfers program data (for the image processing unit [10]) in the memory 33 to the image memory 12 via the interface 21 of the image processing device 10 and the image memory bus 20. When the program transfer to the image memory 12 is completed, the host CP
U 34 is controlled via communication interface 40.
P U 14 shall be notified accordingly. This causes the control CPU 14 to activate the selector channel 18 via the input/output bus 16. The selector channel 18 takes in program data in the image memory 12 via the interface 19 and the internal bus 15, and transfers the program data to the memory 22 via the DMA bus 17.

[Problems with back shell technology] As mentioned above, in conventional image processing devices, data transfer such as program data between the memory of the device and the memory of the host computer to which the device is connected is performed using the image memory. had to be done through. As is well known, image data and program data have different data structures.

Therefore, when transferring program data via the image memory, it is necessary to convert the data structure, which is a problem.

[Object of the Invention] This invention has been made in view of the above circumstances, and its object is to enable data transfer between the memory of an image processing device and the memory of a host computer to which the device is connected via the image memory. An object of the present invention is to provide an image processing device that can perform image processing efficiently without causing any problems.

Another object of the present invention is to perform data transfer between the memory of the image processing device and the memory of the host computer and between the image memory of the image processing device and the memory of the host computer using a common interface. An object of the present invention is to provide an image processing device that uses

[Summary of the Invention] In the present invention, an image processor and an image memory are connected to two buses: an image processing device input/output bus and an image memory bus. A control CPU that controls the image processing unit including the image processor and image memory is connected to the image processing device input/output bus through a first interface circuit.

Further, a second interface circuit is connected to the image processing device input/output bus and the image memory bus, which forms an interface with these two buses and the host computer. This second interface circuit includes a buffer memory for temporarily storing transfer data between the host computer and the image processing equipment output bus, as well as transfer data between the host computer and the image memory bus, and A switch circuit is provided for switching connection to either the image processing device input/output bus or the image memory bus. Therefore, in the case of data transfer between the memory of the host computer and the memory of the image processing device, the buffer memory is connected to the image processing device input/output bus side, and the data is transferred using the image processing device input/output bus. will be carried out.

Further, in the case of data transfer between the memory of the host computer and the image memory of the image processing apparatus, the buffer memory is connected to the image memory bus side, and data transfer is performed using the image memory bus.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

Note that the same parts as in FIG. 3 are given the same reference numerals and detailed explanations are omitted. FIG. 1 shows the configuration of an image processing system. 50 is provided with an image processing section 53 including an image processor 51 and an image memory 52 in addition to the control CPU 14, memory 22, etc. shown in FIG. Image processor 51 and image memory 52 are connected to image processor input/output bus 54 and image memory bus 55 (unlike JLII image processor 11 and image memory 12 of FIG. 3). A control CPU 14 is connected to the image processing device input/output bus 54 via an interface 56 .

Further, an image input/output device (not shown) is connected to the image memory bus 55. Furthermore, the image processing device input/output bus 54 and the image memory bus 55 include these two buses 54.
55 and a host interface 57 forming an interface with the host computer 70. This host interface 57 is connected to the D'MAMA bus 32 of the host computer 70 via an interface 71 (to the image processing unit @SO) on the host computer 70 side.

FIG. 2 shows the configuration of the host interface 57 shown in FIG. 1. Reference numeral 81 is a control section having a data input/output control function and controlling the entire interface 57. 82 is an interface section with the image processing device input/output bus 54, 83 is an interface section with the image memory bus 55, and 84 is an interface section 84 with the host computer 70 side interface 71. 85
is a buffer memory connected to the interface section 84;
A switch circuit 86 connects the buffer memory 85 to either one of the interface sections 82 and 83 according to instructions from the control section 81.

Next, the operation of one embodiment of the present invention will be explained using the case of downline loading as an example.

When the power of the image processing device 50 is turned on, the control m+cpU
14 IPL (Initial Program Loader) is activated. As a result, the control CP Ll 14 sends a downline loading request to the host interface 57 via the interface 5G and the image processing device input/output bus 54. The downline loading request sent to the host interface 57 is transmitted to the control section 81 via the interface section 82 within the same interface 57. The control unit 81 then transmits the downline loading request from the control CP (J 14) to the interface unit 84 and the host computer 10.
The data is transmitted to the host CPU 34 via the side interface 71 and the DMA bus 32.

When the host CP Ll 34 in the host computer 70 receives the downline loading request from the host interface 57, it sends the downline loading mode command and start command to the image processing device 50 via the DMA bus 32 and the interface 11.
The data is sequentially sent to the host interface 57 of. The above command is then transmitted to the control section 81 via the interface section 84 within the host interface 51. The control unit 81 controls the host computer 1
The downline loading mode command from 0 (host CPU 34 within) is held internally. The above-mentioned downline loading mode command performs a downline loading operation in the memory 33 of the host computer 70.
Specify the memory start address and transfer amount.

When the control unit 81 receives a start command from the host computer 70 (the host CPU 34 of the host computer 70), the control unit 81 uses the path of the interface unit 84, the interface 71, and the DMA bus 32 to load the memory 33 specified by the downline loading mode command. The program data of the designated mother (or the capacity of the buffer memory 85) is read out in order from the start address. The program data read from the memory 33 is transferred to the host interface 57 via the DMA bus 32 and the interface 71, and is buffered in the buffer memory 85 via the interface section 84 within the interface 57.

The control unit 81 of the host interface 57 controls the switch circuit 86 when one piece of program data specified by the downline loading mode command is buffered in the buffer memory 85 (or when the buffer memory 85 becomes full). buffer memory 85
is connected to the interface section 82 side. The control unit 81 then controls the control t[I
An interrupt is sent to the cPU 14 to indicate that downline loading is possible. Therefore, the control unit 81 controls c p
When an interrupt is accepted by U 14, the program data buffered in the buffer memory 85 is transferred at a constant transfer rate (bus cycle of the image processing device input/output bus 54) via the switch circuit 86 and the interface section 82. The data are sequentially sent onto the image processing device input/output bus 54. The program data sent to the image processing device input/output bus 54 is transmitted to the control CP which operates according to the IPL.
Under the control of U 14, interface 56, control CP
is loaded into memory 22 via U 14 and DMA bus 17. If the buffer memory 85 is empty and the transfer of the amount of program data specified by the downline loading mode command has not been completed, the control unit 81 of the host interface 51 performs the above-described operation for the subsequent program data. Do it again. In this way, data is transferred from the memory 33 of the host computer 70 to the memory 22 of the image processing device 50.
Downline loading to the image memory 52 is performed without going through the image memory 52.

Therefore, according to this embodiment, complicated processing such as converting the data structure of program data to suit the image memory becomes unnecessary. In addition, downline loading is performed simply by sending a downline loading request and commands for downline loading operations to the host interface 57, which eliminates the need for complicated procedures via communication interfaces as in the past. No longer needed. This means that the host interface 57 is connected to the image processing device input/output bus 54 and the interface 5.
6 to the control CPU 14, and also to the host CPU 34 via the interface 71 and the DMA bus 32. Note that the memory 33 of the host computer 70 and the image processing device 50.

Data transfer to/from the memory 22 is applicable not only to the above-mentioned downline loading.

Next, the operation in the case of image data transfer will be explained.

The host CPU 34 of the host computer 70 is one
When image data needs to be transferred, image data input/output mode commands, input/output commands, and start commands are transferred to the DMA bus 32 and interface 7.
1 via the host interface 57 of the image processing device 50
Sequentially. The above command is then transmitted to the control section 81 via the interface section 84 within the host interface 57. The image data input/output mode command specifies the image data transfer operation between the memory 33 of the host computer 70 and the image memory 52 of the image processing device 50, the memory start address in the memory 33 and the image memory 52, and the transfer amount. do. The input/output command also specifies the direction of image data transfer.

When the control unit 81 receives a start command from the host computer 70 (host CPLJ 34 thereof) following the image data input/output mode command and input/output command, it controls the transfer of image data. If input is specified, the control section 81 controls the interface section 84, interface 71 and D.
The above image data input/output mode and
From the start address of the memory 33 specified by the command, the specified amount (or buffer memory 85
(capacity) of image data is read out. The image data read from the memory 33 is transferred to the host interface 57 via the DMA bus 32 and the interface 71, and is buffered in the buffer memory 85 via the interface unit 84 within the interface 57.

When the image data of a circle specified by the image data input/output mode command is buffered in the buffer memory 85 (or when the buffer memory 85 becomes full), the control unit 81 of the host interface 57 turns on the switch circuit 86. The buffer memory 85 is controlled to be connected to the interface section 83 side. And the control section 81 is
The image data buffered in the buffer memory 85 is sequentially transferred to the image memory 52 via the switch circuit 86, the interface section 83, and the image memory bus 55, and the image data specified by the image data input/output mode command is Starting from the start address of the memory 52, image data corresponding to the specified storage capacity (or the capacity of the buffer memory 85) is written. If it is an output designation, the image data in the image memory 52 is transferred to the memory 33 of the host computer 70, contrary to the input designation described above.

[Effects of the Invention] As detailed above, according to the present invention, the following unique effects can be obtained.

(2) Data transfer between the memory of the image processing device and the memory of the host computer to which the device is connected, such as downline loading, can be performed without going through the image memory. Therefore, there is no need to convert the transferred data into a data structure compatible with the image memory, allowing efficient data transfer.

Become.

(2) Data transfer between the memory of the image processing device and the memory of the host computer and data transfer between the image memory of the image processing device and the memory of the host computer can be performed using a common interface.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an image processing system according to an embodiment of the present invention, FIG. 2 is a block configuration diagram of a host interface provided in the image processing apparatus of FIG. 1, and FIG. M3 is a diagram showing a conventional example. It is. ...Image processing device input/output bus, 55...Image memory bus, 57...Host interface, 70...Host computer, 81...Control unit, 85.
...Buffer memory, 86...Switch circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] an image processing section including an image processor and an image memory;
an image processing device input/output bus and an image memory bus that connect the image processor and the image memory; a control CPU that controls the image processing section; a first interface circuit that connects the control CPU and the image processing section; The image processing device input/output bus, the image memory bus, and a second interface circuit forming an interface with the host computer, the second interface circuit providing an interface between the host computer and the image processing device input/output bus. A buffer memory that temporarily stores transfer data and transfer data between the host computer and the image memory bus, and a switch circuit that switches and connects the buffer memory to either the image processing device input/output bus or the image memory bus. An image processing device comprising: